fixing delay setup for par12 and hispi, ran for par12

memctrl/phy/byte_lane.v

@@ -192,7 +192,7 @@ dm_single #(
         .din(din_dm_r[3:0]) ,           // parallel data to be sent out
         .tin(tin_dq_r),                 // tristate for data out (sent out earlier than data!) 
         .set_odelay(set_r),             // clk_div synchronous load odelay value from dly_data
-        .ld_odelay(ld_odly_dm)         // clk_div synchronous set odealy value from loaded
+        .ld_odelay(ld_odly_dm)          // clk_div synchronous set odealy value from loaded
 );
 
 `ifdef NOFINEDELAY_DQS

memctrl/phy/dqs_single_nofine.v

@@ -61,8 +61,8 @@ module  dqs_single_nofine #(
     input [7:0] dly_data,
     input [3:0] din,
     input [3:0] tin,
-    input       set_odelay,
-    input       ld_odelay,
+    input       set_odelay, // apply loaded pipeline register data
+    input       ld_odelay,  // load  pipeline register data
     input       set_idelay,
     input       ld_idelay
 );
@@ -113,6 +113,7 @@ IOBUFDS_DCIEN #(
     .IBUFDISABLE(1'b0),
     .I(dqs_data_dly), //dqs_data),
     .T(dqs_tri));
+    
 idelay_nofine # (
     .IODELAY_GRP(IODELAY_GRP),
     .DELAY_VALUE(IDELAY_VALUE>>3),

sensor/pxd_clock.v

@@ -56,8 +56,8 @@ module  pxd_clock #(
     input        rst,            // reset
     input        mclk,           // clock for setting delay values
     input  [7:0] dly_data,       // delay value (3 LSB - fine delay) - @posedge mclk
-    input        set_idelay,     // mclk synchronous load idelay value
-    input        ld_idelay       // mclk synchronous set idealy value
+    input        set_idelay,     // mclk synchronous apply loaded delay values
+    input        ld_idelay       // mclk synchronous load delay value to pipeline register
 );
     wire pxclk_iobuf;
 
@@ -97,8 +97,8 @@ module  pxd_clock #(
     ) pxclk_dly_i(
         .clk          (mclk),
         .rst          (rst),
-        .set          (set_idelay),
-        .ld           (ld_idelay),
+        .set          (set_idelay), // apply loaded delay values
+        .ld           (ld_idelay),  // load delay value to pipeline register
         .delay        (dly_data[7:3]),
         .data_in      (pxclk_iobuf),
         .data_out     (pxclk_in)

sensor/pxd_single.v

@@ -60,9 +60,9 @@ module  pxd_single#(
     input        irst,         // reset @ posedge iclk
     input        mclk,         // clock for setting delay values
     input  [7:0] dly_data,     // delay value (3 LSB - fine delay) - @posedge mclk
-    input        set_idelay,   // mclk synchronous load idelay value
-    input        ld_idelay,    // mclk synchronous set idealy value
-    input  [1:0] quadrant       // select one of 4 90-degree shifts for the data (MT9P0xx) have VACT, HACT shifted from PXD
+    input        set_idelay,   // mclk synchronous apply loaded delay values
+    input        ld_idelay,    // mclk synchronous load delay value to pipeline register
+    input  [1:0] quadrant      // select one of 4 90-degree shifts for the data (MT9P0xx) have VACT, HACT shifted from PXD
 );
     wire pxd_iobuf;
     wire pxd_delayed;
@@ -114,8 +114,8 @@ module  pxd_single#(
     ) pxd_dly_i(
         .clk          (mclk),
         .rst          (mrst),
-        .set          (set_idelay),
-        .ld           (ld_idelay),
+        .set          (set_idelay), // apply loaded delay values
+        .ld           (ld_idelay),  // load delay value to pipeline register
         .delay        (dly_data[7:3]),
         .data_in      (pxd_iobuf),
         .data_out     (pxd_delayed)

sensor/sens_10398.v

@@ -204,7 +204,7 @@ module  sens_10398 #(
     reg         iarst = 0;
     reg         imrst = 0;  // active low 
     reg         rst_mmcm=1; // rst and command - en/dis 
-    reg         ld_idelay=0;
+    reg         apply_idelay=0;
     reg         ignore_embed=0; // do not process sensor data marked as "embedded"
 
 //    wire [14:0] status;
@@ -317,8 +317,8 @@ module  sens_10398 #(
         if      (mrst)                                               ignore_embed <= 0;
         else if (set_ctrl_r && data_r[SENS_CTRL_IGNORE_EMBED + 1])   ignore_embed <= data_r[SENS_CTRL_IGNORE_EMBED]; 
          
-        if  (mrst) ld_idelay <= 0;
-        else       ld_idelay <= set_ctrl_r && data_r[SENS_CTRL_LD_DLY]; 
+        if  (mrst) apply_idelay <= 0;
+        else       apply_idelay <= set_ctrl_r && data_r[SENS_CTRL_LD_DLY]; 
 
         if      (mrst)                                      gp_r[1:0] <= 0;
         else if (set_ctrl_r && data_r[SENS_CTRL_GP0 + 2])   gp_r[1:0] <= data_r[SENS_CTRL_GP0+:2]; 
@@ -482,7 +482,7 @@ module  sens_10398 #(
         .set_lanes_map          (set_lanes_map),          // input 
         .set_fifo_dly           (set_fifo_dly),           // input
         .set_idelay             ({4{set_idelays}}),       // input[3:0] 
-        .ld_idelay              (ld_idelay),              // input
+        .apply_idelay           (apply_idelay),           // input
         .set_clk_phase          (set_iclk_phase),         // input
         .rst_mmcm               (rst_mmcm),               // input
         .ignore_embedded        (ignore_embed),           // input

sensor/sens_103993.v

@@ -690,7 +690,8 @@ module  sens_103993 #(
     
 // end of dummy
 
-    
+// pulldown to detect sensor presense
+//    mpulldown i_snsrxd_pulldown          (sns_rxd);
     // READ RXD    
     ibuf_ibufg #(
         .CAPACITANCE      (PXD_CAPACITANCE),

sensor/sens_103993_clock.v

 /*!
- * <b>Module:</b>sens_hispi_clock
+ * <b>Module:</b>sens_103993_clock
  * @file sens_103993_clock.v
  * @date 2020-12-16  
  * @author Andrey Filippov     

sensor/sens_103993_din.v

 /*!
  * <b>Module:</b>sens_103993_din
- * @file sens_hispi_din.v
+ * @file sens_103993_din.v
  * @date 2020-12-16  
  * @author Andrey Filippov     
  *
@@ -56,13 +56,13 @@ module  sens_103993_din #(
 )(
     input                           mclk,
     input                           mrst,
-    input  [NUMLANES * 8-1:0] dly_data,     // delay value (3 LSB - fine delay) - @posedge mclk
-    input      [NUMLANES-1:0] set_idelay,   // mclk synchronous load idelay value
-    input                           ld_idelay,    // mclk synchronous set idealy value
-    input                           pclk,    // 27 MHz
-//    input                           ipclk,   // 165 MHz
-    input                           ipclk2x, // 330 MHz
-//    input                           irst,    // reset @posedge iclk
+    input  [NUMLANES * 8-1:0] dly_data,         // delay value (3 LSB - fine delay) - @posedge mclk
+    input      [NUMLANES-1:0] set_idelay,       // mclk synchronous load idelay value
+    input                           ld_idelay,  // mclk synchronous apply idelay value
+    input                           pclk,       // 27 MHz
+//    input                           ipclk,    // 165 MHz
+    input                           ipclk2x,    // 330 MHz
+//    input                           irst,     // reset @posedge iclk
     input      [NUMLANES-1:0] din_p,
     input      [NUMLANES-1:0] din_n,
     output [NUMLANES * 10-1:0] dout

sensor/sens_103993_l3.v

 /*!
  * <b>Module:</b>sens_103993_l3
- * @file sens_hispi12l4.v
+ * @file sens_103993_l3.v
  * @date 2015-10-13  
  * @author Andrey Filippov     
  *

sensor/sens_hispi12l4.v

@@ -105,7 +105,7 @@ module  sens_hispi12l4#(
     input                           set_lanes_map,   // set number of physical lane for each logical one
     input                           set_fifo_dly,
     input      [HISPI_NUMLANES-1:0] set_idelay,      // mclk synchronous load idelay value
-    input                           ld_idelay,       // mclk synchronous set idealy value
+    input                           apply_idelay,    // mclk synchronous set idealy value
     input                           set_clk_phase,   // mclk synchronous set idealy value
     input                           rst_mmcm,
     input                           ignore_embedded, // ignore lines with embedded data
@@ -253,7 +253,7 @@ module  sens_hispi12l4#(
         .mrst                   (mrst),                   // input
         .phase                  (dly_data[7:0]),          // input[7:0] 
         .set_phase              (set_clk_phase),          // input
-        .load                   (ld_idelay),              // input
+        .apply_phase            (apply_idelay),           // input
         .rst_mmcm               (rst_mmcm),               // input
         .clp_p                  (sns_clkp),               // input
         .clk_n                  (sns_clkn),               // input
@@ -285,7 +285,7 @@ module  sens_hispi12l4#(
         .mrst         (mrst),        // input
         .dly_data     (dly_data),    // input[31:0] 
         .set_idelay   (set_idelay),  // input[3:0] 
-        .ld_idelay    (ld_idelay),   // input
+        .apply_idelay (apply_idelay),   // input
         .ipclk        (ipclk),       // input
         .ipclk2x      (ipclk2x),     // input
         .irst         (irst),        // input

sensor/sens_hispi_clock.v

@@ -78,7 +78,7 @@ module  sens_hispi_clock#(
     input        mrst,
     input  [7:0] phase,
     input        set_phase,
-    input        load,      // only used when delay, not phase
+    input        apply_phase,      // only used when delay, not phase
     input        rst_mmcm,
     input        clp_p,
     input        clk_n,
@@ -144,8 +144,11 @@ module  sens_hispi_clock#(
             ) clk_dly_i(
                 .clk          (mclk),
                 .rst          (mrst),
-                .set          (set_phase),
-                .ld           (load),
+//                .set          (set_phase), // apply pipeline register
+//                .ld           (load),      // load pipeline register
+/// Seems to be a major old bug may need to be changed in idelay_nofine and idelay_fine_pipe (odelay too?) 
+                .set          (apply_phase), // apply pipeline register
+                .ld           (set_phase),      // load pipeline register
                 .delay        (phase[4:0]),
                 .data_in      (clk_int),
                 .data_out     (clk_in)

sensor/sens_hispi_din.v

@@ -58,7 +58,7 @@ module  sens_hispi_din #(
     input                           mrst,
     input  [HISPI_NUMLANES * 8-1:0] dly_data,     // delay value (3 LSB - fine delay) - @posedge mclk
     input      [HISPI_NUMLANES-1:0] set_idelay,   // mclk synchronous load idelay value
-    input                           ld_idelay,    // mclk synchronous set idealy value
+    input                           apply_idelay,    // mclk synchronous set idealy value
     input                           ipclk,   // 165 MHz
     input                           ipclk2x, // 330 MHz
     input                           irst,    // reset @posedge iclk
@@ -111,8 +111,11 @@ module  sens_hispi_din #(
             ) pxd_dly_i(
                 .clk          (mclk),
                 .rst          (mrst),
-                .set          (set_idelay[i]),
-                .ld           (ld_idelay),
+//                .set          (set_idelay[i]),
+//                .ld           (apply_idelay),
+/// Seems to be a major old bug may need to be changed in idelay_nofine and idelay_fine_pipe (odelay too?) 
+                .set          (apply_idelay),
+                .ld           (set_idelay[i]),
                 .delay        (dly_data[3 + 8*i +: 5]),
                 .data_in      (din[i]),
                 .data_out     (din_dly[i])

sensor/sens_parallel12.v

@@ -191,7 +191,7 @@ module  sens_parallel12 #(
     reg         imrst = 0;
     reg         rst_mmcm=1; // rst and command - en/dis 
     reg  [SENS_CTRL_QUADRANTS_WIDTH-1:0]  quadrants=0; //90-degree shifts for data [1:0], hact [3:2] and vact [5:4], [6] odd/even
-    reg         ld_idelay=0;
+    reg         apply_idelay=0; // ld_idelay=0;
     reg         sel_ext_clk=0; // select clock source from the sensor (0 - use internal clock - to sensor)
 
 
@@ -324,8 +324,8 @@ module  sens_parallel12 #(
         if      (mclk_rst)                                      quadrants <= 0;
         else if (set_ctrl_r && data_r[SENS_CTRL_QUADRANTS_EN])  quadrants <= data_r[SENS_CTRL_QUADRANTS +: SENS_CTRL_QUADRANTS_WIDTH]; 
 
-        if  (mclk_rst) ld_idelay <= 0;
-        else           ld_idelay <= set_ctrl_r && data_r[SENS_CTRL_LD_DLY]; 
+        if  (mclk_rst) apply_idelay <= 0;
+        else           apply_idelay <= set_ctrl_r && data_r[SENS_CTRL_LD_DLY]; 
         
         if  (mclk_rst) set_width_r <= 0;
         else           set_width_r <= {set_width_r[0],cmd_we && (cmd_a== SENSIO_WIDTH)}; 
@@ -485,8 +485,11 @@ module  sens_parallel12 #(
         .irst           (irst),            // input
         .mclk           (mclk),            // input
         .dly_data       (data_r[7:0]),          // input[7:0] 
-        .set_idelay     (set_pxd_delay[0]),// input
-        .ld_idelay      (ld_idelay),       // input
+//        .set_idelay     (set_pxd_delay[0]),// input
+//        .ld_idelay      (ld_idelay),       // input
+/// Seems to be a major old bug may need to be changed in idelay_nofine and idelay_fine_pipe (odelay too?) 
+        .set_idelay     (apply_idelay),// input
+        .ld_idelay      (set_pxd_delay[0]),       // input
         .quadrant       (quadrants[1:0])   // input[1:0] 
     );
     
@@ -531,8 +534,11 @@ module  sens_parallel12 #(
         .irst           (irst),            // input
         .mclk           (mclk),            // input
         .dly_data       (data_r[15:8]),    // input[7:0] 
-        .set_idelay     (set_pxd_delay[0]),// input
-        .ld_idelay      (ld_idelay),       // input
+//        .set_idelay     (set_pxd_delay[0]),// input
+//        .ld_idelay      (ld_idelay),       // input
+/// Seems to be a major old bug may need to be changed in idelay_nofine and idelay_fine_pipe (odelay too?) 
+        .set_idelay     (apply_idelay),// input
+        .ld_idelay      (set_pxd_delay[0]),       // input
         .quadrant       (quadrants[1:0])   // input[1:0] 
     );
 `endif    
@@ -566,8 +572,11 @@ module  sens_parallel12 #(
 //                .dly_data       (data_r[8*((i+2)&3)+:8]), // input[7:0] alternating bytes of 32-bit word
 //                .set_idelay     (set_pxd_delay[(i+2)>>2]),// input 0 for pxd[3:2], 1 for pxd[7:4], 2 for pxd [11:8]
                 .dly_data       (data_r[8 * (i & 3) +: 8]), // input[7:0] alternating bytes of 32-bit word
-                .set_idelay     (set_pxd_delay[i >> 2]),// input 0 for pxd[3:2], 1 for pxd[7:4], 2 for pxd [11:8]
-                .ld_idelay      (ld_idelay),       // input
+//                .set_idelay     (set_pxd_delay[i >> 2]),// input 0 for pxd[3:2], 1 for pxd[7:4], 2 for pxd [11:8]
+//                .ld_idelay      (ld_idelay),       // input
+/// Seems to be a major old bug may need to be changed in idelay_nofine and idelay_fine_pipe (odelay too?) 
+                .set_idelay     (apply_idelay),       // input
+                .ld_idelay      (set_pxd_delay[i >> 2]), // input
                 .quadrant       (quadrants[1:0])   // input[1:0] 
             );
         end
@@ -594,8 +603,12 @@ module  sens_parallel12 #(
         .irst           (irst),           // input
         .mclk           (mclk),           // input
         .dly_data       (data_r[7:0]),    // input[7:0] 
-        .set_idelay     (set_other_delay),// input
-        .ld_idelay      (ld_idelay),      // input
+//        .set_idelay     (set_other_delay),// input
+//        .ld_idelay      (ld_idelay),      // input
+/// Seems to be a major old bug may need to be changed in idelay_nofine and idelay_fine_pipe (odelay too?) 
+        .set_idelay     (apply_idelay),       // input
+        .ld_idelay      (set_other_delay), // input
+        
         .quadrant       (quadrants[3:2])  // input[1:0] 
     );
     
@@ -620,8 +633,11 @@ module  sens_parallel12 #(
         .irst           (irst),            // input
         .mclk           (mclk),          // input
         .dly_data       (data_r[15:8]),  // input[7:0] 
-        .set_idelay     (set_other_delay),// input
-        .ld_idelay      (ld_idelay),     // input
+//        .set_idelay     (set_other_delay),// input
+//        .ld_idelay      (ld_idelay),     // input
+/// Seems to be a major old bug may need to be changed in idelay_nofine and idelay_fine_pipe (odelay too?) 
+        .set_idelay     (apply_idelay),       // input
+        .ld_idelay      (set_other_delay), // input
         .quadrant       (quadrants[5:4]) // input[1:0] 
     );
     // receive clock from sensor
@@ -642,8 +658,11 @@ module  sens_parallel12 #(
         .rst        (mclk_rst),        // input
         .mclk       (mclk),            // input
         .dly_data   (data_r[23:16]),   // input[7:0] 
-        .set_idelay (set_other_delay), // input
-        .ld_idelay  (ld_idelay)        // input
+//        .set_idelay (set_other_delay), // input
+//        .ld_idelay  (ld_idelay)        // input
+/// Seems to be a major old bug may need to be changed in idelay_nofine and idelay_fine_pipe (odelay too?) 
+        .set_idelay     (apply_idelay),       // input
+        .ld_idelay      (set_other_delay) // input
     );
     // generate dclk output
     oddr_ss #(

system_defines.vh

@@ -64,9 +64,10 @@
   `define PRELOAD_BRAMS
   `define DISPLAY_COMPRESSED_DATA  
   // if HISPI is not defined, parallel sensor interface is used for all channels
- `define BOSON 1 /*************** CHANGE here and x393_hispi/x393_parallel/x393_lwir in bitstream tool settings ****************/
+//  `define BOSON 1 /*************** CHANGE here and x393_hispi/x393_parallel/x393_lwir/x393_boson in bitstream tool settings ****************/
 //  `define LWIR /*************** CHANGE here and x393_hispi/x393_parallel/x393_lwir in bitstream tool settings ****************/
 //  `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
+// also change in utilization and timimg summary tools (x393_parallel_utilization.report, ...)
   `ifdef BOSON
   
   `elsif LWIR

timing/camsync393.v

@@ -48,7 +48,7 @@
 //`define GENERATE_TRIG_OVERDUE 1
 `undef GENERATE_TRIG_OVERDUE
 module camsync393       #(
-    parameter CAMSYNC_ADDR =               'h160, //TODO: assign valid address
+    parameter CAMSYNC_ADDR =               'h708, //TODO: assign valid address
     parameter CAMSYNC_MASK =               'h7f8,
     parameter CAMSYNC_MODE =               'h0,
     parameter CAMSYNC_TRIG_SRC =           'h1, // setup trigger source