Changed 'author' to full name

axi/cmprs_afi_mux.v

 /*******************************************************************************
  * Module: cmprs_afi_mux
  * Date:2015-06-26  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Writes comressor data from up to 4 channels to system memory over AXI_HP
  *
  * Copyright (c) 2015 Elphel, Inc.

axi/cmprs_afi_mux_ptr.v

 /*******************************************************************************
  * Module: cmprs_afi_mux_ptr
  * Date:2015-06-28  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Maintain 4-channel chunk pointers (before AXI)
  * Advance 32-byte chunk pointers for each AXI burst and each frame (4*2=8 pointers)
  *

axi/cmprs_afi_mux_ptr_wresp.v

 /*******************************************************************************
  * Module: cmprs_afi_mux_ptr_wresp
  * Date:2015-06-28  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Maintain 4-channel chunk pointers for wrirte response
  * Advance 32-byte chunk pointers for each AXI burst and each frame (4*2=8 pointers)
  *

axi/cmprs_afi_mux_status.v

 /*******************************************************************************
  * Module: cmprs_afi_mux_status
  * Date:2015-06-28  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: prepare and send per-channel chunk pointer information as status
  * Using 4 consecutive locations. Each channel can provide one of the 4 pointers:
  * frame pointer in the write channel, current chunk pointer in the write channel

axi/histogram_saxi.v

 /*******************************************************************************
  * Module: histogram_saxi
  * Date:2015-06-04  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Histograms transfer to the system memory over S_AXI 
  *
  * Copyright (c) 2015 Elphel, Inc.

axi/membridge.v

 /*******************************************************************************
  * Module: membridge
  * Date:2015-04-26  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: bi-directional bridge between system and video memory over axi_hp
  *
  * Copyright (c) 2015 Elphel, Inc.

axi/mul_saxi_wr_chn.v

 /*******************************************************************************
  * Module: mul_saxi_wr_chn
  * Date:2015-07-10  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: One channel of the mult_saxi_wr (read/write common buffer)
  *
  * Copyright (c) 2015 Elphel, Inc .

axi/mult_saxi_wr.v

 /*******************************************************************************
  * Module: mult_saxi_wr
  * Date:2015-07-08  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: send data from up to 4 sources to the system memory over S_AXI.
  * Each source should have a 32-bit wide buffer running at the same clock (mclk).
  * Buffer should contain at least burst size (4,8,16,32,64 bytes)

axi/mult_saxi_wr_pointers.v

 /*******************************************************************************
  * Module: mult_saxi_wr_pointers
  * Date:2015-07-10  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Process pointers for mult_saxi_wr
  *
  * Copyright (c) 2015 Elphel, Inc .

axi_hp_clk.v

 /*******************************************************************************
  * Module: axi_hp_clk
  * Date:2015-04-27  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Generate global clock for axi_hp
  *
  * Copyright (c) 2015 Elphel, Inc.

cmd_mux.v

 /*******************************************************************************
  * Module: cmd_mux
  * Date:2015-01-11  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Command multiplexer between AXI and frame-based command sequencer
  *
  * Copyright (c) 2015 Elphel, Inc.

cmd_readback.v

 /*******************************************************************************
  * Module: cmd_readback
  * Date:2015-05-05  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Store control register data and readback
  *
  * Copyright (c) 2015 Elphel, Inc.

compressor_jp/cmprs_buf_average.v

 /*******************************************************************************
  * Module: cmprs_buf_average
  * Date:2015-06-14  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Saves Y and C components to buffers, caculates averages
  * during write, then subtracts them during read and provides to
  * the after DCT to restore DC

compressor_jp/cmprs_cmd_decode.v

 /*******************************************************************************
  * Module: cmprs_cmd_decode
  * Date:2015-06-23  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Decode compressor command/modes, reclock some signals
  *
  * Copyright (c) 2015 Elphel, Inc.

compressor_jp/cmprs_frame_sync.v

 /*******************************************************************************
  * Module: cmprs_frame_sync
  * Date:2015-06-23  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Synchronizes memory channels (sensor and compressor)
  *
  * Copyright (c) 2015 Elphel, Inc.

compressor_jp/cmprs_macroblock_buf_iface.v

 /*******************************************************************************
  * Module: cmprs_macroblock_buf_iface
  * Date:2015-06-11  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Communicates with compressor memory buffer, generates pixel
  * stream matching selected color mode, accommodates for the buffer latency,
  * acts as a pacemaker for the whole compressor (next stages are able to keep up).

compressor_jp/cmprs_out_fifo.v

 /*******************************************************************************
  * Module: cmprs_out_fifo
  * Date:2015-06-25  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Compressor output FIFO
  *
  * Copyright (c) 2015 Elphel, Inc.

compressor_jp/cmprs_pixel_buf_iface.v

 /*******************************************************************************
  * Module: cmprs_pixel_buf_iface
  * Date:2015-06-11  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Communicates with compressor memory buffer, generates pixel
  * stream matching selected color mode, accommodates for the buffer latency,
  * acts as a pacemaker for the whole compressor (next stages are able to keep up).

compressor_jp/cmprs_status.v

 /*******************************************************************************
  * Module: cmprs_status
  * Date:2015-06-25  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Generate compressor status word
  *
  * Copyright (c) 2015 Elphel, Inc.

compressor_jp/cmprs_tile_mode2_decode.v

 /*******************************************************************************
  * Module: cmprs_tile_mode2_decode
  * Date:2015-06-14  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Decode mode parameters, registered at pre-start of the macroblock
  * data to color conversion module
  *

compressor_jp/cmprs_tile_mode_decode.v

 /*******************************************************************************
  * Module: cmprs_tile_mode_decode
  * Date:2015-06-14  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Decode tile/macroblocks parameters from compressor type
  *
  * Copyright (c) 2015 Elphel, Inc.

compressor_jp/color_proc393.v

 /*******************************************************************************
  * Module: color_proc393
  * Date:2015-06-10  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Color processor for JPEG 4:2:0/JP4
  * Updating from the earlier 2002-2010 version
  *

compressor_jp/csconvert.v

 /*******************************************************************************
  * Module: csconvert
  * Date:2015-06-14  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Color space convert: combine differnt color modes
  *
  * Copyright (c) 2015 Elphel, Inc.

compressor_jp/csconvert_jp4.v

 /*******************************************************************************
  * Module: csconvert_jp4
  * Date:2015-06-10  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Color conversion for JP4 mode
  *
  * Copyright (c) 2015 Elphel, Inc.

compressor_jp/csconvert_jp4diff.v

 /*******************************************************************************
  * Module: csconvert_jp4diff
  * Date:2015-06-10  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Color conversion for JP4 differential
  *
  * Copyright (c) 2015 Elphel, Inc.

compressor_jp/csconvert_mono.v

 /*******************************************************************************
  * Module: csconvert_mono
  * Date:2015-06-10  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Convert JPEG monochrome
  *
  * Copyright (c) 2015 Elphel, Inc.

compressor_jp/dcc_sync393.v

 /*******************************************************************************
  * Module: dcc_sync393
  * Date:2015-06-17  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Synchronises output of DC components
  * Syncronizes dcc data with dma1 output, adds 16..31 16-bit zero words for Axis DMA
  * Was not used in late NC353 camera (DMA channel used fro IMU logger)

compressor_jp/jp_channel.v

 /*******************************************************************************
  * Module: jp_channel
  * Date:2015-06-10  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Top module of JPEG/JP4 compressor channel
  *
  * Copyright (c) 2015 Elphel, Inc.

includes/x393_cur_params_target.vh

 /*******************************************************************************
  * File: x393_cur_params_target.vh
  * Date:2015-02-07  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Memory controller parameters that need adjustment during training
  * Target ,pde
  * Copyright (c) 2015 Elphel, Inc.

includes/x393_localparams.vh

 /*******************************************************************************
  * File: x393_localparams.vh
  * Date:2015-02-07  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Local parameters for simulation of the x393
  *
  * Copyright (c) 2015 Elphel, Inc.

includes/x393_mcontr_encode_cmd.vh

 /*******************************************************************************
  * File: x393_mcontr_encode_cmd.vh
  * Date:2015-02-09  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Functions used to encode memory controller sequences
  *
  * Copyright (c) 2015 Elphel, Inc.

includes/x393_parameters.vh

 /*******************************************************************************
  * File: x393_parameters.vh
  * Date:2015-02-07  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Parameters for the x393 (simulation and implementation)
  *
  * Copyright (c) 2015 Elphel, Inc.

includes/x393_simulation_parameters.vh

  /*******************************************************************************
  * File: x393_simulation_parameters.vh
  * Date:2015-02-07  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Simulation-specific parameters for the x393
  *
  * Copyright (c) 2015 Elphel, Inc.

includes/x393_tasks01.vh

  /*******************************************************************************
  * File: x393_tasks01.vh
  * Date:2015-02-07  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Simulation tasks for the x393 (low level)
  *
  * Copyright (c) 2015 Elphel, Inc.

includes/x393_tasks_afi.vh

  /*******************************************************************************
  * File: x393_tasks_afi.vh
  * Date:2015-02-07  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Simulation tasks for the AXI_HP (AFI)
  *
  * Copyright (c) 2015 Elphel, Inc.

includes/x393_tasks_mcntrl_buffers.vh

  /*******************************************************************************
  * File: x393_tasks_mcntrl_buffers.vh
  * Date:2015-02-07  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Simulation tasks for software reading/writing (with test patterns)
  * of the block buffers.
  *

includes/x393_tasks_mcntrl_en_dis_priority.vh

  /*******************************************************************************
  * File: x393_tasks_mcntrl_en_dis_priority.vh
  * Date:2015-02-07  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Simulation tasks for software reading/writing (with test patterns)
  * of the block buffers.
  *

includes/x393_tasks_mcntrl_timing.vh

  /*******************************************************************************
  * File: x393_tasks_mcntrl_timing.vh
  * Date:2015-02-07  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Simulation tasks for programming I/O delays and other timing
  * parameters in the memory controller
  *

includes/x393_tasks_pio_sequences.vh

  /*******************************************************************************
  * File: x393_tasks_pio_sequences.vh
  * Date:2015-02-07  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Simulation tasks for programming memory transaction
  * sequences (controlles by PS)
  *

includes/x393_tasks_ps_pio.vh

  /*******************************************************************************
  * File: x393_tasks_ps_pio.vh
  * Date:2015-02-07  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Simulation tasks for mcntrl_ps_pio module (launching software
  * - programmed memory transaction sequences)
  *

includes/x393_tasks_status.vh

  /*******************************************************************************
  * File: x393_status.vh
  * Date:2015-02-07  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Simulation tasks for the x393 related to status
  *
  * Copyright (c) 2015 Elphel, Inc.

logger/buf_xclk_mclk16_393.v

 /*******************************************************************************
  * Module: buf_xclk_mclk16_393
  * Date:2015-07-06  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: move data from xclk to mclk domain
  *
  * Copyright (c) 2015 Elphel, Inc.

logger/event_logger.v

 /*******************************************************************************
  * Module: event_logger
  * Date:2015-07-06  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: top module of the event logger (ported from imu_logger)
  *
  * Copyright (c) 2015 Elphel, Inc.

logger/imu_exttime393.v

 /*******************************************************************************
  * Module: imu_exttime393
  * Date:2015-07-06  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: get external timestamp (for image)
  *
  * Copyright (c) 2015 Elphel, Inc.

logger/imu_message393.v

 /*******************************************************************************
  * Module: imu_message393
  * Date:2015-07-06  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: 
  *
  * Copyright (c) 2015 Elphel, Inc.

logger/imu_spi393.v

 /*******************************************************************************
  * Module: imu_spi393
  * Date:2015-07-06  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: SPI interface for the IMU
  *
  * Copyright (c) 2015 Elphel, Inc.

logger/imu_timestamps393.v

 /*******************************************************************************
  * Module: imu_timestamps393
  * Date:2015-07-06  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Acquire timestmps for events
  *
  * Copyright (c) 2015 Elphel, Inc.

logger/logger_arbiter393.v

 /*******************************************************************************
  * Module: logger_arbiter393
  * Date:2015-07-06  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: arbiter for the event_logger
  *
  * Copyright (c) 2015 Elphel, Inc.

logger/nmea_decoder393.v

 /*******************************************************************************
  * Module: nmea_decoder393
  * Date:2015-07-06  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Decode some of the NMEA sentences (to compress them)
  *
  * Copyright (c) 2015 Elphel, Inc.

logger/rs232_rcv393.v

 /*******************************************************************************
  * Module: rs232_rcv393
  * Date:2015-07-06  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: rs232 receiver
  *
  * Copyright (c) 2015 Elphel, Inc.

memctrl/cmd_encod_4mux.v

 /*******************************************************************************
  * Module: cmd_encod_4mux
  * Date:2015-02-21  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: 4-to-1 mux to cmbine memory sequences sources
  *
  * Copyright (c) 2015 Elphel, Inc.

memctrl/cmd_encod_linear_mux.v

 /*******************************************************************************
  * Module: cmd_encod_linear_mux
  * Date:2015-01-31  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Multiplex parameters from multiple channels sharing the same
  * linear command encoders (cmd_encod_linear_rd and cmd_encod_linear_wr)
  * Latency 1 clcok cycle

memctrl/cmd_encod_linear_rd.v

 /*******************************************************************************
  * Module: cmd_encod_linear_rd
  * Date:2015-01-23  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Command sequencer generator for reading a sequential up to 1KB page
  * single page access, bank and row will not be changed
  *

memctrl/cmd_encod_linear_rw.v

 /*******************************************************************************
  * Module: cmd_encod_linear_rw
  * Date:2015-02-21  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Combining 2 modules:cmd_encod_linear_rd and cmd_encod_linear_wr
  *
  * Copyright (c) 2015 Elphel, Inc.

memctrl/cmd_encod_linear_wr.v

 /*******************************************************************************
  * Module: cmd_encod_linear_wr
  * Date:2015-01-23  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Command sequencer generator for writing a sequential  up to 1KB page
  * single page access, bank and row will not be changed
  *

memctrl/cmd_encod_tiled_32_rd.v

 /*******************************************************************************
  * Module: cmd_encod_tiled_32_rd
  * Date:2015-02-218  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Command sequencer generator for reading a tiled area
  * up to 1 kB. Memory is mapped so 8 consecuitive rows have same RA, CA
  * and alternating BA (0 to 7). Data will be read in columns 32 bytes wide,

memctrl/cmd_encod_tiled_32_rw.v

 /*******************************************************************************
  * Module: cmd_encod_tiled_32_rw
  * Date:2015-02-21  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Combines  cmd_encod_tiled_32_rd and  cmd_encod_tiled_32_wr modules
  *
  * Copyright (c) 2015 Elphel, Inc.

memctrl/cmd_encod_tiled_32_wr.v

 /*******************************************************************************
  * Module: cmd_encod_tiled_32_wr
  * Date:2015-02-19  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Command sequencer generator for writing a tiled area
  * up to 1 kB. Memory is mapped so 8 consecuitive rows have same RA, CA
  * and alternating BA (0 to 7). Data will be read in columns 16 bytes wide,

memctrl/cmd_encod_tiled_mux.v

 /*******************************************************************************
  * Module: cmd_encod_tiled_mux
  * Date:2015-01-31  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Multiplex parameters from multiple channels sharing the same
  * tiled command encoders (cmd_encod_tiled_rd and cmd_encod_tiled_wr)
  * Latency 1 clcok cycle

memctrl/cmd_encod_tiled_rd.v

 /*******************************************************************************
  * Module: cmd_encod_tiled_rd
  * Date:2015-01-23  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Command sequencer generator for reading a tiled area
  * up to 1 kB. Memory is mapped so 8 consecuitive rows have same RA, CA
  * and alternating BA (0 to 7). Data will be read in columns 16 bytes wide,

memctrl/cmd_encod_tiled_rw.v

 /*******************************************************************************
  * Module: cmd_encod_tiled_rw
  * Date:2015-02-21  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Combines  cmd_encod_tiled_rd and  cmd_encod_tiled_wr modules
  *
  * Copyright (c) 2015 Elphel, Inc.

memctrl/cmd_encod_tiled_wr.v

 /*******************************************************************************
  * Module: cmd_encod_tiled_wr
  * Date:2015-02-19  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Command sequencer generator for writing a tiled area
  * up to 1 kB. Memory is mapped so 8 consecuitive rows have same RA, CA
  * and alternating BA (0 to 7). Data will be read in columns 16 bytes wide,

memctrl/mcntrl393.v

 /*******************************************************************************
  * Module: mcntrl393
  * Date:2015-01-31  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Top level memory controller for 393 camera, includes channel buffers
  *
  * Copyright (c) 2015 Elphel, Inc.

memctrl/mcntrl393_test01.v

 /*******************************************************************************
  * Module: mcntrl393_test01
  * Date:2015-02-06  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Temporary  module to interface mcntrl393 control signals
  *
  * Copyright (c) 2015 Elphel, Inc.

memctrl/mcntrl_1kx32r.v

 /*******************************************************************************
  * Module: mcntrl_1kx32r
  * Date:2015-02-03  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Paged buffer for ddr3 controller read channel
  * with address autoincrement. 32 bit external data.
  *

memctrl/mcntrl_1kx32w.v

 /*******************************************************************************
  * Module: mcntrl_1kx32w
  * Date:2015-02-03  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Paged buffer for ddr3 controller write channel
  * with address autoincrement. 32 bit external data. Extends rd to regen
  *

memctrl/mcntrl_buf_rd.v

 /*******************************************************************************
  * Module: mcntrl_buf_rd
  * Date:2015-02-03  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Paged buffer for ddr3 controller read channel
  * with address autoincrement. Variable width external data
  *

memctrl/mcntrl_buf_wr.v

 /*******************************************************************************
  * Module: mcntrl_buf_wr
  * Date:2015-02-03  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Paged buffer for ddr3 controller write channel
  * with address autoincrement. 32 bit external data. Extends rd to regen
  *

memctrl/mcntrl_linear_rw.v

 /*******************************************************************************
  * Module: mcntrl_linear_rw
  * Date:2015-01-29  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Organize paged R/W from DDR3 memory in scan-line order
  * with window support
  *

memctrl/mcntrl_ps_pio.v

 /*******************************************************************************
  * Module: mcntrl_ps_pio
  * Date:2015-01-27  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Read/write channels to DDR3 memory with software-programmable
  * command sequence
  *

memctrl/mcntrl_tiled_rw.v

 /*******************************************************************************
  * Module: mcntrl_tiled_rw
  * Date:2015-02-03  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description:  Organize paged R/W from DDR3 memory in tiled order
  * with window support
  * Tiles spreading over two different frames is not yet supported (needed for

memctrl/memctrl16.v

 /*******************************************************************************
  * Module: memctrl16
  * Date:2015-01-10  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: 16-channel memory controller
  *
  * Copyright (c) 2015 Elphel, Inc.

memctrl/scheduler16.v

 /*******************************************************************************
  * Module: scheduler16
  * Date:2015-01-09  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: 16-channel programmable DDR memory access scheduler
  *
  * Copyright (c) 2015 Elphel, Inc.

sensor/pxd_clock.v

 /*******************************************************************************
  * Module: pxd_clock
  * Date:2015-05-16  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: pixel clock line input
  *
  * Copyright (c) 2015 Elphel, Inc.

sensor/pxd_single.v

 /*******************************************************************************
  * Module: pxd_single
  * Date:2015-05-15  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: pixel data line input
  *
  * Copyright (c) 2015 Elphel, Inc.

sensor/sens_gamma.v

 /*******************************************************************************
  * Module: sens_gamma
  * Date:2015-05-24  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: table based piecewise-linear conversion of 16 -> 8 bit data
  *
  * Copyright (c) 2015 Elphel, Inc.

sensor/sens_histogram.v

 /*******************************************************************************
  * Module: sens_histogram
  * Date:2015-05-29  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Calculates per-color histogram over the specified rectangular region
  *
  * Copyright (c) 2015 Elphel, Inc.

sensor/sens_histogram_mux.v

 /*******************************************************************************
  * Module: sens_histogram_mux
  * Date:2015-06-01  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Readout multiplexer for 4 histogram modules
  *
  * Copyright (c) 2015 Elphel, Inc.

sensor/sens_parallel12.v

 /*******************************************************************************
  * Module: sens_parallel12
  * Date:2015-05-10  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Sensor interface with 12-bit for parallel bus
  *
  * Copyright (c) 2015 Elphel, Inc.

sensor/sensor_channel.v

 /*******************************************************************************
  * Module: sensor_channel
  * Date:2015-05-10  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Top module for a sensor channel
  *
  * Copyright (c) 2015 Elphel, Inc.

sensor/sensor_fifo.v

 /*******************************************************************************
  * Module: sensor_fifo
  * Date:2015-05-19  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Cross clock boundary for sensor data, synchronize to HACT
  *
  * Copyright (c) 2015 Elphel, Inc.

sensor/sensor_i2c.v

 /*******************************************************************************
  * Module: sensor_i2c
  * Date:2015-05-10  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: i2c write-only sequencer to control image sensor
  *
  * Copyright (c) 2015 Elphel, Inc.

sensor/sensor_i2c_io.v

 /*******************************************************************************
  * Module: sensor_i2c_io
  * Date:2015-05-15  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: sensor_i2c with I/O pad elements
  *
  * Copyright (c) 2015 Elphel, Inc.

simulation_modules/simul_axi_fifo_out.v

 /**************************************
 * Module: simul_axi_fifo
 * Date:2014-03-23  
-* Author: andrey     
+* Author: Andrey Filippov     
 *
 * Description: 
 ***************************************/

simulation_modules/simul_axi_hp_rd.v

 /*******************************************************************************
  * Module: simul_axi_hp_rd
  * Date:2015-04-25  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Simplified model of AXI_HP read channel (64-bit only)
  *
  * Copyright (c) 2015 Elphel, Inc.

simulation_modules/simul_axi_hp_wr.v

 /*******************************************************************************
  * Module: simul_axi_hp_wr
  * Date:2015-04-25  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Simplified model of AXI_HP write channel (64-bit only)
  *
  * Copyright (c) 2015 Elphel, Inc.

simulation_modules/simul_axi_master_rdaddr.v

 /*******************************************************************************
  * Module: simul_axi_master_rdaddr
  * Date:2014-03-23  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Simulation model for AXI read address channel
  *
  * Copyright (c) 2014 Elphel, Inc.

status_read.v

 /*******************************************************************************
  * Module: status_read
  * Date:2015-01-14  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Receives status read data (low bandwidth) from multiple
  * subsystems byte-serial, stores in axi-addressable memory
  * 8-bita ddress is received from the source module,

timing/camsync393.v

 /*******************************************************************************
  * Module: camsync393
  * Date:2015-07-03  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Synchronization between cameras using GPIO lines:
  *  - triggering from selected line(s) with filter;
  *  - programmable delay to actual trigger (in pixel clock periods)

timing/rtc393.v

 /*******************************************************************************
  * Module: rtc393
  * Date:2015-07-05  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Adjustable real time clock, generate 1 microsecond resolution,
  * timestamps. Provides seconds (32 bit) and microseconds (20 bits),
  * allows 24-bit accummulator-based fine adjustment

timing/timestamp_fifo.v

 /*******************************************************************************
  * Module: timestamp_fifo
  * Date:2015-07-02  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Receives 64-bit timestamp data over 8-bit bus,
  * copies it to the outputr register set at 'advance' leading edge
  * and then reads through the different clock domain 8-bit bus.

timing/timestamp_snapshot.v

 /*******************************************************************************
  * Module: timestamp_snapshot
  * Date:2015-07-03  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Take timestamp snapshot and send the ts message over the 8-bit bus
  *
  * Copyright (c) 2015 Elphel, Inc.

timing/timestamp_to_parallel.v

 /*******************************************************************************
  * Module: timestamp_to_parallel
  * Date:2015-07-04  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: convert byte-parallel timestamp message to parallel sec, usec
  * compatible to the x353 code (for NC353 camera)
  *

timing/timestamp_to_serial.v

 /*******************************************************************************
  * Module: timestamp_to_serial
  * Date:2015-07-04  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: convert legacy parallel timestamp data to a byte-parallel message
  *
  * Copyright (c) 2015 Elphel, Inc.

timing/timing393.v

 /*******************************************************************************
  * Module: timing393
  * Date:2015-07-05  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: timestamp realrted functionality, extrenal synchronization
  *
  * Copyright (c) 2015 Elphel, Inc.

util_modules/clk_to_clk2x.v

 /*******************************************************************************
  * Module: clk_to_clk2x
  * Date:2015-05-29  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: move data between clk and clk2x (nominally posedge aligned)
  *
  * Copyright (c) 2015 Elphel, Inc.

util_modules/cmd_deser.v

 /*******************************************************************************
  * Module: cmd_deser
  * Date:2015-01-12  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Expand command address/data from a byte-wide
  *
  * Copyright (c) 2015 Elphel, Inc.

util_modules/cmd_frame_sequencer.v

 /*******************************************************************************
  * Module: cmd_frame_sequencer
  * Date:2015-06-30  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Store/dispatch commands on per-frame basis
  *
  * Copyright (c) 2015 Elphel, Inc.

util_modules/cmd_seq_mux.v

 /*******************************************************************************
  * Module: cmd_seq_mux
  * Date:2015-06-29  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Command multiplexer from 4 channels of frame-based command
  * sequencers.
  *

util_modules/fifo_2regs.v

 /*******************************************************************************
  * Module: fifo_2regs
  * Date:2015-02-17  
- * Author: andrey     
+ * Author: Andrey Filippov     
  * Description: Simple two-register FIFO, no over/under check,
  * behaves correctly only for correct inputs
  *