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Elphel
x393
Commits
41babf8a
Commit
41babf8a
authored
Jul 12, 2015
by
Andrey Filippov
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Changed 'author' to full name
parent
5d61e6fb
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126 changed files
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126 additions
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126 deletions
+126
-126
cmprs_afi_mux.v
axi/cmprs_afi_mux.v
+1
-1
cmprs_afi_mux_ptr.v
axi/cmprs_afi_mux_ptr.v
+1
-1
cmprs_afi_mux_ptr_wresp.v
axi/cmprs_afi_mux_ptr_wresp.v
+1
-1
cmprs_afi_mux_status.v
axi/cmprs_afi_mux_status.v
+1
-1
histogram_saxi.v
axi/histogram_saxi.v
+1
-1
membridge.v
axi/membridge.v
+1
-1
mul_saxi_wr_chn.v
axi/mul_saxi_wr_chn.v
+1
-1
mult_saxi_wr.v
axi/mult_saxi_wr.v
+1
-1
mult_saxi_wr_pointers.v
axi/mult_saxi_wr_pointers.v
+1
-1
axi_hp_clk.v
axi_hp_clk.v
+1
-1
cmd_mux.v
cmd_mux.v
+1
-1
cmd_readback.v
cmd_readback.v
+1
-1
cmprs_buf_average.v
compressor_jp/cmprs_buf_average.v
+1
-1
cmprs_cmd_decode.v
compressor_jp/cmprs_cmd_decode.v
+1
-1
cmprs_frame_sync.v
compressor_jp/cmprs_frame_sync.v
+1
-1
cmprs_macroblock_buf_iface.v
compressor_jp/cmprs_macroblock_buf_iface.v
+1
-1
cmprs_out_fifo.v
compressor_jp/cmprs_out_fifo.v
+1
-1
cmprs_pixel_buf_iface.v
compressor_jp/cmprs_pixel_buf_iface.v
+1
-1
cmprs_status.v
compressor_jp/cmprs_status.v
+1
-1
cmprs_tile_mode2_decode.v
compressor_jp/cmprs_tile_mode2_decode.v
+1
-1
cmprs_tile_mode_decode.v
compressor_jp/cmprs_tile_mode_decode.v
+1
-1
color_proc393.v
compressor_jp/color_proc393.v
+1
-1
csconvert.v
compressor_jp/csconvert.v
+1
-1
csconvert_jp4.v
compressor_jp/csconvert_jp4.v
+1
-1
csconvert_jp4diff.v
compressor_jp/csconvert_jp4diff.v
+1
-1
csconvert_mono.v
compressor_jp/csconvert_mono.v
+1
-1
dcc_sync393.v
compressor_jp/dcc_sync393.v
+1
-1
jp_channel.v
compressor_jp/jp_channel.v
+1
-1
x393_cur_params_target.vh
includes/x393_cur_params_target.vh
+1
-1
x393_localparams.vh
includes/x393_localparams.vh
+1
-1
x393_mcontr_encode_cmd.vh
includes/x393_mcontr_encode_cmd.vh
+1
-1
x393_parameters.vh
includes/x393_parameters.vh
+1
-1
x393_simulation_parameters.vh
includes/x393_simulation_parameters.vh
+1
-1
x393_tasks01.vh
includes/x393_tasks01.vh
+1
-1
x393_tasks_afi.vh
includes/x393_tasks_afi.vh
+1
-1
x393_tasks_mcntrl_buffers.vh
includes/x393_tasks_mcntrl_buffers.vh
+1
-1
x393_tasks_mcntrl_en_dis_priority.vh
includes/x393_tasks_mcntrl_en_dis_priority.vh
+1
-1
x393_tasks_mcntrl_timing.vh
includes/x393_tasks_mcntrl_timing.vh
+1
-1
x393_tasks_pio_sequences.vh
includes/x393_tasks_pio_sequences.vh
+1
-1
x393_tasks_ps_pio.vh
includes/x393_tasks_ps_pio.vh
+1
-1
x393_tasks_status.vh
includes/x393_tasks_status.vh
+1
-1
buf_xclk_mclk16_393.v
logger/buf_xclk_mclk16_393.v
+1
-1
event_logger.v
logger/event_logger.v
+1
-1
imu_exttime393.v
logger/imu_exttime393.v
+1
-1
imu_message393.v
logger/imu_message393.v
+1
-1
imu_spi393.v
logger/imu_spi393.v
+1
-1
imu_timestamps393.v
logger/imu_timestamps393.v
+1
-1
logger_arbiter393.v
logger/logger_arbiter393.v
+1
-1
nmea_decoder393.v
logger/nmea_decoder393.v
+1
-1
rs232_rcv393.v
logger/rs232_rcv393.v
+1
-1
cmd_encod_4mux.v
memctrl/cmd_encod_4mux.v
+1
-1
cmd_encod_linear_mux.v
memctrl/cmd_encod_linear_mux.v
+1
-1
cmd_encod_linear_rd.v
memctrl/cmd_encod_linear_rd.v
+1
-1
cmd_encod_linear_rw.v
memctrl/cmd_encod_linear_rw.v
+1
-1
cmd_encod_linear_wr.v
memctrl/cmd_encod_linear_wr.v
+1
-1
cmd_encod_tiled_32_rd.v
memctrl/cmd_encod_tiled_32_rd.v
+1
-1
cmd_encod_tiled_32_rw.v
memctrl/cmd_encod_tiled_32_rw.v
+1
-1
cmd_encod_tiled_32_wr.v
memctrl/cmd_encod_tiled_32_wr.v
+1
-1
cmd_encod_tiled_mux.v
memctrl/cmd_encod_tiled_mux.v
+1
-1
cmd_encod_tiled_rd.v
memctrl/cmd_encod_tiled_rd.v
+1
-1
cmd_encod_tiled_rw.v
memctrl/cmd_encod_tiled_rw.v
+1
-1
cmd_encod_tiled_wr.v
memctrl/cmd_encod_tiled_wr.v
+1
-1
mcntrl393.v
memctrl/mcntrl393.v
+1
-1
mcntrl393_test01.v
memctrl/mcntrl393_test01.v
+1
-1
mcntrl_1kx32r.v
memctrl/mcntrl_1kx32r.v
+1
-1
mcntrl_1kx32w.v
memctrl/mcntrl_1kx32w.v
+1
-1
mcntrl_buf_rd.v
memctrl/mcntrl_buf_rd.v
+1
-1
mcntrl_buf_wr.v
memctrl/mcntrl_buf_wr.v
+1
-1
mcntrl_linear_rw.v
memctrl/mcntrl_linear_rw.v
+1
-1
mcntrl_ps_pio.v
memctrl/mcntrl_ps_pio.v
+1
-1
mcntrl_tiled_rw.v
memctrl/mcntrl_tiled_rw.v
+1
-1
memctrl16.v
memctrl/memctrl16.v
+1
-1
scheduler16.v
memctrl/scheduler16.v
+1
-1
pxd_clock.v
sensor/pxd_clock.v
+1
-1
pxd_single.v
sensor/pxd_single.v
+1
-1
sens_gamma.v
sensor/sens_gamma.v
+1
-1
sens_histogram.v
sensor/sens_histogram.v
+1
-1
sens_histogram_mux.v
sensor/sens_histogram_mux.v
+1
-1
sens_parallel12.v
sensor/sens_parallel12.v
+1
-1
sensor_channel.v
sensor/sensor_channel.v
+1
-1
sensor_fifo.v
sensor/sensor_fifo.v
+1
-1
sensor_i2c.v
sensor/sensor_i2c.v
+1
-1
sensor_i2c_io.v
sensor/sensor_i2c_io.v
+1
-1
simul_axi_fifo_out.v
simulation_modules/simul_axi_fifo_out.v
+1
-1
simul_axi_hp_rd.v
simulation_modules/simul_axi_hp_rd.v
+1
-1
simul_axi_hp_wr.v
simulation_modules/simul_axi_hp_wr.v
+1
-1
simul_axi_master_rdaddr.v
simulation_modules/simul_axi_master_rdaddr.v
+1
-1
status_read.v
status_read.v
+1
-1
camsync393.v
timing/camsync393.v
+1
-1
rtc393.v
timing/rtc393.v
+1
-1
timestamp_fifo.v
timing/timestamp_fifo.v
+1
-1
timestamp_snapshot.v
timing/timestamp_snapshot.v
+1
-1
timestamp_to_parallel.v
timing/timestamp_to_parallel.v
+1
-1
timestamp_to_serial.v
timing/timestamp_to_serial.v
+1
-1
timing393.v
timing/timing393.v
+1
-1
clk_to_clk2x.v
util_modules/clk_to_clk2x.v
+1
-1
cmd_deser.v
util_modules/cmd_deser.v
+1
-1
cmd_frame_sequencer.v
util_modules/cmd_frame_sequencer.v
+1
-1
cmd_seq_mux.v
util_modules/cmd_seq_mux.v
+1
-1
fifo_2regs.v
util_modules/fifo_2regs.v
+1
-1
gpio393.v
util_modules/gpio393.v
+1
-1
index_max_16.v
util_modules/index_max_16.v
+1
-1
masked_max_reg.v
util_modules/masked_max_reg.v
+1
-1
mcont_common_chnbuf_reg.v
util_modules/mcont_common_chnbuf_reg.v
+1
-1
mcont_from_chnbuf_reg.v
util_modules/mcont_from_chnbuf_reg.v
+1
-1
mcont_to_chnbuf_reg.v
util_modules/mcont_to_chnbuf_reg.v
+1
-1
multipulse_cross_clock.v
util_modules/multipulse_cross_clock.v
+1
-1
pri1hot16.v
util_modules/pri1hot16.v
+1
-1
pulse_cross_clock.v
util_modules/pulse_cross_clock.v
+1
-1
round_robin.v
util_modules/round_robin.v
+1
-1
status_generate.v
util_modules/status_generate.v
+1
-1
status_router16.v
util_modules/status_router16.v
+1
-1
status_router2.v
util_modules/status_router2.v
+1
-1
status_router4.v
util_modules/status_router4.v
+1
-1
status_router8.v
util_modules/status_router8.v
+1
-1
table_ad_receive.v
util_modules/table_ad_receive.v
+1
-1
table_ad_transmit.v
util_modules/table_ad_transmit.v
+1
-1
ddr3_wrap.v
wrap/ddr3_wrap.v
+1
-1
iobuf.v
wrap/iobuf.v
+1
-1
mpullup.v
wrap/mpullup.v
+1
-1
oddr_ss.v
wrap/oddr_ss.v
+1
-1
ram18_var_w_var_r.v
wrap/ram18_var_w_var_r.v
+1
-1
ramt_var_w_var_r.v
wrap/ramt_var_w_var_r.v
+1
-1
ramtp_var_w_var_r.v
wrap/ramtp_var_w_var_r.v
+1
-1
x393.v
x393.v
+1
-1
x393_testbench01.tf
x393_testbench01.tf
+1
-1
No files found.
axi/cmprs_afi_mux.v
View file @
41babf8a
/*******************************************************************************
* Module: cmprs_afi_mux
* Date:2015-06-26
* Author:
andrey
* Author:
Andrey Filippov
* Description: Writes comressor data from up to 4 channels to system memory over AXI_HP
*
* Copyright (c) 2015 Elphel, Inc.
...
...
axi/cmprs_afi_mux_ptr.v
View file @
41babf8a
/*******************************************************************************
* Module: cmprs_afi_mux_ptr
* Date:2015-06-28
* Author:
andrey
* Author:
Andrey Filippov
* Description: Maintain 4-channel chunk pointers (before AXI)
* Advance 32-byte chunk pointers for each AXI burst and each frame (4*2=8 pointers)
*
...
...
axi/cmprs_afi_mux_ptr_wresp.v
View file @
41babf8a
/*******************************************************************************
* Module: cmprs_afi_mux_ptr_wresp
* Date:2015-06-28
* Author:
andrey
* Author:
Andrey Filippov
* Description: Maintain 4-channel chunk pointers for wrirte response
* Advance 32-byte chunk pointers for each AXI burst and each frame (4*2=8 pointers)
*
...
...
axi/cmprs_afi_mux_status.v
View file @
41babf8a
/*******************************************************************************
* Module: cmprs_afi_mux_status
* Date:2015-06-28
* Author:
andrey
* Author:
Andrey Filippov
* Description: prepare and send per-channel chunk pointer information as status
* Using 4 consecutive locations. Each channel can provide one of the 4 pointers:
* frame pointer in the write channel, current chunk pointer in the write channel
...
...
axi/histogram_saxi.v
View file @
41babf8a
/*******************************************************************************
* Module: histogram_saxi
* Date:2015-06-04
* Author:
andrey
* Author:
Andrey Filippov
* Description: Histograms transfer to the system memory over S_AXI
*
* Copyright (c) 2015 Elphel, Inc.
...
...
axi/membridge.v
View file @
41babf8a
/*******************************************************************************
* Module: membridge
* Date:2015-04-26
* Author:
andrey
* Author:
Andrey Filippov
* Description: bi-directional bridge between system and video memory over axi_hp
*
* Copyright (c) 2015 Elphel, Inc.
...
...
axi/mul_saxi_wr_chn.v
View file @
41babf8a
/*******************************************************************************
* Module: mul_saxi_wr_chn
* Date:2015-07-10
* Author:
andrey
* Author:
Andrey Filippov
* Description: One channel of the mult_saxi_wr (read/write common buffer)
*
* Copyright (c) 2015 Elphel, Inc .
...
...
axi/mult_saxi_wr.v
View file @
41babf8a
/*******************************************************************************
* Module: mult_saxi_wr
* Date:2015-07-08
* Author:
andrey
* Author:
Andrey Filippov
* Description: send data from up to 4 sources to the system memory over S_AXI.
* Each source should have a 32-bit wide buffer running at the same clock (mclk).
* Buffer should contain at least burst size (4,8,16,32,64 bytes)
...
...
axi/mult_saxi_wr_pointers.v
View file @
41babf8a
/*******************************************************************************
* Module: mult_saxi_wr_pointers
* Date:2015-07-10
* Author:
andrey
* Author:
Andrey Filippov
* Description: Process pointers for mult_saxi_wr
*
* Copyright (c) 2015 Elphel, Inc .
...
...
axi_hp_clk.v
View file @
41babf8a
/*******************************************************************************
* Module: axi_hp_clk
* Date:2015-04-27
* Author:
andrey
* Author:
Andrey Filippov
* Description: Generate global clock for axi_hp
*
* Copyright (c) 2015 Elphel, Inc.
...
...
cmd_mux.v
View file @
41babf8a
/*******************************************************************************
* Module: cmd_mux
* Date:2015-01-11
* Author:
andrey
* Author:
Andrey Filippov
* Description: Command multiplexer between AXI and frame-based command sequencer
*
* Copyright (c) 2015 Elphel, Inc.
...
...
cmd_readback.v
View file @
41babf8a
/*******************************************************************************
* Module: cmd_readback
* Date:2015-05-05
* Author:
andrey
* Author:
Andrey Filippov
* Description: Store control register data and readback
*
* Copyright (c) 2015 Elphel, Inc.
...
...
compressor_jp/cmprs_buf_average.v
View file @
41babf8a
/*******************************************************************************
* Module: cmprs_buf_average
* Date:2015-06-14
* Author:
andrey
* Author:
Andrey Filippov
* Description: Saves Y and C components to buffers, caculates averages
* during write, then subtracts them during read and provides to
* the after DCT to restore DC
...
...
compressor_jp/cmprs_cmd_decode.v
View file @
41babf8a
/*******************************************************************************
* Module: cmprs_cmd_decode
* Date:2015-06-23
* Author:
andrey
* Author:
Andrey Filippov
* Description: Decode compressor command/modes, reclock some signals
*
* Copyright (c) 2015 Elphel, Inc.
...
...
compressor_jp/cmprs_frame_sync.v
View file @
41babf8a
/*******************************************************************************
* Module: cmprs_frame_sync
* Date:2015-06-23
* Author:
andrey
* Author:
Andrey Filippov
* Description: Synchronizes memory channels (sensor and compressor)
*
* Copyright (c) 2015 Elphel, Inc.
...
...
compressor_jp/cmprs_macroblock_buf_iface.v
View file @
41babf8a
/*******************************************************************************
* Module: cmprs_macroblock_buf_iface
* Date:2015-06-11
* Author:
andrey
* Author:
Andrey Filippov
* Description: Communicates with compressor memory buffer, generates pixel
* stream matching selected color mode, accommodates for the buffer latency,
* acts as a pacemaker for the whole compressor (next stages are able to keep up).
...
...
compressor_jp/cmprs_out_fifo.v
View file @
41babf8a
/*******************************************************************************
* Module: cmprs_out_fifo
* Date:2015-06-25
* Author:
andrey
* Author:
Andrey Filippov
* Description: Compressor output FIFO
*
* Copyright (c) 2015 Elphel, Inc.
...
...
compressor_jp/cmprs_pixel_buf_iface.v
View file @
41babf8a
/*******************************************************************************
* Module: cmprs_pixel_buf_iface
* Date:2015-06-11
* Author:
andrey
* Author:
Andrey Filippov
* Description: Communicates with compressor memory buffer, generates pixel
* stream matching selected color mode, accommodates for the buffer latency,
* acts as a pacemaker for the whole compressor (next stages are able to keep up).
...
...
compressor_jp/cmprs_status.v
View file @
41babf8a
/*******************************************************************************
* Module: cmprs_status
* Date:2015-06-25
* Author:
andrey
* Author:
Andrey Filippov
* Description: Generate compressor status word
*
* Copyright (c) 2015 Elphel, Inc.
...
...
compressor_jp/cmprs_tile_mode2_decode.v
View file @
41babf8a
/*******************************************************************************
* Module: cmprs_tile_mode2_decode
* Date:2015-06-14
* Author:
andrey
* Author:
Andrey Filippov
* Description: Decode mode parameters, registered at pre-start of the macroblock
* data to color conversion module
*
...
...
compressor_jp/cmprs_tile_mode_decode.v
View file @
41babf8a
/*******************************************************************************
* Module: cmprs_tile_mode_decode
* Date:2015-06-14
* Author:
andrey
* Author:
Andrey Filippov
* Description: Decode tile/macroblocks parameters from compressor type
*
* Copyright (c) 2015 Elphel, Inc.
...
...
compressor_jp/color_proc393.v
View file @
41babf8a
/*******************************************************************************
* Module: color_proc393
* Date:2015-06-10
* Author:
andrey
* Author:
Andrey Filippov
* Description: Color processor for JPEG 4:2:0/JP4
* Updating from the earlier 2002-2010 version
*
...
...
compressor_jp/csconvert.v
View file @
41babf8a
/*******************************************************************************
* Module: csconvert
* Date:2015-06-14
* Author:
andrey
* Author:
Andrey Filippov
* Description: Color space convert: combine differnt color modes
*
* Copyright (c) 2015 Elphel, Inc.
...
...
compressor_jp/csconvert_jp4.v
View file @
41babf8a
/*******************************************************************************
* Module: csconvert_jp4
* Date:2015-06-10
* Author:
andrey
* Author:
Andrey Filippov
* Description: Color conversion for JP4 mode
*
* Copyright (c) 2015 Elphel, Inc.
...
...
compressor_jp/csconvert_jp4diff.v
View file @
41babf8a
/*******************************************************************************
* Module: csconvert_jp4diff
* Date:2015-06-10
* Author:
andrey
* Author:
Andrey Filippov
* Description: Color conversion for JP4 differential
*
* Copyright (c) 2015 Elphel, Inc.
...
...
compressor_jp/csconvert_mono.v
View file @
41babf8a
/*******************************************************************************
* Module: csconvert_mono
* Date:2015-06-10
* Author:
andrey
* Author:
Andrey Filippov
* Description: Convert JPEG monochrome
*
* Copyright (c) 2015 Elphel, Inc.
...
...
compressor_jp/dcc_sync393.v
View file @
41babf8a
/*******************************************************************************
* Module: dcc_sync393
* Date:2015-06-17
* Author:
andrey
* Author:
Andrey Filippov
* Description: Synchronises output of DC components
* Syncronizes dcc data with dma1 output, adds 16..31 16-bit zero words for Axis DMA
* Was not used in late NC353 camera (DMA channel used fro IMU logger)
...
...
compressor_jp/jp_channel.v
View file @
41babf8a
/*******************************************************************************
* Module: jp_channel
* Date:2015-06-10
* Author:
andrey
* Author:
Andrey Filippov
* Description: Top module of JPEG/JP4 compressor channel
*
* Copyright (c) 2015 Elphel, Inc.
...
...
includes/x393_cur_params_target.vh
View file @
41babf8a
/*******************************************************************************
* File: x393_cur_params_target.vh
* Date:2015-02-07
* Author:
andrey
* Author:
Andrey Filippov
* Description: Memory controller parameters that need adjustment during training
* Target ,pde
* Copyright (c) 2015 Elphel, Inc.
...
...
includes/x393_localparams.vh
View file @
41babf8a
/*******************************************************************************
* File: x393_localparams.vh
* Date:2015-02-07
* Author:
andrey
* Author:
Andrey Filippov
* Description: Local parameters for simulation of the x393
*
* Copyright (c) 2015 Elphel, Inc.
...
...
includes/x393_mcontr_encode_cmd.vh
View file @
41babf8a
/*******************************************************************************
* File: x393_mcontr_encode_cmd.vh
* Date:2015-02-09
* Author:
andrey
* Author:
Andrey Filippov
* Description: Functions used to encode memory controller sequences
*
* Copyright (c) 2015 Elphel, Inc.
...
...
includes/x393_parameters.vh
View file @
41babf8a
/*******************************************************************************
* File: x393_parameters.vh
* Date:2015-02-07
* Author:
andrey
* Author:
Andrey Filippov
* Description: Parameters for the x393 (simulation and implementation)
*
* Copyright (c) 2015 Elphel, Inc.
...
...
includes/x393_simulation_parameters.vh
View file @
41babf8a
/*******************************************************************************
* File: x393_simulation_parameters.vh
* Date:2015-02-07
* Author:
andrey
* Author:
Andrey Filippov
* Description: Simulation-specific parameters for the x393
*
* Copyright (c) 2015 Elphel, Inc.
...
...
includes/x393_tasks01.vh
View file @
41babf8a
/*******************************************************************************
* File: x393_tasks01.vh
* Date:2015-02-07
* Author:
andrey
* Author:
Andrey Filippov
* Description: Simulation tasks for the x393 (low level)
*
* Copyright (c) 2015 Elphel, Inc.
...
...
includes/x393_tasks_afi.vh
View file @
41babf8a
/*******************************************************************************
* File: x393_tasks_afi.vh
* Date:2015-02-07
* Author:
andrey
* Author:
Andrey Filippov
* Description: Simulation tasks for the AXI_HP (AFI)
*
* Copyright (c) 2015 Elphel, Inc.
...
...
includes/x393_tasks_mcntrl_buffers.vh
View file @
41babf8a
/*******************************************************************************
* File: x393_tasks_mcntrl_buffers.vh
* Date:2015-02-07
* Author:
andrey
* Author:
Andrey Filippov
* Description: Simulation tasks for software reading/writing (with test patterns)
* of the block buffers.
*
...
...
includes/x393_tasks_mcntrl_en_dis_priority.vh
View file @
41babf8a
/*******************************************************************************
* File: x393_tasks_mcntrl_en_dis_priority.vh
* Date:2015-02-07
* Author:
andrey
* Author:
Andrey Filippov
* Description: Simulation tasks for software reading/writing (with test patterns)
* of the block buffers.
*
...
...
includes/x393_tasks_mcntrl_timing.vh
View file @
41babf8a
/*******************************************************************************
* File: x393_tasks_mcntrl_timing.vh
* Date:2015-02-07
* Author:
andrey
* Author:
Andrey Filippov
* Description: Simulation tasks for programming I/O delays and other timing
* parameters in the memory controller
*
...
...
includes/x393_tasks_pio_sequences.vh
View file @
41babf8a
/*******************************************************************************
* File: x393_tasks_pio_sequences.vh
* Date:2015-02-07
* Author:
andrey
* Author:
Andrey Filippov
* Description: Simulation tasks for programming memory transaction
* sequences (controlles by PS)
*
...
...
includes/x393_tasks_ps_pio.vh
View file @
41babf8a
/*******************************************************************************
* File: x393_tasks_ps_pio.vh
* Date:2015-02-07
* Author:
andrey
* Author:
Andrey Filippov
* Description: Simulation tasks for mcntrl_ps_pio module (launching software
* - programmed memory transaction sequences)
*
...
...
includes/x393_tasks_status.vh
View file @
41babf8a
/*******************************************************************************
* File: x393_status.vh
* Date:2015-02-07
* Author:
andrey
* Author:
Andrey Filippov
* Description: Simulation tasks for the x393 related to status
*
* Copyright (c) 2015 Elphel, Inc.
...
...
logger/buf_xclk_mclk16_393.v
View file @
41babf8a
/*******************************************************************************
* Module: buf_xclk_mclk16_393
* Date:2015-07-06
* Author:
andrey
* Author:
Andrey Filippov
* Description: move data from xclk to mclk domain
*
* Copyright (c) 2015 Elphel, Inc.
...
...
logger/event_logger.v
View file @
41babf8a
/*******************************************************************************
* Module: event_logger
* Date:2015-07-06
* Author:
andrey
* Author:
Andrey Filippov
* Description: top module of the event logger (ported from imu_logger)
*
* Copyright (c) 2015 Elphel, Inc.
...
...
logger/imu_exttime393.v
View file @
41babf8a
/*******************************************************************************
* Module: imu_exttime393
* Date:2015-07-06
* Author:
andrey
* Author:
Andrey Filippov
* Description: get external timestamp (for image)
*
* Copyright (c) 2015 Elphel, Inc.
...
...
logger/imu_message393.v
View file @
41babf8a
/*******************************************************************************
* Module: imu_message393
* Date:2015-07-06
* Author:
andrey
* Author:
Andrey Filippov
* Description:
*
* Copyright (c) 2015 Elphel, Inc.
...
...
logger/imu_spi393.v
View file @
41babf8a
/*******************************************************************************
* Module: imu_spi393
* Date:2015-07-06
* Author:
andrey
* Author:
Andrey Filippov
* Description: SPI interface for the IMU
*
* Copyright (c) 2015 Elphel, Inc.
...
...
logger/imu_timestamps393.v
View file @
41babf8a
/*******************************************************************************
* Module: imu_timestamps393
* Date:2015-07-06
* Author:
andrey
* Author:
Andrey Filippov
* Description: Acquire timestmps for events
*
* Copyright (c) 2015 Elphel, Inc.
...
...
logger/logger_arbiter393.v
View file @
41babf8a
/*******************************************************************************
* Module: logger_arbiter393
* Date:2015-07-06
* Author:
andrey
* Author:
Andrey Filippov
* Description: arbiter for the event_logger
*
* Copyright (c) 2015 Elphel, Inc.
...
...
logger/nmea_decoder393.v
View file @
41babf8a
/*******************************************************************************
* Module: nmea_decoder393
* Date:2015-07-06
* Author:
andrey
* Author:
Andrey Filippov
* Description: Decode some of the NMEA sentences (to compress them)
*
* Copyright (c) 2015 Elphel, Inc.
...
...
logger/rs232_rcv393.v
View file @
41babf8a
/*******************************************************************************
* Module: rs232_rcv393
* Date:2015-07-06
* Author:
andrey
* Author:
Andrey Filippov
* Description: rs232 receiver
*
* Copyright (c) 2015 Elphel, Inc.
...
...
memctrl/cmd_encod_4mux.v
View file @
41babf8a
/*******************************************************************************
* Module: cmd_encod_4mux
* Date:2015-02-21
* Author:
andrey
* Author:
Andrey Filippov
* Description: 4-to-1 mux to cmbine memory sequences sources
*
* Copyright (c) 2015 Elphel, Inc.
...
...
memctrl/cmd_encod_linear_mux.v
View file @
41babf8a
/*******************************************************************************
* Module: cmd_encod_linear_mux
* Date:2015-01-31
* Author:
andrey
* Author:
Andrey Filippov
* Description: Multiplex parameters from multiple channels sharing the same
* linear command encoders (cmd_encod_linear_rd and cmd_encod_linear_wr)
* Latency 1 clcok cycle
...
...
memctrl/cmd_encod_linear_rd.v
View file @
41babf8a
/*******************************************************************************
* Module: cmd_encod_linear_rd
* Date:2015-01-23
* Author:
andrey
* Author:
Andrey Filippov
* Description: Command sequencer generator for reading a sequential up to 1KB page
* single page access, bank and row will not be changed
*
...
...
memctrl/cmd_encod_linear_rw.v
View file @
41babf8a
/*******************************************************************************
* Module: cmd_encod_linear_rw
* Date:2015-02-21
* Author:
andrey
* Author:
Andrey Filippov
* Description: Combining 2 modules:cmd_encod_linear_rd and cmd_encod_linear_wr
*
* Copyright (c) 2015 Elphel, Inc.
...
...
memctrl/cmd_encod_linear_wr.v
View file @
41babf8a
/*******************************************************************************
* Module: cmd_encod_linear_wr
* Date:2015-01-23
* Author:
andrey
* Author:
Andrey Filippov
* Description: Command sequencer generator for writing a sequential up to 1KB page
* single page access, bank and row will not be changed
*
...
...
memctrl/cmd_encod_tiled_32_rd.v
View file @
41babf8a
/*******************************************************************************
* Module: cmd_encod_tiled_32_rd
* Date:2015-02-218
* Author:
andrey
* Author:
Andrey Filippov
* Description: Command sequencer generator for reading a tiled area
* up to 1 kB. Memory is mapped so 8 consecuitive rows have same RA, CA
* and alternating BA (0 to 7). Data will be read in columns 32 bytes wide,
...
...
memctrl/cmd_encod_tiled_32_rw.v
View file @
41babf8a
/*******************************************************************************
* Module: cmd_encod_tiled_32_rw
* Date:2015-02-21
* Author:
andrey
* Author:
Andrey Filippov
* Description: Combines cmd_encod_tiled_32_rd and cmd_encod_tiled_32_wr modules
*
* Copyright (c) 2015 Elphel, Inc.
...
...
memctrl/cmd_encod_tiled_32_wr.v
View file @
41babf8a
/*******************************************************************************
* Module: cmd_encod_tiled_32_wr
* Date:2015-02-19
* Author:
andrey
* Author:
Andrey Filippov
* Description: Command sequencer generator for writing a tiled area
* up to 1 kB. Memory is mapped so 8 consecuitive rows have same RA, CA
* and alternating BA (0 to 7). Data will be read in columns 16 bytes wide,
...
...
memctrl/cmd_encod_tiled_mux.v
View file @
41babf8a
/*******************************************************************************
* Module: cmd_encod_tiled_mux
* Date:2015-01-31
* Author:
andrey
* Author:
Andrey Filippov
* Description: Multiplex parameters from multiple channels sharing the same
* tiled command encoders (cmd_encod_tiled_rd and cmd_encod_tiled_wr)
* Latency 1 clcok cycle
...
...
memctrl/cmd_encod_tiled_rd.v
View file @
41babf8a
/*******************************************************************************
* Module: cmd_encod_tiled_rd
* Date:2015-01-23
* Author:
andrey
* Author:
Andrey Filippov
* Description: Command sequencer generator for reading a tiled area
* up to 1 kB. Memory is mapped so 8 consecuitive rows have same RA, CA
* and alternating BA (0 to 7). Data will be read in columns 16 bytes wide,
...
...
memctrl/cmd_encod_tiled_rw.v
View file @
41babf8a
/*******************************************************************************
* Module: cmd_encod_tiled_rw
* Date:2015-02-21
* Author:
andrey
* Author:
Andrey Filippov
* Description: Combines cmd_encod_tiled_rd and cmd_encod_tiled_wr modules
*
* Copyright (c) 2015 Elphel, Inc.
...
...
memctrl/cmd_encod_tiled_wr.v
View file @
41babf8a
/*******************************************************************************
* Module: cmd_encod_tiled_wr
* Date:2015-02-19
* Author:
andrey
* Author:
Andrey Filippov
* Description: Command sequencer generator for writing a tiled area
* up to 1 kB. Memory is mapped so 8 consecuitive rows have same RA, CA
* and alternating BA (0 to 7). Data will be read in columns 16 bytes wide,
...
...
memctrl/mcntrl393.v
View file @
41babf8a
/*******************************************************************************
* Module: mcntrl393
* Date:2015-01-31
* Author:
andrey
* Author:
Andrey Filippov
* Description: Top level memory controller for 393 camera, includes channel buffers
*
* Copyright (c) 2015 Elphel, Inc.
...
...
memctrl/mcntrl393_test01.v
View file @
41babf8a
/*******************************************************************************
* Module: mcntrl393_test01
* Date:2015-02-06
* Author:
andrey
* Author:
Andrey Filippov
* Description: Temporary module to interface mcntrl393 control signals
*
* Copyright (c) 2015 Elphel, Inc.
...
...
memctrl/mcntrl_1kx32r.v
View file @
41babf8a
/*******************************************************************************
* Module: mcntrl_1kx32r
* Date:2015-02-03
* Author:
andrey
* Author:
Andrey Filippov
* Description: Paged buffer for ddr3 controller read channel
* with address autoincrement. 32 bit external data.
*
...
...
memctrl/mcntrl_1kx32w.v
View file @
41babf8a
/*******************************************************************************
* Module: mcntrl_1kx32w
* Date:2015-02-03
* Author:
andrey
* Author:
Andrey Filippov
* Description: Paged buffer for ddr3 controller write channel
* with address autoincrement. 32 bit external data. Extends rd to regen
*
...
...
memctrl/mcntrl_buf_rd.v
View file @
41babf8a
/*******************************************************************************
* Module: mcntrl_buf_rd
* Date:2015-02-03
* Author:
andrey
* Author:
Andrey Filippov
* Description: Paged buffer for ddr3 controller read channel
* with address autoincrement. Variable width external data
*
...
...
memctrl/mcntrl_buf_wr.v
View file @
41babf8a
/*******************************************************************************
* Module: mcntrl_buf_wr
* Date:2015-02-03
* Author:
andrey
* Author:
Andrey Filippov
* Description: Paged buffer for ddr3 controller write channel
* with address autoincrement. 32 bit external data. Extends rd to regen
*
...
...
memctrl/mcntrl_linear_rw.v
View file @
41babf8a
/*******************************************************************************
* Module: mcntrl_linear_rw
* Date:2015-01-29
* Author:
andrey
* Author:
Andrey Filippov
* Description: Organize paged R/W from DDR3 memory in scan-line order
* with window support
*
...
...
memctrl/mcntrl_ps_pio.v
View file @
41babf8a
/*******************************************************************************
* Module: mcntrl_ps_pio
* Date:2015-01-27
* Author:
andrey
* Author:
Andrey Filippov
* Description: Read/write channels to DDR3 memory with software-programmable
* command sequence
*
...
...
memctrl/mcntrl_tiled_rw.v
View file @
41babf8a
/*******************************************************************************
* Module: mcntrl_tiled_rw
* Date:2015-02-03
* Author:
andrey
* Author:
Andrey Filippov
* Description: Organize paged R/W from DDR3 memory in tiled order
* with window support
* Tiles spreading over two different frames is not yet supported (needed for
...
...
memctrl/memctrl16.v
View file @
41babf8a
/*******************************************************************************
* Module: memctrl16
* Date:2015-01-10
* Author:
andrey
* Author:
Andrey Filippov
* Description: 16-channel memory controller
*
* Copyright (c) 2015 Elphel, Inc.
...
...
memctrl/scheduler16.v
View file @
41babf8a
/*******************************************************************************
* Module: scheduler16
* Date:2015-01-09
* Author:
andrey
* Author:
Andrey Filippov
* Description: 16-channel programmable DDR memory access scheduler
*
* Copyright (c) 2015 Elphel, Inc.
...
...
sensor/pxd_clock.v
View file @
41babf8a
/*******************************************************************************
* Module: pxd_clock
* Date:2015-05-16
* Author:
andrey
* Author:
Andrey Filippov
* Description: pixel clock line input
*
* Copyright (c) 2015 Elphel, Inc.
...
...
sensor/pxd_single.v
View file @
41babf8a
/*******************************************************************************
* Module: pxd_single
* Date:2015-05-15
* Author:
andrey
* Author:
Andrey Filippov
* Description: pixel data line input
*
* Copyright (c) 2015 Elphel, Inc.
...
...
sensor/sens_gamma.v
View file @
41babf8a
/*******************************************************************************
* Module: sens_gamma
* Date:2015-05-24
* Author:
andrey
* Author:
Andrey Filippov
* Description: table based piecewise-linear conversion of 16 -> 8 bit data
*
* Copyright (c) 2015 Elphel, Inc.
...
...
sensor/sens_histogram.v
View file @
41babf8a
/*******************************************************************************
* Module: sens_histogram
* Date:2015-05-29
* Author:
andrey
* Author:
Andrey Filippov
* Description: Calculates per-color histogram over the specified rectangular region
*
* Copyright (c) 2015 Elphel, Inc.
...
...
sensor/sens_histogram_mux.v
View file @
41babf8a
/*******************************************************************************
* Module: sens_histogram_mux
* Date:2015-06-01
* Author:
andrey
* Author:
Andrey Filippov
* Description: Readout multiplexer for 4 histogram modules
*
* Copyright (c) 2015 Elphel, Inc.
...
...
sensor/sens_parallel12.v
View file @
41babf8a
/*******************************************************************************
* Module: sens_parallel12
* Date:2015-05-10
* Author:
andrey
* Author:
Andrey Filippov
* Description: Sensor interface with 12-bit for parallel bus
*
* Copyright (c) 2015 Elphel, Inc.
...
...
sensor/sensor_channel.v
View file @
41babf8a
/*******************************************************************************
* Module: sensor_channel
* Date:2015-05-10
* Author:
andrey
* Author:
Andrey Filippov
* Description: Top module for a sensor channel
*
* Copyright (c) 2015 Elphel, Inc.
...
...
sensor/sensor_fifo.v
View file @
41babf8a
/*******************************************************************************
* Module: sensor_fifo
* Date:2015-05-19
* Author:
andrey
* Author:
Andrey Filippov
* Description: Cross clock boundary for sensor data, synchronize to HACT
*
* Copyright (c) 2015 Elphel, Inc.
...
...
sensor/sensor_i2c.v
View file @
41babf8a
/*******************************************************************************
* Module: sensor_i2c
* Date:2015-05-10
* Author:
andrey
* Author:
Andrey Filippov
* Description: i2c write-only sequencer to control image sensor
*
* Copyright (c) 2015 Elphel, Inc.
...
...
sensor/sensor_i2c_io.v
View file @
41babf8a
/*******************************************************************************
* Module: sensor_i2c_io
* Date:2015-05-15
* Author:
andrey
* Author:
Andrey Filippov
* Description: sensor_i2c with I/O pad elements
*
* Copyright (c) 2015 Elphel, Inc.
...
...
simulation_modules/simul_axi_fifo_out.v
View file @
41babf8a
/**************************************
* Module: simul_axi_fifo
* Date:2014-03-23
* Author:
andrey
* Author:
Andrey Filippov
*
* Description:
***************************************/
...
...
simulation_modules/simul_axi_hp_rd.v
View file @
41babf8a
/*******************************************************************************
* Module: simul_axi_hp_rd
* Date:2015-04-25
* Author:
andrey
* Author:
Andrey Filippov
* Description: Simplified model of AXI_HP read channel (64-bit only)
*
* Copyright (c) 2015 Elphel, Inc.
...
...
simulation_modules/simul_axi_hp_wr.v
View file @
41babf8a
/*******************************************************************************
* Module: simul_axi_hp_wr
* Date:2015-04-25
* Author:
andrey
* Author:
Andrey Filippov
* Description: Simplified model of AXI_HP write channel (64-bit only)
*
* Copyright (c) 2015 Elphel, Inc.
...
...
simulation_modules/simul_axi_master_rdaddr.v
View file @
41babf8a
/*******************************************************************************
* Module: simul_axi_master_rdaddr
* Date:2014-03-23
* Author:
andrey
* Author:
Andrey Filippov
* Description: Simulation model for AXI read address channel
*
* Copyright (c) 2014 Elphel, Inc.
...
...
status_read.v
View file @
41babf8a
/*******************************************************************************
* Module: status_read
* Date:2015-01-14
* Author:
andrey
* Author:
Andrey Filippov
* Description: Receives status read data (low bandwidth) from multiple
* subsystems byte-serial, stores in axi-addressable memory
* 8-bita ddress is received from the source module,
...
...
timing/camsync393.v
View file @
41babf8a
/*******************************************************************************
* Module: camsync393
* Date:2015-07-03
* Author:
andrey
* Author:
Andrey Filippov
* Description: Synchronization between cameras using GPIO lines:
* - triggering from selected line(s) with filter;
* - programmable delay to actual trigger (in pixel clock periods)
...
...
timing/rtc393.v
View file @
41babf8a
/*******************************************************************************
* Module: rtc393
* Date:2015-07-05
* Author:
andrey
* Author:
Andrey Filippov
* Description: Adjustable real time clock, generate 1 microsecond resolution,
* timestamps. Provides seconds (32 bit) and microseconds (20 bits),
* allows 24-bit accummulator-based fine adjustment
...
...
timing/timestamp_fifo.v
View file @
41babf8a
/*******************************************************************************
* Module: timestamp_fifo
* Date:2015-07-02
* Author:
andrey
* Author:
Andrey Filippov
* Description: Receives 64-bit timestamp data over 8-bit bus,
* copies it to the outputr register set at 'advance' leading edge
* and then reads through the different clock domain 8-bit bus.
...
...
timing/timestamp_snapshot.v
View file @
41babf8a
/*******************************************************************************
* Module: timestamp_snapshot
* Date:2015-07-03
* Author:
andrey
* Author:
Andrey Filippov
* Description: Take timestamp snapshot and send the ts message over the 8-bit bus
*
* Copyright (c) 2015 Elphel, Inc.
...
...
timing/timestamp_to_parallel.v
View file @
41babf8a
/*******************************************************************************
* Module: timestamp_to_parallel
* Date:2015-07-04
* Author:
andrey
* Author:
Andrey Filippov
* Description: convert byte-parallel timestamp message to parallel sec, usec
* compatible to the x353 code (for NC353 camera)
*
...
...
timing/timestamp_to_serial.v
View file @
41babf8a
/*******************************************************************************
* Module: timestamp_to_serial
* Date:2015-07-04
* Author:
andrey
* Author:
Andrey Filippov
* Description: convert legacy parallel timestamp data to a byte-parallel message
*
* Copyright (c) 2015 Elphel, Inc.
...
...
timing/timing393.v
View file @
41babf8a
/*******************************************************************************
* Module: timing393
* Date:2015-07-05
* Author:
andrey
* Author:
Andrey Filippov
* Description: timestamp realrted functionality, extrenal synchronization
*
* Copyright (c) 2015 Elphel, Inc.
...
...
util_modules/clk_to_clk2x.v
View file @
41babf8a
/*******************************************************************************
* Module: clk_to_clk2x
* Date:2015-05-29
* Author:
andrey
* Author:
Andrey Filippov
* Description: move data between clk and clk2x (nominally posedge aligned)
*
* Copyright (c) 2015 Elphel, Inc.
...
...
util_modules/cmd_deser.v
View file @
41babf8a
/*******************************************************************************
* Module: cmd_deser
* Date:2015-01-12
* Author:
andrey
* Author:
Andrey Filippov
* Description: Expand command address/data from a byte-wide
*
* Copyright (c) 2015 Elphel, Inc.
...
...
util_modules/cmd_frame_sequencer.v
View file @
41babf8a
/*******************************************************************************
* Module: cmd_frame_sequencer
* Date:2015-06-30
* Author:
andrey
* Author:
Andrey Filippov
* Description: Store/dispatch commands on per-frame basis
*
* Copyright (c) 2015 Elphel, Inc.
...
...
util_modules/cmd_seq_mux.v
View file @
41babf8a
/*******************************************************************************
* Module: cmd_seq_mux
* Date:2015-06-29
* Author:
andrey
* Author:
Andrey Filippov
* Description: Command multiplexer from 4 channels of frame-based command
* sequencers.
*
...
...
util_modules/fifo_2regs.v
View file @
41babf8a
/*******************************************************************************
* Module: fifo_2regs
* Date:2015-02-17
* Author:
andrey
* Author:
Andrey Filippov
* Description: Simple two-register FIFO, no over/under check,
* behaves correctly only for correct inputs
*
...
...
util_modules/gpio393.v
View file @
41babf8a
/*******************************************************************************
* Module: gpio393
* Date:2015-07-06
* Author:
andrey
* Author:
Andrey Filippov
* Description: Control of the 10 GPIO signals of the 10393 board
* Converted from twelve_ios.v of teh x353 project (2005)
*
...
...
util_modules/index_max_16.v
View file @
41babf8a
/*******************************************************************************
* Module: index_max_16
* Date:2015-01-09
* Author:
andrey
* Author:
Andrey Filippov
* Description: Find index of the maximal of 16 values (masked), 4 cycle latency
*
* Copyright (c) 2015 Elphel, Inc.
...
...
util_modules/masked_max_reg.v
View file @
41babf8a
/*******************************************************************************
* Module: masked_max_reg
* Date:2015-01-09
* Author:
andrey
* Author:
Andrey Filippov
* Description: Finds maximal of two masked values, registers result
*
* Copyright (c) 2015 Elphel, Inc.
...
...
util_modules/mcont_common_chnbuf_reg.v
View file @
41babf8a
/*******************************************************************************
* Module: mcont_common_chnbuf_reg
* Date:2015-01-19
* Author:
andrey
* Author:
Andrey Filippov
* Description: Registering data from channel buffer to memory controller
*
* Copyright (c) 2015 Elphel, Inc.
...
...
util_modules/mcont_from_chnbuf_reg.v
View file @
41babf8a
/*******************************************************************************
* Module: mcont_from_chnbuf_reg
* Date:2015-01-19
* Author:
andrey
* Author:
Andrey Filippov
* Description: Registering data from channel buffer to memory controller
*
* Copyright (c) 2015 Elphel, Inc.
...
...
util_modules/mcont_to_chnbuf_reg.v
View file @
41babf8a
/*******************************************************************************
* Module: mcont_to_chnbuf_reg
* Date:2015-01-19
* Author:
andrey
* Author:
Andrey Filippov
* Description: Registering data from memory controller to channel buffer
*
* Copyright (c) 2015 Elphel, Inc.
...
...
util_modules/multipulse_cross_clock.v
View file @
41babf8a
/*******************************************************************************
* Module: multipulse_cross_clock
* Date:2015-04-27
* Author:
andrey
* Author:
Andrey Filippov
* Description: Generate a train of pulses through clock domains boundary
* Maximal duty cycle (with EXTRA_DLY=0 and Fdst << Fsrc) = 50%
* same frequencies - ~1/3 (with EXTRA_DLY=0) and 1/5 (with EXTRA_DLY=1)
...
...
util_modules/pri1hot16.v
View file @
41babf8a
/*******************************************************************************
* Module: pri1hot16
* Date:2015-01-09
* Author:
andrey
* Author:
Andrey Filippov
* Description: Priority select one of 16 inputs
*
* Copyright (c) 2015 Elphel, Inc.
...
...
util_modules/pulse_cross_clock.v
View file @
41babf8a
/*******************************************************************************
* Module: pulse_cross_clock
* Date:2015-04-27
* Author:
andrey
* Author:
Andrey Filippov
* Description: Propagate a single pulse through clock domain boundary
* For same frequencies input pulses can have 1:3 duty cycle EXTRA_DLY=0
* and 1:5 for EXTRA_DLY=1
...
...
util_modules/round_robin.v
View file @
41babf8a
/*******************************************************************************
* Module: round_robin
* Date:2015-07-10
* Author:
andrey
* Author:
Andrey Filippov
* Description: Round-robin arbiter
*
* Copyright (c) 2015 Elphel, Inc .
...
...
util_modules/status_generate.v
View file @
41babf8a
/*******************************************************************************
* Module: status_generate
* Date:2015-01-14
* Author:
andrey
* Author:
Andrey Filippov
* Description: generate byte-serial status data
*
* Copyright (c) 2015 Elphel, Inc.
...
...
util_modules/status_router16.v
View file @
41babf8a
/*******************************************************************************
* Module: status_router16
* Date:2015-01-31
* Author:
andrey
* Author:
Andrey Filippov
* Description: Routes status data from 16 sources
*
* Copyright (c) 2015 Elphel, Inc.
...
...
util_modules/status_router2.v
View file @
41babf8a
/*******************************************************************************
* Module: status_router2
* Date:2015-01-13
* Author:
andrey
* Author:
Andrey Filippov
* Description: 2:1 status data router/mux
*
* Copyright (c) 2015 Elphel, Inc.
...
...
util_modules/status_router4.v
View file @
41babf8a
/*******************************************************************************
* Module: status_router4
* Date:2015-01-31
* Author:
andrey
* Author:
Andrey Filippov
* Description: Routes status data from 4 sources
*
* Copyright (c) 2015 Elphel, Inc.
...
...
util_modules/status_router8.v
View file @
41babf8a
/*******************************************************************************
* Module: status_router8
* Date:2015-01-31
* Author:
andrey
* Author:
Andrey Filippov
* Description: Routes status data from 8 sources
*
* Copyright (c) 2015 Elphel, Inc.
...
...
util_modules/table_ad_receive.v
View file @
41babf8a
/*******************************************************************************
* Module: table_ad_receive
* Date:2015-06-18
* Author:
andrey
* Author:
Andrey Filippov
* Description: Receive tabble address/data sent by table_ad_transmit
*
* Copyright (c) 2015 Elphel, Inc.
...
...
util_modules/table_ad_transmit.v
View file @
41babf8a
/*******************************************************************************
* Module: table_ad_transmit
* Date:2015-06-18
* Author:
andrey
* Author:
Andrey Filippov
* Description: transmit byte-wide table address/data from 32-bit cmd_desr
* In 32-bit mode we duty cycle is >= 6, so there will always be gaps in
* chn_stb[i] active
...
...
wrap/ddr3_wrap.v
View file @
41babf8a
/*******************************************************************************
* Module: ddr3_wrap
* Date:2015-04-20
* Author:
andrey
* Author:
Andrey Filippov
* Description: ddr3 model wrapper to include delays matching hardware
*
* Copyright (c) 2015 Elphel, Inc.
...
...
wrap/iobuf.v
View file @
41babf8a
/*******************************************************************************
* Module: iobuf
* Date:2015-05-15
* Author:
andrey
* Author:
Andrey Filippov
* Description: Wrapper for IOBUF primitive
*
* Copyright (c) 2015 Elphel, Inc.
...
...
wrap/mpullup.v
View file @
41babf8a
/*******************************************************************************
* Module: mpullup
* Date:2015-05-15
* Author:
andrey
* Author:
Andrey Filippov
* Description: wrapper for PULLUP primitive
*
* Copyright (c) 2015 Elphel, Inc.
...
...
wrap/oddr_ss.v
View file @
41babf8a
/*******************************************************************************
* Module: oddr_ss
* Date:2015-05-16
* Author:
andrey
* Author:
Andrey Filippov
* Description: Wrapper for ODDR+OBUFT
*
* Copyright (c) 2015 Elphel, Inc.
...
...
wrap/ram18_var_w_var_r.v
View file @
41babf8a
/*******************************************************************************
* Module: ram18_var_w_var_r
* Date:2015-06-16
* Author:
andrey
* Author:
Andrey Filippov
* Description: Half-BRAM module wrapper to use as a variable width R/W, no parity
*
* Copyright (c) 2015 Elphel, Inc.
...
...
wrap/ramt_var_w_var_r.v
View file @
41babf8a
/*******************************************************************************
* Module: ramt_var_w_var_r
* Date:2015-05-29
* Author:
andrey
* Author:
Andrey Filippov
* Description: Dual port memory wrapper, with variable width write and variable
* width read, using "TDP" mode of RAMB36E1. Same R/W widths in each port.
* Does not use parity bits to increase total data width, width down to 1 are valid.
...
...
wrap/ramtp_var_w_var_r.v
View file @
41babf8a
/*******************************************************************************
* Module: ramtp_var_w_var_r
* Date:2015-05-29
* Author:
andrey
* Author:
Andrey Filippov
* Description: Dual port memory wrapper, with variable width write and variable
* width read, using "TDP" mode of RAMB36E1. Same R/W widths in each port.
* Uses parity bits to increase total data width. Widths down to 9 are valid.
...
...
x393.v
View file @
41babf8a
/*******************************************************************************
* Module: x393
* Date:2015-01-13
* Author:
andrey
* Author:
Andrey Filippov
* Description: Elphel NC393 camera FPGA top module
*
* Copyright (c) 2015 Elphel, Inc.
...
...
x393_testbench01.tf
View file @
41babf8a
/*******************************************************************************
* Module: x393_testbench01
* Date:2015-02-06
* Author:
andrey
* Author:
Andrey Filippov
* Description: testbench for the initial x393.v simulation
*
* Copyright (c) 2015 Elphel, Inc.
...
...
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