Commit 41babf8a authored by Andrey Filippov's avatar Andrey Filippov

Changed 'author' to full name

parent 5d61e6fb
/*******************************************************************************
* Module: cmprs_afi_mux
* Date:2015-06-26
* Author: andrey
* Author: Andrey Filippov
* Description: Writes comressor data from up to 4 channels to system memory over AXI_HP
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: cmprs_afi_mux_ptr
* Date:2015-06-28
* Author: andrey
* Author: Andrey Filippov
* Description: Maintain 4-channel chunk pointers (before AXI)
* Advance 32-byte chunk pointers for each AXI burst and each frame (4*2=8 pointers)
*
......
/*******************************************************************************
* Module: cmprs_afi_mux_ptr_wresp
* Date:2015-06-28
* Author: andrey
* Author: Andrey Filippov
* Description: Maintain 4-channel chunk pointers for wrirte response
* Advance 32-byte chunk pointers for each AXI burst and each frame (4*2=8 pointers)
*
......
/*******************************************************************************
* Module: cmprs_afi_mux_status
* Date:2015-06-28
* Author: andrey
* Author: Andrey Filippov
* Description: prepare and send per-channel chunk pointer information as status
* Using 4 consecutive locations. Each channel can provide one of the 4 pointers:
* frame pointer in the write channel, current chunk pointer in the write channel
......
/*******************************************************************************
* Module: histogram_saxi
* Date:2015-06-04
* Author: andrey
* Author: Andrey Filippov
* Description: Histograms transfer to the system memory over S_AXI
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: membridge
* Date:2015-04-26
* Author: andrey
* Author: Andrey Filippov
* Description: bi-directional bridge between system and video memory over axi_hp
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: mul_saxi_wr_chn
* Date:2015-07-10
* Author: andrey
* Author: Andrey Filippov
* Description: One channel of the mult_saxi_wr (read/write common buffer)
*
* Copyright (c) 2015 Elphel, Inc .
......
/*******************************************************************************
* Module: mult_saxi_wr
* Date:2015-07-08
* Author: andrey
* Author: Andrey Filippov
* Description: send data from up to 4 sources to the system memory over S_AXI.
* Each source should have a 32-bit wide buffer running at the same clock (mclk).
* Buffer should contain at least burst size (4,8,16,32,64 bytes)
......
/*******************************************************************************
* Module: mult_saxi_wr_pointers
* Date:2015-07-10
* Author: andrey
* Author: Andrey Filippov
* Description: Process pointers for mult_saxi_wr
*
* Copyright (c) 2015 Elphel, Inc .
......
/*******************************************************************************
* Module: axi_hp_clk
* Date:2015-04-27
* Author: andrey
* Author: Andrey Filippov
* Description: Generate global clock for axi_hp
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: cmd_mux
* Date:2015-01-11
* Author: andrey
* Author: Andrey Filippov
* Description: Command multiplexer between AXI and frame-based command sequencer
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: cmd_readback
* Date:2015-05-05
* Author: andrey
* Author: Andrey Filippov
* Description: Store control register data and readback
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: cmprs_buf_average
* Date:2015-06-14
* Author: andrey
* Author: Andrey Filippov
* Description: Saves Y and C components to buffers, caculates averages
* during write, then subtracts them during read and provides to
* the after DCT to restore DC
......
/*******************************************************************************
* Module: cmprs_cmd_decode
* Date:2015-06-23
* Author: andrey
* Author: Andrey Filippov
* Description: Decode compressor command/modes, reclock some signals
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: cmprs_frame_sync
* Date:2015-06-23
* Author: andrey
* Author: Andrey Filippov
* Description: Synchronizes memory channels (sensor and compressor)
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: cmprs_macroblock_buf_iface
* Date:2015-06-11
* Author: andrey
* Author: Andrey Filippov
* Description: Communicates with compressor memory buffer, generates pixel
* stream matching selected color mode, accommodates for the buffer latency,
* acts as a pacemaker for the whole compressor (next stages are able to keep up).
......
/*******************************************************************************
* Module: cmprs_out_fifo
* Date:2015-06-25
* Author: andrey
* Author: Andrey Filippov
* Description: Compressor output FIFO
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: cmprs_pixel_buf_iface
* Date:2015-06-11
* Author: andrey
* Author: Andrey Filippov
* Description: Communicates with compressor memory buffer, generates pixel
* stream matching selected color mode, accommodates for the buffer latency,
* acts as a pacemaker for the whole compressor (next stages are able to keep up).
......
/*******************************************************************************
* Module: cmprs_status
* Date:2015-06-25
* Author: andrey
* Author: Andrey Filippov
* Description: Generate compressor status word
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: cmprs_tile_mode2_decode
* Date:2015-06-14
* Author: andrey
* Author: Andrey Filippov
* Description: Decode mode parameters, registered at pre-start of the macroblock
* data to color conversion module
*
......
/*******************************************************************************
* Module: cmprs_tile_mode_decode
* Date:2015-06-14
* Author: andrey
* Author: Andrey Filippov
* Description: Decode tile/macroblocks parameters from compressor type
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: color_proc393
* Date:2015-06-10
* Author: andrey
* Author: Andrey Filippov
* Description: Color processor for JPEG 4:2:0/JP4
* Updating from the earlier 2002-2010 version
*
......
/*******************************************************************************
* Module: csconvert
* Date:2015-06-14
* Author: andrey
* Author: Andrey Filippov
* Description: Color space convert: combine differnt color modes
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: csconvert_jp4
* Date:2015-06-10
* Author: andrey
* Author: Andrey Filippov
* Description: Color conversion for JP4 mode
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: csconvert_jp4diff
* Date:2015-06-10
* Author: andrey
* Author: Andrey Filippov
* Description: Color conversion for JP4 differential
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: csconvert_mono
* Date:2015-06-10
* Author: andrey
* Author: Andrey Filippov
* Description: Convert JPEG monochrome
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: dcc_sync393
* Date:2015-06-17
* Author: andrey
* Author: Andrey Filippov
* Description: Synchronises output of DC components
* Syncronizes dcc data with dma1 output, adds 16..31 16-bit zero words for Axis DMA
* Was not used in late NC353 camera (DMA channel used fro IMU logger)
......
/*******************************************************************************
* Module: jp_channel
* Date:2015-06-10
* Author: andrey
* Author: Andrey Filippov
* Description: Top module of JPEG/JP4 compressor channel
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* File: x393_cur_params_target.vh
* Date:2015-02-07
* Author: andrey
* Author: Andrey Filippov
* Description: Memory controller parameters that need adjustment during training
* Target ,pde
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* File: x393_localparams.vh
* Date:2015-02-07
* Author: andrey
* Author: Andrey Filippov
* Description: Local parameters for simulation of the x393
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* File: x393_mcontr_encode_cmd.vh
* Date:2015-02-09
* Author: andrey
* Author: Andrey Filippov
* Description: Functions used to encode memory controller sequences
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* File: x393_parameters.vh
* Date:2015-02-07
* Author: andrey
* Author: Andrey Filippov
* Description: Parameters for the x393 (simulation and implementation)
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* File: x393_simulation_parameters.vh
* Date:2015-02-07
* Author: andrey
* Author: Andrey Filippov
* Description: Simulation-specific parameters for the x393
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* File: x393_tasks01.vh
* Date:2015-02-07
* Author: andrey
* Author: Andrey Filippov
* Description: Simulation tasks for the x393 (low level)
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* File: x393_tasks_afi.vh
* Date:2015-02-07
* Author: andrey
* Author: Andrey Filippov
* Description: Simulation tasks for the AXI_HP (AFI)
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* File: x393_tasks_mcntrl_buffers.vh
* Date:2015-02-07
* Author: andrey
* Author: Andrey Filippov
* Description: Simulation tasks for software reading/writing (with test patterns)
* of the block buffers.
*
......
/*******************************************************************************
* File: x393_tasks_mcntrl_en_dis_priority.vh
* Date:2015-02-07
* Author: andrey
* Author: Andrey Filippov
* Description: Simulation tasks for software reading/writing (with test patterns)
* of the block buffers.
*
......
/*******************************************************************************
* File: x393_tasks_mcntrl_timing.vh
* Date:2015-02-07
* Author: andrey
* Author: Andrey Filippov
* Description: Simulation tasks for programming I/O delays and other timing
* parameters in the memory controller
*
......
/*******************************************************************************
* File: x393_tasks_pio_sequences.vh
* Date:2015-02-07
* Author: andrey
* Author: Andrey Filippov
* Description: Simulation tasks for programming memory transaction
* sequences (controlles by PS)
*
......
/*******************************************************************************
* File: x393_tasks_ps_pio.vh
* Date:2015-02-07
* Author: andrey
* Author: Andrey Filippov
* Description: Simulation tasks for mcntrl_ps_pio module (launching software
* - programmed memory transaction sequences)
*
......
/*******************************************************************************
* File: x393_status.vh
* Date:2015-02-07
* Author: andrey
* Author: Andrey Filippov
* Description: Simulation tasks for the x393 related to status
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: buf_xclk_mclk16_393
* Date:2015-07-06
* Author: andrey
* Author: Andrey Filippov
* Description: move data from xclk to mclk domain
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: event_logger
* Date:2015-07-06
* Author: andrey
* Author: Andrey Filippov
* Description: top module of the event logger (ported from imu_logger)
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: imu_exttime393
* Date:2015-07-06
* Author: andrey
* Author: Andrey Filippov
* Description: get external timestamp (for image)
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: imu_message393
* Date:2015-07-06
* Author: andrey
* Author: Andrey Filippov
* Description:
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: imu_spi393
* Date:2015-07-06
* Author: andrey
* Author: Andrey Filippov
* Description: SPI interface for the IMU
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: imu_timestamps393
* Date:2015-07-06
* Author: andrey
* Author: Andrey Filippov
* Description: Acquire timestmps for events
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: logger_arbiter393
* Date:2015-07-06
* Author: andrey
* Author: Andrey Filippov
* Description: arbiter for the event_logger
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: nmea_decoder393
* Date:2015-07-06
* Author: andrey
* Author: Andrey Filippov
* Description: Decode some of the NMEA sentences (to compress them)
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: rs232_rcv393
* Date:2015-07-06
* Author: andrey
* Author: Andrey Filippov
* Description: rs232 receiver
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: cmd_encod_4mux
* Date:2015-02-21
* Author: andrey
* Author: Andrey Filippov
* Description: 4-to-1 mux to cmbine memory sequences sources
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: cmd_encod_linear_mux
* Date:2015-01-31
* Author: andrey
* Author: Andrey Filippov
* Description: Multiplex parameters from multiple channels sharing the same
* linear command encoders (cmd_encod_linear_rd and cmd_encod_linear_wr)
* Latency 1 clcok cycle
......
/*******************************************************************************
* Module: cmd_encod_linear_rd
* Date:2015-01-23
* Author: andrey
* Author: Andrey Filippov
* Description: Command sequencer generator for reading a sequential up to 1KB page
* single page access, bank and row will not be changed
*
......
/*******************************************************************************
* Module: cmd_encod_linear_rw
* Date:2015-02-21
* Author: andrey
* Author: Andrey Filippov
* Description: Combining 2 modules:cmd_encod_linear_rd and cmd_encod_linear_wr
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: cmd_encod_linear_wr
* Date:2015-01-23
* Author: andrey
* Author: Andrey Filippov
* Description: Command sequencer generator for writing a sequential up to 1KB page
* single page access, bank and row will not be changed
*
......
/*******************************************************************************
* Module: cmd_encod_tiled_32_rd
* Date:2015-02-218
* Author: andrey
* Author: Andrey Filippov
* Description: Command sequencer generator for reading a tiled area
* up to 1 kB. Memory is mapped so 8 consecuitive rows have same RA, CA
* and alternating BA (0 to 7). Data will be read in columns 32 bytes wide,
......
/*******************************************************************************
* Module: cmd_encod_tiled_32_rw
* Date:2015-02-21
* Author: andrey
* Author: Andrey Filippov
* Description: Combines cmd_encod_tiled_32_rd and cmd_encod_tiled_32_wr modules
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: cmd_encod_tiled_32_wr
* Date:2015-02-19
* Author: andrey
* Author: Andrey Filippov
* Description: Command sequencer generator for writing a tiled area
* up to 1 kB. Memory is mapped so 8 consecuitive rows have same RA, CA
* and alternating BA (0 to 7). Data will be read in columns 16 bytes wide,
......
/*******************************************************************************
* Module: cmd_encod_tiled_mux
* Date:2015-01-31
* Author: andrey
* Author: Andrey Filippov
* Description: Multiplex parameters from multiple channels sharing the same
* tiled command encoders (cmd_encod_tiled_rd and cmd_encod_tiled_wr)
* Latency 1 clcok cycle
......
/*******************************************************************************
* Module: cmd_encod_tiled_rd
* Date:2015-01-23
* Author: andrey
* Author: Andrey Filippov
* Description: Command sequencer generator for reading a tiled area
* up to 1 kB. Memory is mapped so 8 consecuitive rows have same RA, CA
* and alternating BA (0 to 7). Data will be read in columns 16 bytes wide,
......
/*******************************************************************************
* Module: cmd_encod_tiled_rw
* Date:2015-02-21
* Author: andrey
* Author: Andrey Filippov
* Description: Combines cmd_encod_tiled_rd and cmd_encod_tiled_wr modules
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: cmd_encod_tiled_wr
* Date:2015-02-19
* Author: andrey
* Author: Andrey Filippov
* Description: Command sequencer generator for writing a tiled area
* up to 1 kB. Memory is mapped so 8 consecuitive rows have same RA, CA
* and alternating BA (0 to 7). Data will be read in columns 16 bytes wide,
......
/*******************************************************************************
* Module: mcntrl393
* Date:2015-01-31
* Author: andrey
* Author: Andrey Filippov
* Description: Top level memory controller for 393 camera, includes channel buffers
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: mcntrl393_test01
* Date:2015-02-06
* Author: andrey
* Author: Andrey Filippov
* Description: Temporary module to interface mcntrl393 control signals
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: mcntrl_1kx32r
* Date:2015-02-03
* Author: andrey
* Author: Andrey Filippov
* Description: Paged buffer for ddr3 controller read channel
* with address autoincrement. 32 bit external data.
*
......
/*******************************************************************************
* Module: mcntrl_1kx32w
* Date:2015-02-03
* Author: andrey
* Author: Andrey Filippov
* Description: Paged buffer for ddr3 controller write channel
* with address autoincrement. 32 bit external data. Extends rd to regen
*
......
/*******************************************************************************
* Module: mcntrl_buf_rd
* Date:2015-02-03
* Author: andrey
* Author: Andrey Filippov
* Description: Paged buffer for ddr3 controller read channel
* with address autoincrement. Variable width external data
*
......
/*******************************************************************************
* Module: mcntrl_buf_wr
* Date:2015-02-03
* Author: andrey
* Author: Andrey Filippov
* Description: Paged buffer for ddr3 controller write channel
* with address autoincrement. 32 bit external data. Extends rd to regen
*
......
/*******************************************************************************
* Module: mcntrl_linear_rw
* Date:2015-01-29
* Author: andrey
* Author: Andrey Filippov
* Description: Organize paged R/W from DDR3 memory in scan-line order
* with window support
*
......
/*******************************************************************************
* Module: mcntrl_ps_pio
* Date:2015-01-27
* Author: andrey
* Author: Andrey Filippov
* Description: Read/write channels to DDR3 memory with software-programmable
* command sequence
*
......
/*******************************************************************************
* Module: mcntrl_tiled_rw
* Date:2015-02-03
* Author: andrey
* Author: Andrey Filippov
* Description: Organize paged R/W from DDR3 memory in tiled order
* with window support
* Tiles spreading over two different frames is not yet supported (needed for
......
/*******************************************************************************
* Module: memctrl16
* Date:2015-01-10
* Author: andrey
* Author: Andrey Filippov
* Description: 16-channel memory controller
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: scheduler16
* Date:2015-01-09
* Author: andrey
* Author: Andrey Filippov
* Description: 16-channel programmable DDR memory access scheduler
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: pxd_clock
* Date:2015-05-16
* Author: andrey
* Author: Andrey Filippov
* Description: pixel clock line input
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: pxd_single
* Date:2015-05-15
* Author: andrey
* Author: Andrey Filippov
* Description: pixel data line input
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: sens_gamma
* Date:2015-05-24
* Author: andrey
* Author: Andrey Filippov
* Description: table based piecewise-linear conversion of 16 -> 8 bit data
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: sens_histogram
* Date:2015-05-29
* Author: andrey
* Author: Andrey Filippov
* Description: Calculates per-color histogram over the specified rectangular region
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: sens_histogram_mux
* Date:2015-06-01
* Author: andrey
* Author: Andrey Filippov
* Description: Readout multiplexer for 4 histogram modules
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: sens_parallel12
* Date:2015-05-10
* Author: andrey
* Author: Andrey Filippov
* Description: Sensor interface with 12-bit for parallel bus
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: sensor_channel
* Date:2015-05-10
* Author: andrey
* Author: Andrey Filippov
* Description: Top module for a sensor channel
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: sensor_fifo
* Date:2015-05-19
* Author: andrey
* Author: Andrey Filippov
* Description: Cross clock boundary for sensor data, synchronize to HACT
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: sensor_i2c
* Date:2015-05-10
* Author: andrey
* Author: Andrey Filippov
* Description: i2c write-only sequencer to control image sensor
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: sensor_i2c_io
* Date:2015-05-15
* Author: andrey
* Author: Andrey Filippov
* Description: sensor_i2c with I/O pad elements
*
* Copyright (c) 2015 Elphel, Inc.
......
/**************************************
* Module: simul_axi_fifo
* Date:2014-03-23
* Author: andrey
* Author: Andrey Filippov
*
* Description:
***************************************/
......
/*******************************************************************************
* Module: simul_axi_hp_rd
* Date:2015-04-25
* Author: andrey
* Author: Andrey Filippov
* Description: Simplified model of AXI_HP read channel (64-bit only)
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: simul_axi_hp_wr
* Date:2015-04-25
* Author: andrey
* Author: Andrey Filippov
* Description: Simplified model of AXI_HP write channel (64-bit only)
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: simul_axi_master_rdaddr
* Date:2014-03-23
* Author: andrey
* Author: Andrey Filippov
* Description: Simulation model for AXI read address channel
*
* Copyright (c) 2014 Elphel, Inc.
......
/*******************************************************************************
* Module: status_read
* Date:2015-01-14
* Author: andrey
* Author: Andrey Filippov
* Description: Receives status read data (low bandwidth) from multiple
* subsystems byte-serial, stores in axi-addressable memory
* 8-bita ddress is received from the source module,
......
/*******************************************************************************
* Module: camsync393
* Date:2015-07-03
* Author: andrey
* Author: Andrey Filippov
* Description: Synchronization between cameras using GPIO lines:
* - triggering from selected line(s) with filter;
* - programmable delay to actual trigger (in pixel clock periods)
......
/*******************************************************************************
* Module: rtc393
* Date:2015-07-05
* Author: andrey
* Author: Andrey Filippov
* Description: Adjustable real time clock, generate 1 microsecond resolution,
* timestamps. Provides seconds (32 bit) and microseconds (20 bits),
* allows 24-bit accummulator-based fine adjustment
......
/*******************************************************************************
* Module: timestamp_fifo
* Date:2015-07-02
* Author: andrey
* Author: Andrey Filippov
* Description: Receives 64-bit timestamp data over 8-bit bus,
* copies it to the outputr register set at 'advance' leading edge
* and then reads through the different clock domain 8-bit bus.
......
/*******************************************************************************
* Module: timestamp_snapshot
* Date:2015-07-03
* Author: andrey
* Author: Andrey Filippov
* Description: Take timestamp snapshot and send the ts message over the 8-bit bus
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: timestamp_to_parallel
* Date:2015-07-04
* Author: andrey
* Author: Andrey Filippov
* Description: convert byte-parallel timestamp message to parallel sec, usec
* compatible to the x353 code (for NC353 camera)
*
......
/*******************************************************************************
* Module: timestamp_to_serial
* Date:2015-07-04
* Author: andrey
* Author: Andrey Filippov
* Description: convert legacy parallel timestamp data to a byte-parallel message
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: timing393
* Date:2015-07-05
* Author: andrey
* Author: Andrey Filippov
* Description: timestamp realrted functionality, extrenal synchronization
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: clk_to_clk2x
* Date:2015-05-29
* Author: andrey
* Author: Andrey Filippov
* Description: move data between clk and clk2x (nominally posedge aligned)
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: cmd_deser
* Date:2015-01-12
* Author: andrey
* Author: Andrey Filippov
* Description: Expand command address/data from a byte-wide
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: cmd_frame_sequencer
* Date:2015-06-30
* Author: andrey
* Author: Andrey Filippov
* Description: Store/dispatch commands on per-frame basis
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: cmd_seq_mux
* Date:2015-06-29
* Author: andrey
* Author: Andrey Filippov
* Description: Command multiplexer from 4 channels of frame-based command
* sequencers.
*
......
/*******************************************************************************
* Module: fifo_2regs
* Date:2015-02-17
* Author: andrey
* Author: Andrey Filippov
* Description: Simple two-register FIFO, no over/under check,
* behaves correctly only for correct inputs
*
......
/*******************************************************************************
* Module: gpio393
* Date:2015-07-06
* Author: andrey
* Author: Andrey Filippov
* Description: Control of the 10 GPIO signals of the 10393 board
* Converted from twelve_ios.v of teh x353 project (2005)
*
......
/*******************************************************************************
* Module: index_max_16
* Date:2015-01-09
* Author: andrey
* Author: Andrey Filippov
* Description: Find index of the maximal of 16 values (masked), 4 cycle latency
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: masked_max_reg
* Date:2015-01-09
* Author: andrey
* Author: Andrey Filippov
* Description: Finds maximal of two masked values, registers result
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: mcont_common_chnbuf_reg
* Date:2015-01-19
* Author: andrey
* Author: Andrey Filippov
* Description: Registering data from channel buffer to memory controller
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: mcont_from_chnbuf_reg
* Date:2015-01-19
* Author: andrey
* Author: Andrey Filippov
* Description: Registering data from channel buffer to memory controller
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: mcont_to_chnbuf_reg
* Date:2015-01-19
* Author: andrey
* Author: Andrey Filippov
* Description: Registering data from memory controller to channel buffer
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: multipulse_cross_clock
* Date:2015-04-27
* Author: andrey
* Author: Andrey Filippov
* Description: Generate a train of pulses through clock domains boundary
* Maximal duty cycle (with EXTRA_DLY=0 and Fdst << Fsrc) = 50%
* same frequencies - ~1/3 (with EXTRA_DLY=0) and 1/5 (with EXTRA_DLY=1)
......
/*******************************************************************************
* Module: pri1hot16
* Date:2015-01-09
* Author: andrey
* Author: Andrey Filippov
* Description: Priority select one of 16 inputs
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: pulse_cross_clock
* Date:2015-04-27
* Author: andrey
* Author: Andrey Filippov
* Description: Propagate a single pulse through clock domain boundary
* For same frequencies input pulses can have 1:3 duty cycle EXTRA_DLY=0
* and 1:5 for EXTRA_DLY=1
......
/*******************************************************************************
* Module: round_robin
* Date:2015-07-10
* Author: andrey
* Author: Andrey Filippov
* Description: Round-robin arbiter
*
* Copyright (c) 2015 Elphel, Inc .
......
/*******************************************************************************
* Module: status_generate
* Date:2015-01-14
* Author: andrey
* Author: Andrey Filippov
* Description: generate byte-serial status data
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: status_router16
* Date:2015-01-31
* Author: andrey
* Author: Andrey Filippov
* Description: Routes status data from 16 sources
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: status_router2
* Date:2015-01-13
* Author: andrey
* Author: Andrey Filippov
* Description: 2:1 status data router/mux
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: status_router4
* Date:2015-01-31
* Author: andrey
* Author: Andrey Filippov
* Description: Routes status data from 4 sources
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: status_router8
* Date:2015-01-31
* Author: andrey
* Author: Andrey Filippov
* Description: Routes status data from 8 sources
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: table_ad_receive
* Date:2015-06-18
* Author: andrey
* Author: Andrey Filippov
* Description: Receive tabble address/data sent by table_ad_transmit
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: table_ad_transmit
* Date:2015-06-18
* Author: andrey
* Author: Andrey Filippov
* Description: transmit byte-wide table address/data from 32-bit cmd_desr
* In 32-bit mode we duty cycle is >= 6, so there will always be gaps in
* chn_stb[i] active
......
/*******************************************************************************
* Module: ddr3_wrap
* Date:2015-04-20
* Author: andrey
* Author: Andrey Filippov
* Description: ddr3 model wrapper to include delays matching hardware
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: iobuf
* Date:2015-05-15
* Author: andrey
* Author: Andrey Filippov
* Description: Wrapper for IOBUF primitive
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: mpullup
* Date:2015-05-15
* Author: andrey
* Author: Andrey Filippov
* Description: wrapper for PULLUP primitive
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: oddr_ss
* Date:2015-05-16
* Author: andrey
* Author: Andrey Filippov
* Description: Wrapper for ODDR+OBUFT
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: ram18_var_w_var_r
* Date:2015-06-16
* Author: andrey
* Author: Andrey Filippov
* Description: Half-BRAM module wrapper to use as a variable width R/W, no parity
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: ramt_var_w_var_r
* Date:2015-05-29
* Author: andrey
* Author: Andrey Filippov
* Description: Dual port memory wrapper, with variable width write and variable
* width read, using "TDP" mode of RAMB36E1. Same R/W widths in each port.
* Does not use parity bits to increase total data width, width down to 1 are valid.
......
/*******************************************************************************
* Module: ramtp_var_w_var_r
* Date:2015-05-29
* Author: andrey
* Author: Andrey Filippov
* Description: Dual port memory wrapper, with variable width write and variable
* width read, using "TDP" mode of RAMB36E1. Same R/W widths in each port.
* Uses parity bits to increase total data width. Widths down to 9 are valid.
......
/*******************************************************************************
* Module: x393
* Date:2015-01-13
* Author: andrey
* Author: Andrey Filippov
* Description: Elphel NC393 camera FPGA top module
*
* Copyright (c) 2015 Elphel, Inc.
......
/*******************************************************************************
* Module: x393_testbench01
* Date:2015-02-06
* Author: andrey
* Author: Andrey Filippov
* Description: testbench for the initial x393.v simulation
*
* Copyright (c) 2015 Elphel, Inc.
......
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