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Elphel
x393
Commits
407c39ca
Commit
407c39ca
authored
May 08, 2014
by
Andrey Filippov
Browse files
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Plain Diff
fixed warnings
parent
e9a79158
Changes
6
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6 changed files
with
38 additions
and
22 deletions
+38
-22
test_dqs.v
phy/test_dqs.v
+1
-1
test_dqs01.v
phy/test_dqs01.v
+18
-6
test_dqs02.v
phy/test_dqs02.v
+12
-11
test_dqs03.v
phy/test_dqs03.v
+3
-1
test_dqs04.v
phy/test_dqs04.v
+1
-1
test_dqs05.v
phy/test_dqs05.v
+3
-2
No files found.
phy/test_dqs.v
View file @
407c39ca
...
...
@@ -34,7 +34,7 @@ module test_dqs(
inout
ndqs
,
output
dqs_received
,
output
dly_ready
,
input
dqs_tri_a
,
//
input dqs_tri_a,
output
dqs_tri
)
;
...
...
phy/test_dqs01.v
View file @
407c39ca
...
...
@@ -36,12 +36,24 @@ IOBUFDS #(
.
IBUF_LOW_PWR
(
"TRUE"
)
,
.
IOSTANDARD
(
"DEFAULT"
)
,
.
SLEW
(
"SLOW"
)
)
iobufs_dqs_i
(
.
O
(
dqs_received
)
,
.
IO
(
dqs
[
1
:
0
])
,
.
IOB
(
ndqs
)
,
.
I
(
123
)
,
//2'b11), //dqs_data),
.
T
(
dqs_tri
))
;
)
iobufs_dqs_i0
(
.
O
(
dqs_received
[
0
])
,
.
IO
(
dqs
[
0
])
,
.
IOB
(
ndqs
[
0
])
,
.
I
(
dqs_data
[
0
])
,
.
T
(
dqs_tri
[
0
]))
;
IOBUFDS
#(
.
DQS_BIAS
(
"FALSE"
)
,
.
IBUF_LOW_PWR
(
"TRUE"
)
,
.
IOSTANDARD
(
"DEFAULT"
)
,
.
SLEW
(
"SLOW"
)
)
iobufs_dqs_i1
(
.
O
(
dqs_received
[
1
])
,
.
IO
(
dqs
[
1
])
,
.
IOB
(
ndqs
[
1
])
,
.
I
(
dqs_data
[
1
])
,
.
T
(
dqs_tri
[
1
]))
;
endmodule
phy/test_dqs02.v
View file @
407c39ca
...
...
@@ -24,18 +24,18 @@ module test_dqs02(
input
rst
,
// reset
input
refclk
,
// 200MHz/300MHz for delay calibration
input
clk_in
,
input
set
,
input
ld_dly_data
,
input
ld_dly_tri
,
input
[
7
:
0
]
dly_data
,
//
input set,
//
input ld_dly_data,
//
input ld_dly_tri,
//
input [7:0] dly_data,
input
[
3
:
0
]
data_in
,
input
[
3
:
0
]
tri_in
,
//
input [3:0] tri_in,
inout
dqs
,
inout
ndqs
,
//
inout ndqs,
output
dqs_received
,
output
dly_ready
,
input
dqs_tri_a
,
output
dqs_tri
output
dly_ready
//
input dqs_tri_a,
//
output dqs_tri
// output dqs_data
)
;
...
...
@@ -43,7 +43,7 @@ wire refclk_b=refclk; // use buffer
wire
clk
,
clk_div
;
//wire dqs_data,dqs_tri; // after odelay
//wire dqs_data; // after odelay
wire
pre_dqs_data
,
pre_dqs_tri
;
// before odelay
//
wire pre_dqs_data,pre_dqs_tri; // before odelay
wire
dqs_data
;
BUFR
#(
.
BUFR_DIVIDE
(
"2"
))
clk_div_i
(
.
I
(
clk_in
)
,.
O
(
clk_div
)
,.
CLR
(
rst
)
,
.
CE
(
1'b1
))
;
BUFR
#(
.
BUFR_DIVIDE
(
"BYPASS"
))
clk_i
(
.
I
(
clk_in
)
,.
O
(
clk
)
,
.
CLR
(
1'b0
)
,.
CE
(
1'b1
))
;
...
...
@@ -58,7 +58,8 @@ oserdes_mem oserdes_dqs_i(
.
dout_dly
()
,
//pre_dqs_data), // data out to be connected to odelay input
.
dout_iob
(
dqs_data
)
,
// data out to be connected directly to the output buffer
.
tout_dly
()
,
// tristate out to be connected to odelay input
.
tout_iob
(
pre_dqs_tri
)
// tristate out to be connected directly to the tristate control of the output buffer
// .tout_iob(pre_dqs_tri) // tristate out to be connected directly to the tristate control of the output buffer
.
tout_iob
()
// tristate out to be connected directly to the tristate control of the output buffer
)
;
idelay_ctrl
#
(
...
...
phy/test_dqs03.v
View file @
407c39ca
...
...
@@ -36,7 +36,9 @@ module test_dqs03(
input
ld
)
;
wire
clk
,
clk_div
,
clk_ref
;
//SuppressWarnings all
wire
clk
;
wire
clk_div
,
clk_ref
;
wire
dqs_data_dly
;
BUFR
#(
.
BUFR_DIVIDE
(
"2"
))
clk_div_i
(
.
I
(
clk_in
)
,.
O
(
clk_div
)
,.
CLR
(
rst
)
,
.
CE
(
1'b1
))
;
BUFR
#(
.
BUFR_DIVIDE
(
"BYPASS"
))
clk_i
(
.
I
(
clk_in
)
,.
O
(
clk
)
,
.
CLR
(
1'b0
)
,.
CE
(
1'b1
))
;
...
...
phy/test_dqs04.v
View file @
407c39ca
...
...
@@ -28,7 +28,7 @@ module test_dqs04(
input
clk_ref_in
,
input
rst
,
output
dqs_received
,
input
dqs_tri
,
//
input dqs_tri,
output
dly_ready
,
input
[
4
:
0
]
dly_data
,
...
...
phy/test_dqs05.v
View file @
407c39ca
...
...
@@ -44,7 +44,7 @@ assign dly_ready= dly_ready_0 && dqs_data;
wire
d_ser
;
wire
dqs_tri1
;
wire
d_tri
;
//
wire d_tri;
BUFR
#(
.
BUFR_DIVIDE
(
"2"
))
clk_div_i
(
.
I
(
clk_in
)
,.
O
(
clk_div
)
,.
CLR
(
rst
)
,
.
CE
(
1'b1
))
;
BUFR
#(
.
BUFR_DIVIDE
(
"BYPASS"
))
clk_i
(
.
I
(
clk_in
)
,.
O
(
clk
)
,
.
CLR
(
1'b0
)
,.
CE
(
1'b1
))
;
...
...
@@ -65,9 +65,10 @@ BUFG ref_clk_i (.I(clk_ref_in),.O(clk_ref));
.
TBYTE_SRC
(
"FALSE"
)
)
oserdes_i
(
.
OFB
(
d_ser
)
,
.
OQ
()
,
// dout_iob),
.
OQ
()
,
.
SHIFTOUT1
()
,
.
SHIFTOUT2
()
,
.
TFB
()
,
// .TFB (d_tri),
// .TQ (dqs_tri1),
.
TQ
()
,
...
...
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