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Commit 3ed89577 authored by Andrey Filippov's avatar Andrey Filippov
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Added progremmable interrupts from multi_saxi (used for IMU/GPS logger) and related export to C

parent 4a4984a7
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Showing with 215 additions and 178 deletions
.settings/com.elphel.vdt.VivadoBitstream.prefs
View file @ 3ed89577
VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_@_force=true
VivadoBitstream_@_rawfile=x393_parallel
VivadoBitstream_@_rawfile=x393_hispi
com.elphel.store.context.VivadoBitstream=VivadoBitstream_@_rawfile<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->
eclipse.preferences.version=1
VERSION
View file @ 3ed89577
......@@ -4,4 +4,4 @@
# a. 3
# b. 3.2 (preferred)
# c. 3.2.4
1.155
1.157
axi/mult_saxi_wr.v
View file @ 3ed89577
......@@ -43,7 +43,11 @@
module mult_saxi_wr #(
parameter MULT_SAXI_ADDR = 'h730, // ..'h737
parameter MULT_SAXI_CNTRL_ADDR = 'h738, // ..'h739
parameter MULT_SAXI_IRQLEN_ADDR = 'h738, // ..'h73b
parameter MULT_SAXI_CNTRL_ADDR = 'h73c, // ..'h73e
parameter MULT_SAXI_CNTRL_MODE = 'h0, // 'h73c offset for mode register
parameter MULT_SAXI_CNTRL_STATUS = 'h1, // 'h73d offset for status control register
parameter MULT_SAXI_CNTRL_IRQ = 'h2, // 'h73e offset for IRQ contgrol register (4 dibits): 0 - nop, 1 reset, 2 - disable, 3 - enable
parameter MULT_SAXI_STATUS_REG = 'h34, //..'h37 uses 4 consecutive locations
parameter MULT_SAXI_HALF_BRAM = 1, // 0 - use full 36Kb BRAM for the buffer, 1 - use just half
parameter MULT_SAXI_BSLOG0 = 4, // number of bits to represent burst size (4 - b.s. = 16, 0 - b.s = 1)
......@@ -51,7 +55,8 @@ module mult_saxi_wr #(
parameter MULT_SAXI_BSLOG2 = 4,
parameter MULT_SAXI_BSLOG3 = 4,
parameter MULT_SAXI_MASK = 'h7f8, // 4 address/length pairs. In bytes, but lower bits are set to 0?
parameter MULT_SAXI_CNTRL_MASK = 'h7fe, // mode and status - 2 locations
parameter MULT_SAXI_IRQLEN_MASK = 'h7fc, // number of address bits to change for interrupt - 4 locations
parameter MULT_SAXI_CNTRL_MASK = 'h7fc, // mode, status, irq - 3 locations
parameter MULT_SAXI_AWCACHE = 4'h3, //..7 cache mode (4 bits, default 4'h3)
parameter MULT_SAXI_ADV_WR = 4, // number of clock cycles before end of write to genearte adv_wr_done
parameter MULT_SAXI_ADV_RD = 3 // number of clock cycles before end of write to genearte adv_wr_done
......@@ -92,6 +97,8 @@ module mult_saxi_wr #(
output read_burst3, // request to read a burst of data from channel 0
input [31:0] data_in_chn3, // data read from channel 0 (with some latency)
input pre_valid_chn3,// data valid (same latency)
output [3:0] irq, // per channel IRQ (generated after each 2^n DWORDS are transferred)
// S_AXI inerface w/o read channel
// write address
......@@ -169,7 +176,13 @@ module mult_saxi_wr #(
wire we_ctrl;
wire cmd_we_sa_len;
wire irq_log_we; // write number of address bits to change to generate interrupt
wire [3:0] irqs_src; // IRQ pulses to be used for IRQ generation
reg [3:0] irq_r = 0; // IRQ request (before mask)
reg [3:0] irq_m = 0; // IRQ enable
wire irq_we;
assign irq = irq_r & irq_m;
assign saxi_bready=1'b1;
assign {en_chn3, en_chn2, en_chn1, en_chn0} = en_chn_mclk;
......@@ -180,11 +193,35 @@ module mult_saxi_wr #(
assign en_chn_mclk = mode_reg[3:0];
assign run_chn_mclk = mode_reg[7:4];
assign irq_we = we_ctrl && (cmd_a[1:0] == MULT_SAXI_CNTRL_IRQ);
always @ (posedge mclk) begin
if (mrst) mode_reg <= 0;
else if (we_ctrl && !cmd_a[0]) mode_reg <= cmd_data[7:0];
if (mrst) mode_reg <= 0;
else if (we_ctrl && (cmd_a[1:0] == MULT_SAXI_CNTRL_MODE)) mode_reg <= cmd_data[7:0];
/*
if (mrst) irq_r <= 0;
else irq_r <= irqs_src | (irq_r & (irq_we?{cmd_data[7:6] != 1,
cmd_data[5:4] != 1,
cmd_data[3:2] != 1,
cmd_data[1:0] != 1}:4'hf));
*/
end
generate
genvar i;
for (i=0; i<4; i=i+1) begin: irq_ctrl_block
always @ (posedge mclk) begin
if (mrst) irq_m[i] <= 0;
else if (irq_we && cmd_data[2*i+1]) irq_m[i] <= cmd_data[2*i];
if (mrst) irq_r[i] <= 0;
else if (irqs_src[i]) irq_r[i] <= 1;
else if (irq_we && (cmd_data[2*i +: 2] == 1)) irq_r[i] <= 0;
end
end
endgenerate
// Arbiter requests on copying from one of the input channels to the internal buffer
......@@ -394,6 +431,7 @@ module mult_saxi_wr #(
.sa_len_di (cmd_data[29:0]), // input[29:0]
.sa_len_wa (cmd_a[2:0]), // input[2:0]
.sa_len_we (cmd_we_sa_len), // input
.irq_log_we (irq_log_we), // input
.chn (re_cur_chn), // input[1:0]
.start (grant_rd_any), // input make sure 1 cycle
.busy (axi_ptr_busy), // output OR this busy with write data channel busy for en_out_arb
......@@ -401,7 +439,9 @@ module mult_saxi_wr #(
.axi_len (axi_len), // output[3:0] reg
.pntr_wd (pntr_wd), // output[29:0]
.pntr_wa (pntr_wa), // output[1:0]
.pntr_we (pntr_we) // output
.pntr_we (pntr_we), // output
.irqs (irqs_src) // output[3:0]
);
// interface axi_aw channel
......@@ -498,17 +538,17 @@ module mult_saxi_wr #(
.DATA_WIDTH (32),
.ADDR1 (MULT_SAXI_CNTRL_ADDR),
.ADDR_MASK1 (MULT_SAXI_CNTRL_MASK),
.ADDR2 (0),
.ADDR_MASK2 (0)
) cmd_deser_sens_i2c_i (
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
.data (cmd_data), // output[31:0]
.we ({cmd_we_sa_len,we_ctrl}) // output
.ADDR2 (MULT_SAXI_IRQLEN_ADDR),
.ADDR_MASK2 (MULT_SAXI_IRQLEN_MASK)
) cmd_deser_mult_saxi_wr_i (
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
.data (cmd_data), // output[31:0]
.we ({cmd_we_sa_len,we_ctrl,irq_log_we}) // output
);
// now - converting all to parallel (TODO: use RAM for multi-word status data)
......@@ -542,7 +582,7 @@ module mult_saxi_wr #(
.rst (1'b0), //rst), // input
.clk (mclk), // input
.srst (mrst), // input
.we (we_ctrl && cmd_a[0]), // input
.we (we_ctrl && (cmd_a[1:0] == MULT_SAXI_CNTRL_STATUS)), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data), // input[128:0]
.ad (status_ad), // output[7:0]
......
axi/mult_saxi_wr_pointers.v
View file @ 3ed89577
......@@ -50,6 +50,7 @@ module mult_saxi_wr_pointers#(
input [29:0] sa_len_di, // input data to write pointers address/data
input [ 2:0] sa_len_wa, // channel address to write sa/lengths
input sa_len_we, // write enable sa/length data
input irq_log_we, // write log2 of number of written dwords to generate interrupt
input [ 1:0] chn, // selected channel number, valid with start
input start, // start address generation/pointer increment
output busy, // suspend new accesses (check latencies)
......@@ -60,7 +61,8 @@ module mult_saxi_wr_pointers#(
// alternatively - read out directly from ptr_ram?
output [29:0] pntr_wd, // @aclk
output [1:0] pntr_wa,
output pntr_we
output pntr_we,
output [3:0] irqs // @mclk, single-clock pulses to generate channel interrupts
);
reg [3:0] chn_en_mclk_r;
reg [3:0] chn_en_aclk;
......@@ -79,6 +81,10 @@ module mult_saxi_wr_pointers#(
reg [1:0] chn_r; // registered channel being processed (or reset)
reg [1:0] seq; // 1-hot sequence of address generation
wire [29:0] sa_len_ram_out;
reg [4:0] irq_log_r;
wire [29:0] irq_log_decoded_w;
reg gen_irq;
reg [3:0] irqs_aclk;
wire [29:0] ptr_ram_out;
wire [2:0] sa_len_ra;
reg ptr_we; // write to the pointer memory
......@@ -105,11 +111,13 @@ module mult_saxi_wr_pointers#(
// 8x30 RAM for address/length
reg [29:0] sa_len_ram[0:7]; // start chunk/num cunks in a buffer (write port @mclk)
// 4*5 RAM to store number of dword conters that need to chnage to generate interrupt
reg [4:0] irq_log_ram[0:3];
always @ (posedge mclk) begin
if (sa_len_we) sa_len_ram[sa_len_wa] <= sa_len_di;
if (sa_len_we) sa_len_ram[sa_len_wa] <= sa_len_di;
if (irq_log_we) irq_log_ram[sa_len_wa[1:0]] <= sa_len_di[4:0];
end
assign sa_len_ram_out = sa_len_ram[sa_len_ra];
// 4 x 30 RAM for current pointers
reg [29:0] ptr_ram[0:3]; // start chunk/num cunks in a buffer (write port @mclk)
always @ (posedge aclk) begin
......@@ -158,14 +166,28 @@ module mult_saxi_wr_pointers#(
ptr_we <= resetting[0] || seq[1];
if (seq[0]) irq_log_r <= irq_log_ram[chn_r];
gen_irq <= seq[1] && (|((ptr_inc ^ ptr_ram_out) & irq_log_decoded_w));
irqs_aclk <= gen_irq? {chn_r[1] & chn_r[0], chn_r[1] & ~chn_r[0], ~chn_r[1] & chn_r[0], ~chn_r[1] & ~chn_r[0]}:4'b0;
// add one extra register layer here?
end
generate
genvar i;
for (i = 0; i < 30; i = i+1) begin: decoder_block
assign irq_log_decoded_w[i] = i >= irq_log_r;
end
endgenerate
pulse_cross_clock #(.EXTRA_DLY(1)) rst_pntr_aclk0_i (.rst(rst), .src_clk(mclk), .dst_clk(aclk), .in_pulse(rst_pntr_mclk[0]), .out_pulse(rst_pntr_aclk[0]),.busy());
pulse_cross_clock #(.EXTRA_DLY(1)) rst_pntr_aclk1_i (.rst(rst), .src_clk(mclk), .dst_clk(aclk), .in_pulse(rst_pntr_mclk[1]), .out_pulse(rst_pntr_aclk[1]),.busy());
pulse_cross_clock #(.EXTRA_DLY(1)) rst_pntr_aclk2_i (.rst(rst), .src_clk(mclk), .dst_clk(aclk), .in_pulse(rst_pntr_mclk[2]), .out_pulse(rst_pntr_aclk[2]),.busy());
pulse_cross_clock #(.EXTRA_DLY(1)) rst_pntr_aclk3_i (.rst(rst), .src_clk(mclk), .dst_clk(aclk), .in_pulse(rst_pntr_mclk[3]), .out_pulse(rst_pntr_aclk[3]),.busy());
pulse_cross_clock irqs0_i (.rst(rst_aclk), .src_clk(aclk), .dst_clk(mclk), .in_pulse(irqs_aclk[0]), .out_pulse(irqs[0]),.busy());
pulse_cross_clock irqs1_i (.rst(rst_aclk), .src_clk(aclk), .dst_clk(mclk), .in_pulse(irqs_aclk[1]), .out_pulse(irqs[1]),.busy());
pulse_cross_clock irqs2_i (.rst(rst_aclk), .src_clk(aclk), .dst_clk(mclk), .in_pulse(irqs_aclk[2]), .out_pulse(irqs[2]),.busy());
pulse_cross_clock irqs3_i (.rst(rst_aclk), .src_clk(aclk), .dst_clk(mclk), .in_pulse(irqs_aclk[3]), .out_pulse(irqs[3]),.busy());
endmodule
fpga_version.vh
View file @ 3ed89577
......@@ -35,7 +35,9 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h0393009b; // parallel, bug fixed in dct_chen 79.58, timing met (2015.3)
parameter FPGA_VERSION = 32'h0393009d; // hispi, adding IRQ from multi_saxi 80.95%, timing not met (-0.034 )
// parameter FPGA_VERSION = 32'h0393009c; // parallel, adding IRQ from multi_saxi 79.31% , timing met (2015.3)
// parameter FPGA_VERSION = 32'h0393009b; // parallel, bug fixed in dct_chen 79.58, timing met (2015.3)
// parameter FPGA_VERSION = 32'h0393009a; // serial, bug fixed in dct_chen 80.94%, timing met (2015.3)
// parameter FPGA_VERSION = 32'h03930099; // parallel, with dct_chen, all met, 79.2%
// parameter FPGA_VERSION = 32'h03930098; // serial, trying dct_chen - works, removing old completely, constraints met80.?%
......
includes/x393_parameters.vh
View file @ 3ed89577
......@@ -829,7 +829,11 @@
parameter MULT_SAXI_WLOG = 4, // number of bits for the input data ( 3 - 8 bit, 4 - 16-bit, 5 - 32-bit
parameter MULT_SAXI_ADDR = 'h730, // ..'h737
parameter MULT_SAXI_CNTRL_ADDR = 'h738, // ..'h739
parameter MULT_SAXI_IRQLEN_ADDR = 'h738, // ..'h73b
parameter MULT_SAXI_CNTRL_ADDR = 'h73c, // ..'h73e
parameter MULT_SAXI_CNTRL_MODE = 'h0, // 'h73c offset for mode register
parameter MULT_SAXI_CNTRL_STATUS = 'h1, // 'h73d offset for status control register
parameter MULT_SAXI_CNTRL_IRQ = 'h2, // 'h73e offset for IRQ contgrol register (4 dibits): 0 - nop, 1 reset, 2 - disable, 3 - enable
parameter MULT_SAXI_STATUS_REG = 'h34, //..'h37 uses 4 consecutive locations
parameter MULT_SAXI_HALF_BRAM = 1, // 0 - use full 36Kb BRAM for the buffer, 1 - use just half
parameter MULT_SAXI_BSLOG0 = 4, // number of bits to represent burst size (4 - b.s. = 16, 0 - b.s = 1)
......@@ -837,7 +841,8 @@
parameter MULT_SAXI_BSLOG2 = 4,
parameter MULT_SAXI_BSLOG3 = 4,
parameter MULT_SAXI_MASK = 'h7f8, // 4 address/length pairs. In bytes, but lower bits are set to 0?
parameter MULT_SAXI_CNTRL_MASK = 'h7fe, // mode and status - 2 locations
parameter MULT_SAXI_IRQLEN_MASK = 'h7fc, // number of address bits to change for interrupt - 4 locations
parameter MULT_SAXI_CNTRL_MASK = 'h7fc, // mode, status, irq - 3 locations
parameter MULT_SAXI_AWCACHE = 4'h3, //..7 cache mode (4 bits, default 4'h3)
parameter MULT_SAXI_ADV_WR = 4, // number of clock cycles before end of write to genearte adv_wr_done
parameter MULT_SAXI_ADV_RD = 3, // number of clock cycles before end of write to genearte adv_wr_done
......
py393/vrlg.py
View file @ 3ed89577
This diff is collapsed.
py393/x393_export_c.py
View file @ 3ed89577
......@@ -586,6 +586,18 @@ class X393ExportC(object):
data = self._enc_mult_saxi_addr(),
name = "x393_mult_saxi_al", typ="rw", # some - wo, others - ro
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "MULT_SAXI DMA DW address bit to change for interrupt to be generated",
data = self._enc_mult_saxi_irqlen(),
name = "x393_mult_saxi_irqlen", typ="rw", # some - wo, others - ro
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "MULT_SAXI DMA mode register (per channel enable/run)",
data = self._enc_mult_saxi_mode(),
name = "x393_mult_saxi_mode", typ="rw", # some - wo, others - ro
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "MULT_SAXI per-channel interrupt control",
data = self._enc_mult_saxi_interrupts(),
name = "x393_mult_saxi_interrupts", typ="wo", # some - wo, others - ro
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "MULTICLK reset/power down controls",
data = self._enc_multiclk_ctl(),
......@@ -1066,7 +1078,7 @@ class X393ExportC(object):
sdefines +=[
(('Event logger',)),
(('_Event logger configuration/data is writtent to the module ising two 32-bit register locations : data and address.',)),
(('_Event logger configuration/data is written to the module using two 32-bit register locations : data and address.',)),
(('_Address consists of 2 parts - 2-bit page (configuration, imu, gps, message) and a 5-bit sub-address autoincremented when writing data.',)),
(('_Register pages:',)),
(("X393_LOGGER_PAGE_CONF", "", 0 , 0, None, None, "", "Logger configuration page")),
......@@ -1091,10 +1103,13 @@ class X393ExportC(object):
c = "chn"
sdefines +=[
(('MULT SAXI DMA engine control. Of 4 channels only one (number 0) is currently used - for the event logger',)),
(("X393_MULT_SAXI_STATUS_CTRL", "", vrlg.MULT_SAXI_CNTRL_ADDR, 0, None, "x393_status_ctrl", "rw", "MULT_SAXI status control mode (status provides current DWORD pointer)")),
(("X393_MULT_SAXI_BUF_ADDRESS", c, vrlg.MULT_SAXI_ADDR + 0, 2, z3, "x393_mult_saxi_al", "wo", "MULT_SAXI buffer start address in DWORDS")),
(("X393_MULT_SAXI_BUF_LEN", c, vrlg.MULT_SAXI_ADDR + 1, 2, z3, "x393_mult_saxi_al", "wo", "MULT_SAXI buffer length in DWORDS")),
(("X393_MULT_SAXI_STATUS", c, vrlg.STATUS_ADDR + vrlg.MULT_SAXI_STATUS_REG, 1, z3, "x393_mult_saxi_al", "ro", "MULT_SAXI current DWORD pointer"))]
(("X393_MULT_SAXI_MODE", "", vrlg.MULT_SAXI_CNTRL_ADDR+vrlg.MULT_SAXI_CNTRL_MODE, 0, None, "x393_mult_saxi_mode", "rw","MULT_SAXI mode register (per-channel enable and run bits)")),
(("X393_MULT_SAXI_STATUS_CTRL", "", vrlg.MULT_SAXI_CNTRL_ADDR+vrlg.MULT_SAXI_CNTRL_STATUS, 0, None, "x393_status_ctrl", "rw","MULT_SAXI status control mode (status provides current DWORD pointers)")),
(("X393_MULT_SAXI_INTERRUPTS", "", vrlg.MULT_SAXI_CNTRL_ADDR+vrlg.MULT_SAXI_CNTRL_IRQ, 0, None, "x393_mult_saxi_interrupts", "wo","MULT_SAXI per-channel interrupts control (each dibit:nop/reset/disable/enable)")),
(("X393_MULT_SAXI_BUF_ADDRESS", c, vrlg.MULT_SAXI_ADDR + 0, 2, z3, "x393_mult_saxi_al", "wo","MULT_SAXI buffer start address in DWORDS")),
(("X393_MULT_SAXI_BUF_LEN", c, vrlg.MULT_SAXI_ADDR + 1, 2, z3, "x393_mult_saxi_al", "wo","MULT_SAXI buffer length in DWORDS")),
(("X393_MULT_SAXI_IRQLEN", c, vrlg.MULT_SAXI_IRQLEN_ADDR, 1, z3, "x393_mult_saxi_al", "wo","MULT_SAXI lower DWORD address bit to change to generate interrupt")),
(("X393_MULT_SAXI_STATUS", c, vrlg.STATUS_ADDR + vrlg.MULT_SAXI_STATUS_REG, 1, z3, "x393_mult_saxi_al", "ro","MULT_SAXI current DWORD pointer"))]
#MULTI_CLK global clock generation PLLs
ba = 0
......@@ -2329,9 +2344,33 @@ class X393ExportC(object):
def _enc_mult_saxi_addr(self):
dw=[]
dw.append(("addr32", 0, 30, 0, "SAXI sddress/length in DWORDs"))
dw.append(("addr32", 0, 30, 0, "SAXI address/length in DWORDs"))
return dw
def _enc_mult_saxi_irqlen(self):
dw=[]
dw.append(("irqlen", 0, 5, 0, "lowest DW address bit that has to change to generate interrupt"))
return dw
def _enc_mult_saxi_mode(self):
dw=[]
dw.append(("en0", 0, 1, 0, "Channel 0 enable (0 - reset)"))
dw.append(("en1", 1, 1, 0, "Channel 1 enable (0 - reset)"))
dw.append(("en2", 2, 1, 0, "Channel 2 enable (0 - reset)"))
dw.append(("en3", 3, 1, 0, "Channel 3 enable (0 - reset)"))
dw.append(("run0", 4, 1, 0, "Channel 0 run (0 - stop)"))
dw.append(("run1", 5, 1, 0, "Channel 1 run (0 - stop)"))
dw.append(("run2", 6, 1, 0, "Channel 2 run (0 - stop)"))
dw.append(("run3", 7, 1, 0, "Channel 3 run (0 - stop)"))
return dw
def _enc_mult_saxi_interrupts(self):
dw=[]
dw.append(("interrupt_cmd0", 0, 2, 0, "Channel 0 command - 0: nop, 1: clear interrupt status, 2: disable interrupt, 3: enable interrupt"))
dw.append(("interrupt_cmd1", 2, 2, 0, "Channel 1 command - 0: nop, 1: clear interrupt status, 2: disable interrupt, 3: enable interrupt"))
dw.append(("interrupt_cmd2", 4, 2, 0, "Channel 2 command - 0: nop, 1: clear interrupt status, 2: disable interrupt, 3: enable interrupt"))
dw.append(("interrupt_cmd3", 6, 2, 0, "Channel 3 command - 0: nop, 1: clear interrupt status, 2: disable interrupt, 3: enable interrupt"))
return dw
def _enc_multiclk_ctl(self):
dw=[]
dw.append(("rst_clk0", 0, 1, 0, "Reset PLL for xclk(240MHz), hclk(150MHz)"))
......
system_defines.vh
View file @ 3ed89577
......@@ -63,7 +63,7 @@
`define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels
// `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
`define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
// `define USE_OLD_XDCT393
// `define USE_PCLK2X
// `define USE_XCLK2X
......
x393.v
View file @ 3ed89577
......@@ -548,6 +548,7 @@ module x393 #(
wire [3:0] stuffer_done_mclk; // output// SuppressThisWarning VEditor - (yet) unused
wire [3:0] cmprs_irq; // compressor done, data confirmed written to memory)
wire [3:0] mult_saxi_irq; // interrupts from mult_saxi channels
// Compressor frame synchronization
......@@ -2323,7 +2324,11 @@ assign axi_grst = axi_rst_pre;
mult_saxi_wr #(
.MULT_SAXI_ADDR (MULT_SAXI_ADDR),
.MULT_SAXI_IRQLEN_ADDR (MULT_SAXI_IRQLEN_ADDR),
.MULT_SAXI_CNTRL_ADDR (MULT_SAXI_CNTRL_ADDR),
.MULT_SAXI_CNTRL_MODE (MULT_SAXI_CNTRL_MODE),
.MULT_SAXI_CNTRL_STATUS (MULT_SAXI_CNTRL_STATUS),
.MULT_SAXI_CNTRL_IRQ (MULT_SAXI_CNTRL_IRQ),
.MULT_SAXI_STATUS_REG (MULT_SAXI_STATUS_REG),
.MULT_SAXI_HALF_BRAM (MULT_SAXI_HALF_BRAM),
.MULT_SAXI_BSLOG0 (MULT_SAXI_BSLOG0),
......@@ -2331,6 +2336,7 @@ assign axi_grst = axi_rst_pre;
.MULT_SAXI_BSLOG2 (MULT_SAXI_BSLOG2),
.MULT_SAXI_BSLOG3 (MULT_SAXI_BSLOG3),
.MULT_SAXI_MASK (MULT_SAXI_MASK),
.MULT_SAXI_IRQLEN_MASK (MULT_SAXI_IRQLEN_MASK),
.MULT_SAXI_CNTRL_MASK (MULT_SAXI_CNTRL_MASK),
.MULT_SAXI_AWCACHE (MULT_SAXI_AWCACHE),
.MULT_SAXI_ADV_WR (MULT_SAXI_ADV_WR),
......@@ -2367,28 +2373,29 @@ assign axi_grst = axi_rst_pre;
.read_burst3 (), // output
.data_in_chn3 (32'b0), // input[31:0]
.pre_valid_chn3 (1'b0), // input
.irq (mult_saxi_irq[3:0]), // output[3:0]
.saxi_awaddr (saxi1_awaddr), // output[31:0]
.saxi_awvalid (saxi1_awvalid), // output
.saxi_awready (saxi1_awready), // input
.saxi_awid (saxi1_awid), // output[5:0]
.saxi_awlock (saxi1_awlock), // output[1:0]
.saxi_awcache (saxi1_awcache), // output[3:0]
.saxi_awprot (saxi1_awprot), // output[2:0]
.saxi_awlen (saxi1_awlen), // output[3:0]
.saxi_awsize (saxi1_awsize), // output[1:0]
.saxi_awburst (saxi1_awburst), // output[1:0]
.saxi_awqos (saxi1_awqos), // output[3:0]
.saxi_wdata (saxi1_wdata), // output[31:0]
.saxi_wvalid (saxi1_wvalid), // output
.saxi_wready (saxi1_wready), // input
.saxi_wid (saxi1_wid), // output[5:0]
.saxi_wlast (saxi1_wlast), // output
.saxi_wstrb (saxi1_wstrb), // output[3:0]
.saxi_bvalid (saxi1_bvalid), // input
.saxi_bready (saxi1_bready), // output
.saxi_bid (saxi1_bid), // input[5:0]
.saxi_bresp (saxi1_bresp) // input[1:0]
.saxi_awaddr (saxi1_awaddr), // output[31:0]
.saxi_awvalid (saxi1_awvalid), // output
.saxi_awready (saxi1_awready), // input
.saxi_awid (saxi1_awid), // output[5:0]
.saxi_awlock (saxi1_awlock), // output[1:0]
.saxi_awcache (saxi1_awcache), // output[3:0]
.saxi_awprot (saxi1_awprot), // output[2:0]
.saxi_awlen (saxi1_awlen), // output[3:0]
.saxi_awsize (saxi1_awsize), // output[1:0]
.saxi_awburst (saxi1_awburst), // output[1:0]
.saxi_awqos (saxi1_awqos), // output[3:0]
.saxi_wdata (saxi1_wdata), // output[31:0]
.saxi_wvalid (saxi1_wvalid), // output
.saxi_wready (saxi1_wready), // input
.saxi_wid (saxi1_wid), // output[5:0]
.saxi_wlast (saxi1_wlast), // output
.saxi_wstrb (saxi1_wstrb), // output[3:0]
.saxi_bvalid (saxi1_bvalid), // input
.saxi_bready (saxi1_bready), // output
.saxi_bid (saxi1_bid), // input[5:0]
.saxi_bresp (saxi1_bresp) // input[1:0]
);
clocks393m #(
......@@ -2943,7 +2950,7 @@ sata_ahci_top sata_top(
.DMA3DATYPE(), // DMAC 3 DMA Ackbowledge TYpe (completed single AXI, completed burst AXI, flush request), output
.DMA3RSTN(), // DMAC 3 RESET output (reserved, do not use), output
// Interrupt signals
.IRQF2P({4'b0,
.IRQF2P({mult_saxi_irq[3:0], // [19:16] interrupts from mult_saxi channels
cmprs_irq[3:0], // [15:12] Compressor done interrupts
frseq_irq[3:0], // [11: 8] Frame sync interrupts
7'b0,
......
x393_hispi.bit
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x393_parallel.bit
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