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x393
Commit 3b76078a authored by Andrey Filippov's avatar Andrey Filippov
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last dct branch mods

parent 3bb9ab01
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Showing with 273 additions and 222 deletions
compressor_jp/compressor393.v
View file @ 3b76078a
......@@ -39,6 +39,7 @@
`timescale 1ns/1ps
module compressor393 # (
parameter CMPRS_CHN_MASK = 4'hf, // specify wich compressor channels to use (disable some/all to make room for processing)
parameter CMPRS_NUM_AFI_CHN = 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
parameter CMPRS_BASE_INC = 'h10,
......@@ -340,6 +341,7 @@ module compressor393 # (
generate
genvar i;
for (i=0; i < 4; i=i+1) begin: cmprs_channel_block
if (CMPRS_CHN_MASK & (1<<i)) begin
jp_channel #(
.CMPRS_NUMBER (i),
.CMPRS_GROUP_ADDR (CMPRS_GROUP_ADDR),
......@@ -413,15 +415,15 @@ module compressor393 # (
.CMPRS_TIMEOUT_BITS (CMPRS_TIMEOUT_BITS),
.CMPRS_TIMEOUT (CMPRS_TIMEOUT),
.NUM_FRAME_BITS (NUM_FRAME_BITS)
`ifdef DEBUG_RING
`ifdef DEBUG_RING
,.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
`endif
`endif
) jp_channel_i (
// .rst (rst), // input
// .rst (rst), // input
.xclk (xclk), // input
`ifdef USE_XCLK2X
`ifdef USE_XCLK2X
.xclk2x (xclk2x), // input
`endif
`endif
.mrst (mrst), // input
.xrst (xrst), // input
.hrst (hrst), // input
......@@ -473,11 +475,31 @@ module compressor393 # (
.fifo_count (fifo_count[8* i +: 8]) // output[7:0]
`ifdef DEBUG_RING
,.debug_do (debug_ring[i]), // output
.debug_sl (debug_sl), // output
.debug_sl (debug_sl), // input
.debug_di (debug_ring[i+1]) // input
`endif
`endif
);
end else begin
// assign unused outputs from missing jp_channel instances
assign status_ad_mux[8 * i +: 8] = 'bx;
assign status_rq_mux[i] = 'b0;
assign cmprs_irq[i] = 'b0;
assign next_page[i] = 'b0;
assign frame_start_dst[i] = 'b0;
assign suspend[i] = 'b0;
assign eof_written_mclk[i] = 'b0;
assign eof_written_mclk[i] = 'b0;
assign stuffer_done_mclk[i] = 'b0;
assign fifo_rdata[64 * i +: 64] = 'bx;
assign fifo_eof[i] = 'b0;
assign fifo_flush[i] = 'b0;
assign flush_hclk[i] = 'b0;
assign fifo_count[8* i +: 8] = 'bx;
`ifdef DEBUG_RING
assign debug_ring[i] = 'bx;
`endif
end
end
endgenerate
......
fpga_version.vh
View file @ 3b76078a
......@@ -35,7 +35,11 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h039300d9; //parallel - correcting histograms -0.022/1, 79.60%
parameter FPGA_VERSION = 32'h03930103; //parallel - three compressor channels -0.177/37, 74.94%
// parameter FPGA_VERSION = 32'h03930102; //parallel - two compressor channels - all met, 67.75%
// parameter FPGA_VERSION = 32'h03930101; //parallel - single compressor channel all met, 61.25%
// parameter FPGA_VERSION = 32'h03930100; //parallel - removing some compressors to make room for DCT-based processing -0.004/3, 80.17 - all channels,
// parameter FPGA_VERSION = 32'h039300d9; //parallel - correcting histograms -0.022/1, 79.60%
// parameter FPGA_VERSION = 32'h039300d8; //parallel - SATA is now logging irq on/off -0.054 /16, 80.50%
// parameter FPGA_VERSION = 32'h039300d7; //parallel - updated SATA (v12) all met, 80.32%
// parameter FPGA_VERSION = 32'h039300d6; //parallel - more SATA debug link layer -0.127/18, 80.03% -> -0.002/4, 80.26%
......
includes/x393_parameters.vh
View file @ 3b76078a
......@@ -661,7 +661,10 @@
// parameter HISPI_IOSTANDARD = "PPDS_25", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
// parameter HISPI_IOSTANDARD = "DIFF_HSTL_II_18", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
//`endif DIFF_HSTL_II_18
// parameter CMPRS_CHN_MASK = 4'hf, // all channels (specify wich compressor channels to use (disable some/all to make room for processing))
// parameter CMPRS_CHN_MASK = 4'h1, // single channel (specify wich compressor channels to use (disable some/all to make room for processing))
// parameter CMPRS_CHN_MASK = 4'h3, // two channels (specify wich compressor channels to use (disable some/all to make room for processing))
parameter CMPRS_CHN_MASK = 4'h7, // three channels (specify wich compressor channels to use (disable some/all to make room for processing))
parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
......
memctrl/mcntrl393.v
View file @ 3b76078a
......@@ -39,6 +39,7 @@
`timescale 1ns/1ps
`include "system_defines.vh"
module mcntrl393 #(
parameter CMPRS_CHN_MASK = 4'hf, // specify wich compressor channels to use (disable some/all to make room for processing)
// MAXI address space, in 32-bit words
parameter MCONTR_SENS_BASE = 'h680, // .. 'h6bf
parameter MCONTR_SENS_INC = 'h10,
......@@ -1159,7 +1160,7 @@ module mcntrl393 #(
,.dbg_wpage (dbg_wpage[2*i +:2]) // input[1:0]
`endif
);
if (CMPRS_CHN_MASK & (1<<i)) begin
mcntrl_tiled_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
......@@ -1216,7 +1217,7 @@ module mcntrl393 #(
.frames_in_sync (cmprs_frames_in_sync[i]), // output
.master_frame (cmprs_frame_number_src[i * LAST_FRAME_BITS +: LAST_FRAME_BITS]), // input[15:0]
.master_set (sens_frame_set[i]), // input
// .master_follow (master_follow[i]), // input
// .master_follow (master_follow[i]), // input
.xfer_want (cmprs_want[i]), // output
.xfer_need (cmprs_need[i]), // output
.xfer_grant (cmprs_channel_pgm_en[i]), // input
......@@ -1236,11 +1237,29 @@ module mcntrl393 #(
.xfer_page_rst_wr (), // output
.xfer_page_rst_rd (cmprs_xfer_reset_page_rd[i]) // output @negedge
);
end else begin
// assign unused outputs from missing mcntrl_tiled_rd_compressor_i instances
assign status_cmprs_ad[i * 8 +: 8] = 'bx;
assign status_cmprs_rq[i] = 'b0;
assign cmprs_frame_start_conf[i] = 'b0;
assign cmprs_frame_done_dst[i] = 'b0;
assign cmprs_line_unfinished_dst[i * FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS] = 'bx;
assign cmprs_frame_number_dst[i * LAST_FRAME_BITS +: LAST_FRAME_BITS] = 'bx;
assign cmprs_frames_in_sync[i] = 'b0;
assign cmprs_want[i] = 'b0;
assign cmprs_need[i] = 'b0;
assign cmprs_start_rd16[i] = 'b0;
assign cmprs_start_rd32[i] = 'b0;
assign cmprs_bank[i * 3 +: 3] = 'b0;
assign cmprs_row[ADDRESS_NUMBER * i +: ADDRESS_NUMBER] = 'bx;
assign cmprs_col[COL_WDTH * i +: COL_WDTH] = 'bx;
assign cmprs_rowcol_inc[i * FRAME_WBP1 +: FRAME_WBP1] = 'bx;
assign cmprs_num_rows_m1[i * MAX_TILE_WIDTH +: MAX_TILE_WIDTH] = 'bx;
assign cmprs_num_cols_m1[i * MAX_TILE_HEIGHT +: MAX_TILE_HEIGHT] = 'bx;
assign cmprs_keep_open[i] = 'bx;
assign cmprs_partial[i] = 'bx;
assign cmprs_xfer_reset_page_rd[i] = 'bx;
end
end
endgenerate
......
x393.v
View file @ 3b76078a
......@@ -1144,6 +1144,7 @@ assign axi_grst = axi_rst_pre;
);
mcntrl393 #(
.CMPRS_CHN_MASK (CMPRS_CHN_MASK),
.MCONTR_SENS_BASE (MCONTR_SENS_BASE),
.MCONTR_SENS_INC (MCONTR_SENS_INC),
.MCONTR_CMPRS_BASE (MCONTR_CMPRS_BASE),
......@@ -1266,6 +1267,7 @@ assign axi_grst = axi_rst_pre;
.MAX_TILE_HEIGHT (MAX_TILE_HEIGHT),
.MCNTRL_TILED_CHN2_ADDR (MCNTRL_TILED_CHN2_ADDR),
.MCNTRL_TILED_CHN4_ADDR (MCNTRL_TILED_CHN4_ADDR),
.MCNTRL_TILED_MASK (MCNTRL_TILED_MASK),
.MCNTRL_TILED_MODE (MCNTRL_TILED_MODE),
.MCNTRL_TILED_STATUS_CNTRL (MCNTRL_TILED_STATUS_CNTRL),
......@@ -1978,6 +1980,7 @@ assign axi_grst = axi_rst_pre;
wire afi2_wrissuecap1en; // output
compressor393 #(
.CMPRS_CHN_MASK (CMPRS_CHN_MASK),
.CMPRS_NUM_AFI_CHN (CMPRS_NUM_AFI_CHN),
.CMPRS_GROUP_ADDR (CMPRS_GROUP_ADDR),
.CMPRS_BASE_INC (CMPRS_BASE_INC),
......
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