merged with framepars branch

fpga_version.vh

@@ -35,7 +35,10 @@
  * contains all the components and scripts required to completely simulate it
  * with at least one of the Free Software programs.
  */
-        parameter FPGA_VERSION =          32'h039300b9;      //parallel, correcting RTC (it was 25/24 faster) -0.038/29, 79.64%
+        parameter FPGA_VERSION =          32'h039300bc;      //parallel, 100kHz min i2c speed -0.076/8, 79.69%
+//        parameter FPGA_VERSION =          32'h039300bb;      //parallel, adding i2c almost full. -0.101/8, 79.37%
+//      parameter FPGA_VERSION =          32'h039300ba;      //parallel, fixing introduced by debug bug in sens_parallel12.v: met, 80.03%
+//      parameter FPGA_VERSION =          32'h039300b9;      //parallel, correcting RTC (it was 25/24 faster) -0.038/29, 79.64%
 //      parameter FPGA_VERSION =          32'h039300b8;      //parallel, working on camsync -0.330/99, 80.52% -> -0.143 /40, 79.88% 
 //      parameter FPGA_VERSION =          32'h039300b7;      //parallel, matching histograms Bayer to gamma bayer -0.011/9, 79.92%
 //      parameter FPGA_VERSION =          32'h039300b6;      //parallel, working on histograms odd colors bug -0.207 /58,  79.68%

py393/hargs-after

@@ -5,5 +5,4 @@
 -p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
 -c bitstream_set_path /usr/local/verilog/x393_parallel.bit
 -c specify_phys_memory
--c specify_window
 -i

py393/hargs-eyesis

+-d TARGET_MODE=1
+-f /usr/local/verilog/system_defines.vh
+-f /usr/local/verilog/x393_parameters.vh   /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
+-l /usr/local/verilog/x393_cur_params_target.vh
+-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
+-c bitstream_set_path /usr/local/verilog/x393_parallel.bit
+-c setupEyesisPower 50 100
+-c measure_all "*DI"
+-c setSensorClock 24.0 "2V5_LVDS"
+-c set_rtc

py393/x393_export_c.py

@@ -1826,7 +1826,7 @@ class X393ExportC(object):
         dw.append(("i2c_fifo_nempty",        8, 1,0,  "I2C read FIFO has data"))
         dw.append(("i2c_fifo_lsb",           9, 1,0,  "I2C FIFO byte counter (odd/even bytes)"))
         dw.append(("busy",                  10, 1,0,  "I2C sequencer busy"))
-        dw.append(("alive_fs",              11, 1,0,  "Sensor generated frame sync since last status update"))
+        dw.append(("wr_full",               11, 1,0,  "Write buffer almost full (1/4..3/4 in ASAP mode)"))
         dw.append(("frame_num",             12, 4,0,  "I2C sequencer frame number"))
         dw.append(("req_clr",               16, 1,0,  "Request for clearing fifo_wp (delay frame sync if previous is not yet sent out)"))
         dw.append(("reset_on",              17, 1,0,  "Reset in progress"))

py393/x393_jpeg.py

@@ -1072,6 +1072,8 @@ camsync_setup 0xf # sensor mask - use local timestamps)
 jpeg_write  "img.jpeg" 0 80
 
 ####### Parallel - setup sensor 1 (sensor 0 is set by drivers) ##############
+cd /usr/local/verilog/; test_mcntrl.py @hargs-after
+
 setup_all_sensors True None 0x2 # sensor 1
 set_sensor_io_ctl  1 None None 1 # Set ARO low - check if it is still needed?
 #set quadrants
@@ -1099,6 +1101,8 @@ jpeg_write  "img.jpeg" 1 80
 
 
 ################## Parallel ##################
+cd /usr/local/verilog/; test_mcntrl.py @hargs-after
+
 cd /usr/local/verilog/; test_mcntrl.py @tpargs -x
 
 
@@ -1903,8 +1907,8 @@ set_gpio_ports  1   1 # enable software gpio pins and porta (camsync)
 set_gpio_pins 0 1 # pin 0 low, pin 1 - high
 
 set_camsync_period 31 # set bit duration
-set_camsync_period 7500 # 75 usec
-set_camsync_delay 0 0
+set_camsync_period  8000 # 80 usec
+set_camsync_delay 0 400
 set_camsync_delay 1 100
 set_camsync_delay 2 200
 set_camsync_delay 3 300
@@ -2014,7 +2018,7 @@ jpeg_sim_multi 4
 #set_camsync_mode  <en=None>  <en_snd=None>  <en_ts_external=None>  <triggered_mode=None>  <master_chn=None>  <chn_en=None> 
 set_camsync_mode     None        None            None                      0
 jpeg_sim_multi 4
-jpeg_sim_multi 4
+jpeg_sim_multi 8
 
 
 

py393/x393_sens_cmprs.py

@@ -59,6 +59,10 @@ PAGE_SIZE =           4096
 SI5338_PATH =         '/sys/devices/soc0/amba@0/e0004000.ps7-i2c/i2c-0/0-0070'
 POWER393_PATH =       '/sys/devices/soc0/elphel393-pwr@0'
 MEM_PATH =            '/sys/devices/soc0/elphel393-mem@0/'
+EYESIS_POWER_PATH=    '/sys/devices/soc0/elphel393-pwr@0/gpio_10389'
+EYESIS_POWER_ON=      '0x101'
+EYESIS_POWER_OFF=     '0x100'
+
 
 BUFFER_ADDRESS_NAME = 'buffer_address'
 BUFFER_PAGES_NAME =   'buffer_pages'
@@ -271,8 +275,9 @@ class X393SensCmprs(object):
         """
         Sleep for specified number of milliseconds
         @param time_ms - sleep time in milliseconds
-        """    
-        time.sleep(0.001*time_ms)
+        """
+        if (time_ms):    
+            time.sleep(0.001*time_ms)
     def setSensorClock(self, freq_MHz = 24.0, iface = "2V5_LVDS", quiet = 0):
         """
         Set up external clock for sensor-synchronous circuitry (and sensor(s) themselves. 
@@ -314,11 +319,53 @@ class X393SensCmprs(object):
         if quiet == 0:
             print ("Set sensors %s interface voltage to %d mV"%(("0, 1","2, 3")[sub_pair],voltage_mv))    
         time.sleep(0.1)
+        
+    def setEyesisPower (self, en, dly_ms=0):
+        """
+        Turn on/off external power supply for Eyesis sensor ports. At startup stupid GPIO system
+        interface "thinks" it is off, but it is actually on. So to turn off after boot On-Off sequence
+        is needed
+        @param en True or 1 - turn power on, False or 0 - turn off
+        @param dly_ms - delay in ms after turning power on or off   
+        """
+        if self.DRY_MODE:
+            print ("setEyesisPower() is not defined for simulation mode")
+            return
+        with open (EYESIS_POWER_PATH,      "w") as f:
+            print((EYESIS_POWER_OFF,EYESIS_POWER_ON)[en], file = f)
+        self.sleep_ms(dly_ms)
+
+    def setupEyesisPower (self, dly1_ms = 50, dly2_ms=100):
+        """
+        1. Turn off external power supply for Eyesis sensor ports (it is on after boot),
+        2. Set interface voltage (should be with power off)
+        3. Turn on power
+        @param dly1_ms - delay time in ms after interface voltage
+        @param dly2_ms - delay time in ms after external power on/off
+        """
+        voltage_mv = SENSOR_INTERFACES['PAR12']["mv"]
+        if self.DRY_MODE:
+            print ("setupEyesisPower() is not defined for simulation mode")
+            return
+        #turn off external sensor power    
+        self.setEyesisPower (True,  0) # stupid GPIO after reset will not turn off if it thinks it is off 
+        self.setEyesisPower (False, dly2_ms)
+        #Turn off on-board sensor power (just in case)
+        for sub_pair in (0,1):
+            self.setSensorPower(sub_pair = sub_pair, power_on = 0)
+        for sub_pair in (0,1):
+            self.setSensorIfaceVoltage(sub_pair=sub_pair, voltage_mv = voltage_mv)
+            self.sleep_ms(dly1_ms)
+        self.setEyesisPower (True, dly2_ms)
+        #Turn on-board sensor power (just in case)
+        for sub_pair in (0,1):
+            self.setSensorPower(sub_pair = sub_pair, power_on = 0)
 
     def setupSensorsPower(self, ifaceType,  pairs = "all", quiet=0, dly=0.0):
         """
         Set interface voltage and turn on power for interface and the sensors
-        according to sensor type 
+        according to sensor type
+        @param ifaceType "PAR12" or "HISPI" 
         @param pairs - 'all' or list/tuple of pairs of the sensors: 0 - sensors 1 and 2, 1 - sensors 3 and 4 
         @param quiet - reduce output        
         @param dly - debug feature: step delay in sec        

py393/x393_sensor.py

@@ -240,7 +240,7 @@ class X393Sensor(object):
         print ("   reset_on =               %d"%((status>>17) & 1))
         print ("   req_clr =                %d"%((status>>16) & 1))
         print ("   frame_num =              %d"%((status>>12) & 0xf))
-        print ("   alive_fs =               %d"%((status>>11) & 1))
+        print ("   wr_full =                %d"%((status>>11) & 1))
         print ("   busy =                   %d"%((status>>10) & 1))
         print ("   i2c_fifo_lsb =           %d"%((status>> 9) & 1))
         print ("   i2c_fifo_nempty =        %d"%((status>> 8) & 1))
@@ -1326,7 +1326,7 @@ class X393Sensor(object):
         print ("print_status_sensor_i2c(%d):"%(num_sensor))
         print ("   reset_on =               %d"%((status>> 7) & 1))
         print ("   req_clr =                %d"%((status>> 6) & 1))
-        print ("   alive_fs =               %d"%((status>> 5) & 1))
+        print ("   wr_full =               %d"%((status>> 5) & 1))
         
         print ("   busy =                   %d"%((status>> 4) & 1))
         print ("   frame_num =              %d"%((status>> 0)  & 0xf))
@@ -1376,7 +1376,7 @@ setSensorClock
 
 checkSclSda 1
 
-cat /usr/local/verilog/x359.bit > /dev/sfpgaconfjtag1
+#cat /usr/local/verilog/x359.bit > /dev/sfpgaconfjtag1
 
 
 #jtag_set_pgm_mode 0 1

sensor/sens_parallel12.v

@@ -247,7 +247,7 @@ module  sens_parallel12 #(
                      xfpgatdo_byte[7:0],
                      vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm, 
                      clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
-                     ps_out,
+                     ps_rdy, ps_out,
                      xfpgatdo, senspgmin};
                         
     assign hact_out = hact_r;

sensor/sensor_i2c.v

@@ -196,7 +196,15 @@ module  sensor_i2c#(
      reg           was_asap;     
      reg     [3:0] last_wpage; // last written to page (or zeroed)
      reg     [5:0] fifo_fill;  // number of words written to the other (not current) page, or difference wp-rp for the current
-     wire    [5:0] fifo_wr_pointers_next; // pointer value to be written to  fifo_wr_pointers_ram[wpage_wr]    
+     wire    [5:0] fifo_wr_pointers_next; // pointer value to be written to  fifo_wr_pointers_ram[wpage_wr]
+     
+     // Preventing overflow when many i2c commands are written in ASAP mode (stopped compressor) 
+     wire    [1:0] send_diff= fifo_wr_pointers_outr[5:4] - rpointer[5:4]; // to determine buffer full in ASAP mode
+     wire          wr_full_w = (wpage0==wpage_wr)? // is it ASAP mode (i.e. sequencer is stopped, progr. 10359)
+                                send_diff[1]: // 1/4..3/4 full in ASAP mode
+                                (&fifo_wr_pointers_outw_r[5:2]); // current page almost full
+     reg           wr_full_r;                             
+// fifo_wr_pointers_outw_r         
      
      assign set_ctrl_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_CTRL );// ==0
      assign set_status_w = we_cmd && ((wa & ~SENSI2C_CTRL_MASK) == SENSI2C_STATUS );// ==0
@@ -217,13 +225,13 @@ module  sensor_i2c#(
      assign fifo_wr_pointers_next = wpage0_inc[1]? 6'h0:(fifo_wr_pointers_outw_r[5:0]+1);
 
 
-     
+/*    
     reg alive_fs;
     always @ (posedge mclk) begin
         if    (set_status_w) alive_fs <= 0;
         else if (frame_sync) alive_fs <= 1;
     end
-    
+*/    
 
     cmd_deser #(
         .ADDR        (SENSI2C_ABS_ADDR),
@@ -258,7 +266,10 @@ module  sensor_i2c#(
         .status     ({reset_on, req_clr,
                       fifo_fill[5:0],
                       frame_num[3:0],
-                      alive_fs,busy, i2c_fifo_cntrl, i2c_fifo_nempty,
+                      wr_full_r, // alive_fs,
+                      busy,
+                      i2c_fifo_cntrl,
+                      i2c_fifo_nempty,
                       i2c_fifo_dout[7:0],
                       sda_in, scl_in}), // input[25:0] 
         .ad         (status_ad), // output[7:0] 
@@ -281,6 +292,8 @@ module  sensor_i2c#(
     );
      
     always @ (posedge mclk) begin
+        wr_full_r <= wr_full_w;  // write buffer is almost full
+    
         if (wen) di_r <= di; // 32 bit command takes 6 cycles, so di_r can hold data for up to this long
         wen_r    <= {wen_r[0],wen}; // is it needed?      
 //        wen_fifo <= {wen_fifo[0],we_rel || we_abs};      
@@ -387,7 +400,7 @@ module  sensor_i2c#(
       else if (page_r_inc[0]) page_r <= page_r+1;
 `endif
 
-//############ rpointer should start not from 0, but form value in another RAM???
+//############ rpointer should start not from 0, but from the value in another RAM???
       if      (reset_cmd || page_r_inc[0])  rpointer[5:0] <= 6'h0;
       else if (i2c_run_d && ! i2c_run)      rpointer[5:0] <= rpointer[5:0] + 1;
 

sensor/sensor_i2c_scl_sda.v

@@ -38,7 +38,9 @@
  */
 `timescale 1ns/1ps
 
-module  sensor_i2c_scl_sda(
+module  sensor_i2c_scl_sda#
+(parameter I2C_REDUCE_SPEED_BITS = 1 // reduce i2c speed , 0: min = 200kHz, 1: 100kHz
+)(
     input         mrst,           // @ posedge mclk
     input         mclk,           // global clock
     input         i2c_rst,
@@ -63,7 +65,9 @@ module  sensor_i2c_scl_sda(
     wire         rst = mrst || i2c_rst;
     reg          is_open_r;
     reg    [8:0] sr;
-    reg    [7:0] dly_cntr;
+    reg  [I2C_REDUCE_SPEED_BITS + 7:0] dly_cntr;
+    wire [I2C_REDUCE_SPEED_BITS + 8:0] dly_cntr_w = {i2c_dly,{I2C_REDUCE_SPEED_BITS+1{1'b0}}}; // to handle 0-lengths
+    
     reg          busy_r;
     wire         snd_start_w =  snd_start && ready; //!busy_r;
     wire         snd_stop_w =   snd_stop && ready; // !busy_r;
@@ -137,7 +141,9 @@ module  sensor_i2c_scl_sda(
 //        if (!busy_r || dly_over_d) dly_cntr <= i2c_dly;
 //        else                       dly_cntr <= dly_cntr - 1;
         
-        if (!busy_w || dly_over) dly_cntr <= i2c_dly;
+//        if (!busy_w || dly_over) dly_cntr <= i2c_dly << I2C_REDUCE_SPEED_BITS;
+        if (!busy_w || dly_over) dly_cntr <= dly_cntr_w[I2C_REDUCE_SPEED_BITS+8 :1]; // top 8 bits
+        //
         else                     dly_cntr <= dly_cntr - 1;
         
         if (dly_over && seq_bit[1]) sda_r <= sda_in; // just before the end of SCL pulse - delay it by a few clocks to match external latencies?