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Commit 37190574 authored by Andrey Filippov's avatar Andrey Filippov
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more code for LWIR sensor

parent 691579c0
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cocotb/x393_cocotb_lwir_04.sav 0 → 100644
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includes/x393_parameters.vh
View file @ 37190574
...@@ -538,20 +538,20 @@ ...@@ -538,20 +538,20 @@
//`ifdef HISPI //`ifdef HISPI
//`elsif LWIR //`elsif LWIR
parameter VOSPI_EN = 0, parameter VOSPI_MRST = 0,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 2,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 4,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 6,
parameter VOSPI_RESET_CRC = 7,
parameter VOSPI_MRST = 8,
parameter VOSPI_MRST_BITS = 2, parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 10, parameter VOSPI_PWDN = 2,
parameter VOSPI_PWDN_BITS = 2, parameter VOSPI_PWDN_BITS = 2,
parameter VOSPI_MCLK = 12, parameter VOSPI_MCLK = 4,
parameter VOSPI_MCLK_BITS = 2, parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_EN = 6,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 8,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12,
parameter VOSPI_RESET_CRC = 13,
parameter VOSPI_SPI_CLK = 14, parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2, parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16, parameter VOSPI_GPIO = 16,
...@@ -568,7 +568,7 @@ ...@@ -568,7 +568,7 @@
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
//`else //`else
//sensor_fifo parameters //sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12, parameter SENSOR_DATA_WIDTH = 12,
...@@ -993,11 +993,20 @@ ...@@ -993,11 +993,20 @@
parameter CLKOUT_DIV_PCLK = 4, // 220 MHz parameter CLKOUT_DIV_PCLK = 4, // 220 MHz
parameter CLKOUT_DIV_PCLK2X = 2, // 440 MHz parameter CLKOUT_DIV_PCLK2X = 2, // 440 MHz
`else `else
// Python program bug - does not support elseif??
`ifdef LWIR
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
parameter CLKOUT_DIV_PCLK = 48, // 20 MHz
parameter CLKOUT_DIV_PCLK2X = 24, // 40 MHz
`else
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
parameter DIVCLK_DIVIDE_PCLK = 1, parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
parameter CLKOUT_DIV_PCLK = 10, // 96MHz parameter CLKOUT_DIV_PCLK = 10, // 96MHz
parameter CLKOUT_DIV_PCLK2X = 5, // 192 MHz parameter CLKOUT_DIV_PCLK2X = 5, // 192 MHz
`endif
`endif `endif
parameter PHASE_CLK2X_PCLK = 0.000, parameter PHASE_CLK2X_PCLK = 0.000,
parameter BUF_CLK1X_PCLK = "BUFG", parameter BUF_CLK1X_PCLK = "BUFG",
......
py393/vrlg.py
View file @ 37190574
...@@ -237,6 +237,7 @@ SENSI2C_ABS_RADDR__RAW = str ...@@ -237,6 +237,7 @@ SENSI2C_ABS_RADDR__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__RAW = str MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__RAW = str
CLKFBOUT_MULT = int CLKFBOUT_MULT = int
RTC_STATUS_REG_ADDR__RAW = str RTC_STATUS_REG_ADDR__RAW = str
VOSPI_MCLK_HALFDIV__RAW = str
SENS_LENS_C_MASK__RAW = str SENS_LENS_C_MASK__RAW = str
SIMULATE_CMPRS_CMODE0__RAW = str SIMULATE_CMPRS_CMODE0__RAW = str
NUM_CYCLES_11__TYPE = str NUM_CYCLES_11__TYPE = str
...@@ -417,6 +418,7 @@ SENS_LENS_BY_MASK__RAW = str ...@@ -417,6 +418,7 @@ SENS_LENS_BY_MASK__RAW = str
SENS_CTRL_GP0__TYPE = str SENS_CTRL_GP0__TYPE = str
DFLT_REFRESH_ADDR = int DFLT_REFRESH_ADDR = int
DLY_DQS_ODELAY__TYPE = str DLY_DQS_ODELAY__TYPE = str
DFLT_REFRESH_PERIOD__RAW = str
TEST01_SUSPEND__RAW = str TEST01_SUSPEND__RAW = str
SENS_GAMMA_HEIGHT01__TYPE = str SENS_GAMMA_HEIGHT01__TYPE = str
LWIR_TELEMETRY_AGC_LOW__RAW = str LWIR_TELEMETRY_AGC_LOW__RAW = str
...@@ -612,6 +614,7 @@ NUM_CYCLES_12 = int ...@@ -612,6 +614,7 @@ NUM_CYCLES_12 = int
MCNTRL_SCANLINE_FRAME_PAGE_RESET__TYPE = str MCNTRL_SCANLINE_FRAME_PAGE_RESET__TYPE = str
MCNTRL_TILED_CHN2_ADDR__TYPE = str MCNTRL_TILED_CHN2_ADDR__TYPE = str
NUM_CYCLES_11 = int NUM_CYCLES_11 = int
HIST_SAXI_ADDR_REL__TYPE = str
SENS_GAMMA_ADDR_MASK = int SENS_GAMMA_ADDR_MASK = int
NUM_CYCLES_10 = int NUM_CYCLES_10 = int
MEMCLK_IBUF_LOW_PWR__TYPE = str MEMCLK_IBUF_LOW_PWR__TYPE = str
...@@ -758,7 +761,7 @@ SENS_GAMMA_HEIGHT2 = int ...@@ -758,7 +761,7 @@ SENS_GAMMA_HEIGHT2 = int
DLY_LD_MASK__TYPE = str DLY_LD_MASK__TYPE = str
STATUS_MSB_RSHFT__TYPE = str STATUS_MSB_RSHFT__TYPE = str
MCONTR_BUF0_RD_ADDR = int MCONTR_BUF0_RD_ADDR = int
HIST_SAXI_ADDR_REL__TYPE = str VOSPI_RESET_CRC = int
CMPRS_CBIT_CMODE_JPEG20 = int CMPRS_CBIT_CMODE_JPEG20 = int
CMPRS_TIMEOUT_BITS = int CMPRS_TIMEOUT_BITS = int
CAMSYNC_PRE_MAGIC = int CAMSYNC_PRE_MAGIC = int
...@@ -1597,6 +1600,7 @@ SENS_CTRL_IGNORE_EMBED = int ...@@ -1597,6 +1600,7 @@ SENS_CTRL_IGNORE_EMBED = int
RTC_MASK__TYPE = str RTC_MASK__TYPE = str
MCNTRL_TILED_PENDING_CNTR_BITS = int MCNTRL_TILED_PENDING_CNTR_BITS = int
NUM_CYCLES_00__TYPE = str NUM_CYCLES_00__TYPE = str
VOSPI_MCLK_HALFDIV = int
CMPRS_MASK__RAW = str CMPRS_MASK__RAW = str
MEMBRIDGE_CTRL_IRQ__TYPE = str MEMBRIDGE_CTRL_IRQ__TYPE = str
MCNTRL_TEST01_MASK__RAW = str MCNTRL_TEST01_MASK__RAW = str
...@@ -1676,6 +1680,7 @@ LOGGER_PAGE_MSG = int ...@@ -1676,6 +1680,7 @@ LOGGER_PAGE_MSG = int
SENS_HIGH_PERFORMANCE_MODE = str SENS_HIGH_PERFORMANCE_MODE = str
WINDOW_X0 = int WINDOW_X0 = int
INITIALIZE_OFFSET__TYPE = str INITIALIZE_OFFSET__TYPE = str
VOSPI_RESET_CRC__TYPE = str
LOGGER_CONF_IMU_BITS__TYPE = str LOGGER_CONF_IMU_BITS__TYPE = str
LWIR_TELEMETRY_AGC_ROI_RIGHT__RAW = str LWIR_TELEMETRY_AGC_ROI_RIGHT__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI__TYPE = str MCONTR_PHY_16BIT_PATTERNS_TRI__TYPE = str
...@@ -2202,7 +2207,7 @@ MULT_SAXI_CNTRL_MODE__RAW = str ...@@ -2202,7 +2207,7 @@ MULT_SAXI_CNTRL_MODE__RAW = str
SENS_GAMMA_ADDR_DATA__TYPE = str SENS_GAMMA_ADDR_DATA__TYPE = str
VOSPI_OUT_EN__TYPE = str VOSPI_OUT_EN__TYPE = str
CAMSYNC_DELAY__TYPE = str CAMSYNC_DELAY__TYPE = str
DFLT_REFRESH_PERIOD__RAW = str VOSPI_RESET_CRC__RAW = str
SENS_REF_JITTER1__TYPE = str SENS_REF_JITTER1__TYPE = str
SENS_LENS_RADDR__RAW = str SENS_LENS_RADDR__RAW = str
MCONTR_PHY_0BIT_DCI_RST__TYPE = str MCONTR_PHY_0BIT_DCI_RST__TYPE = str
...@@ -2464,6 +2469,7 @@ WRITE_BLOCK_OFFSET__RAW = str ...@@ -2464,6 +2469,7 @@ WRITE_BLOCK_OFFSET__RAW = str
SENS_GAMMA_MODE_EN_SET = int SENS_GAMMA_MODE_EN_SET = int
MCONTR_LINTILE_SINGLE__RAW = str MCONTR_LINTILE_SINGLE__RAW = str
MCNTRL_TILED_FRAME_PAGE_RESET__RAW = str MCNTRL_TILED_FRAME_PAGE_RESET__RAW = str
VOSPI_MCLK_HALFDIV__TYPE = str
SENS_GAMMA_BUFFER__TYPE = str SENS_GAMMA_BUFFER__TYPE = str
SLEW_DQ__TYPE = str SLEW_DQ__TYPE = str
MCONTR_BUF4_RD_ADDR = int MCONTR_BUF4_RD_ADDR = int
......
py393/x393_export_c.py
View file @ 37190574
...@@ -2127,6 +2127,12 @@ class X393ExportC(object): ...@@ -2127,6 +2127,12 @@ class X393ExportC(object):
def _enc_sensio_ctrl_vospi(self): def _enc_sensio_ctrl_vospi(self):
dw=[] dw=[]
dw.append(("mrst", vrlg.VOSPI_MRST, 1, 0, "RESET signal level to the sensor (0 - low(active), 1 - high (inactive)"))
dw.append(("mrst_set", vrlg.VOSPI_MRST + 1, 1, 0, "When set to 1, RESET is set to the 'rst' field value"))
dw.append(("pwdn", vrlg.VOSPI_PWDN, 1, 0, "POWER DOWN signal level to the sensor (0 - low(active), 1 - high (inactive)"))
dw.append(("pwdn_set", vrlg.VOSPI_PWDN + 1, 1, 0, "When set to 1, POWER DOWN is set to the 'pwdn' field value"))
dw.append(("mclk", vrlg.VOSPI_MCLK, 1, 0, "Enable master clock (25MHz) to sensor"))
dw.append(("mclk_set", vrlg.VOSPI_MCLK + 1, 1, 0, "When set to 1, MCLK enable is set to the 'mclk' field value"))
dw.append(("spi_en", vrlg.VOSPI_EN, 2, 0, "SPI Reset/enable: 0 - NOP, 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable")) dw.append(("spi_en", vrlg.VOSPI_EN, 2, 0, "SPI Reset/enable: 0 - NOP, 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable"))
dw.append(("segm_zero", vrlg.VOSPI_SEGM0_OK, 1, 0, "OK to input segment 0 (invalid, valid are 1,2,3,4)")) dw.append(("segm_zero", vrlg.VOSPI_SEGM0_OK, 1, 0, "OK to input segment 0 (invalid, valid are 1,2,3,4)"))
dw.append(("segm_zero_set",vrlg.VOSPI_SEGM0_OK + 1, 1, 0, "Enable setting of segm_zero")) dw.append(("segm_zero_set",vrlg.VOSPI_SEGM0_OK + 1, 1, 0, "Enable setting of segm_zero"))
...@@ -2134,12 +2140,6 @@ class X393ExportC(object): ...@@ -2134,12 +2140,6 @@ class X393ExportC(object):
dw.append(("out_en_set", vrlg.VOSPI_OUT_EN + 1, 1, 0, "Set enable sensor data to memory")) dw.append(("out_en_set", vrlg.VOSPI_OUT_EN + 1, 1, 0, "Set enable sensor data to memory"))
dw.append(("out_single", vrlg.VOSPI_OUT_EN_SINGL, 1, 0, "Enable single sensor frame to memory")) dw.append(("out_single", vrlg.VOSPI_OUT_EN_SINGL, 1, 0, "Enable single sensor frame to memory"))
dw.append(("reset_crc", vrlg.VOSPI_RESET_CRC, 1, 0, "Reset CRC error status bit")) dw.append(("reset_crc", vrlg.VOSPI_RESET_CRC, 1, 0, "Reset CRC error status bit"))
dw.append(("rst", vrlg.VOSPI_MRST, 1, 0, "RESET signal level to the sensor (0 - low(active), 1 - high (inactive)"))
dw.append(("rst_set", vrlg.VOSPI_MRST + 1, 1, 0, "When set to 1, RESET is set to the 'rst' field value"))
dw.append(("pwdn", vrlg.VOSPI_PWDN, 1, 0, "POWER DOWN signal level to the sensor (0 - low(active), 1 - high (inactive)"))
dw.append(("pwdn_set", vrlg.VOSPI_PWDN + 1, 1, 0, "When set to 1, POWER DOWN is set to the 'pwdn' field value"))
dw.append(("mclk", vrlg.VOSPI_MCLK, 1, 0, "Enable master clock (25MHz) to sensor"))
dw.append(("mclk_set", vrlg.VOSPI_MCLK + 1, 1, 0, "When set to 1, MCLK enable is set to the 'mclk' field value"))
dw.append(("spi_clk", vrlg.VOSPI_SPI_CLK, 1, 0, "Enable continuous SPI clock (0 - only when SPI CS is active)")) dw.append(("spi_clk", vrlg.VOSPI_SPI_CLK, 1, 0, "Enable continuous SPI clock (0 - only when SPI CS is active)"))
dw.append(("spi_clk_set", vrlg.VOSPI_SPI_CLK + 1, 1, 0, "When set to 1, SPI CLK enable is set to the 'spi_clk' field value")) dw.append(("spi_clk_set", vrlg.VOSPI_SPI_CLK + 1, 1, 0, "When set to 1, SPI CLK enable is set to the 'spi_clk' field value"))
dw.append(("gpio0", vrlg.VOSPI_GPIO , 2, 0, "Output control for GPIO0: 0 - nop, 1 - set low, 2 - set high, 3 - input")) dw.append(("gpio0", vrlg.VOSPI_GPIO , 2, 0, "Output control for GPIO0: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
......
sensor/sens_lepton3.v
View file @ 37190574
...@@ -98,24 +98,26 @@ module sens_lepton3 #( ...@@ -98,24 +98,26 @@ module sens_lepton3 #(
parameter STATUS_ALIVE_WIDTH = 4, parameter STATUS_ALIVE_WIDTH = 4,
// mode bits // mode bits
parameter VOSPI_EN = 0, parameter VOSPI_MRST = 0,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 2,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 4,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 6,
parameter VOSPI_RESET_CRC = 7,
parameter VOSPI_MRST = 8,
parameter VOSPI_MRST_BITS = 2, parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 10, parameter VOSPI_PWDN = 2,
parameter VOSPI_PWDN_BITS = 2, parameter VOSPI_PWDN_BITS = 2,
parameter VOSPI_MCLK = 12, parameter VOSPI_MCLK = 4,
parameter VOSPI_MCLK_BITS = 2, parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_EN = 6,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 8,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12,
parameter VOSPI_RESET_CRC = 13,
parameter VOSPI_SPI_CLK = 14, parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2, parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16, parameter VOSPI_GPIO = 16,
parameter VOSPI_GPIO_BITS = 8, parameter VOSPI_GPIO_BITS = 8,
parameter VOSPI_FAKE_OUT = 24, // to keep hardware parameter VOSPI_FAKE_OUT = 24, // to keep hardware
parameter VOSPI_MOSI = 25, // pot used parameter VOSPI_MOSI = 25, // pot used
parameter VOSPI_PACKET_WORDS = 80, parameter VOSPI_PACKET_WORDS = 80,
...@@ -127,7 +129,8 @@ module sens_lepton3 #( ...@@ -127,7 +129,8 @@ module sens_lepton3 #(
parameter VOSPI_PACKET_LAST = 60, parameter VOSPI_PACKET_LAST = 60,
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2 // minimal clock cycles from HACT to HACT or to EOF parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4 // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
)( )(
// programming interface // programming interface
input mrst, // @posedge mclk, sync reset input mrst, // @posedge mclk, sync reset
...@@ -142,7 +145,7 @@ module sens_lepton3 #( ...@@ -142,7 +145,7 @@ module sens_lepton3 #(
output prsts, // @pclk - includes sensor reset and sensor PLL reset output prsts, // @pclk - includes sensor reset and sensor PLL reset
input pclk, // global clock input, SPI rate (10-20 MHz) - defines internal pixel rate input pclk, // global clock input, SPI rate (10-20 MHz) - defines internal pixel rate
input sns_mclk, // 25Mz for the sensor // input sns_mclk, // 25Mz for the sensor
// sensor pads excluding i2c // sensor pads excluding i2c
inout spi_miso, // input inout spi_miso, // input
...@@ -189,45 +192,6 @@ module sens_lepton3 #( ...@@ -189,45 +192,6 @@ module sens_lepton3 #(
segment_id [3:0], segment_id [3:0],
out_busy | in_busy, senspgm_int out_busy | in_busy, senspgm_int
}; };
/*
xfpgatdo_byte[7:0],
vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm,
clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
ps_rdy, ps_out,
xfpgatdo, senspgmin}; // go to bits 24, 25 when read
*/
// mode register (4 bits + 8 + 1)
/*
bits 0,1: 0: nop
1 - nreset=0 disable
2 - nreset, disable
3 - nreset, enable
2,3: 0,1 - nop
2 - disable invalid segments
3 - enabl;e invalid segments
4,5: 0,1 - nop
2 - disable out_en
3 - enabl;e out_en
6: 0 - nop,
1 - single frame out_en
7: reset CRC error
8,9: 0,1 - nop
2 - lwir_mrst <= 0 (active reset)
3 - lwir_mrst <= 1 (inactive)
10,11: 0,1 - nop
2 - lwir_pwdn <= 0 (active, disable sensor)
3 - lwir_pwdn <= 1 (inactive)
12,13: 0,1 - nop
2 - disable sns_mclk (25 MHz clock to sensor)
3 - enable sns_mclk
14,15: 0,1 - nop
2 - disable spi_clk (stop between CS acvtive)
3 - enabl;e spi_clk (continuously run evenwhen CS is acvtive)
16-23: GPIO[3:0] - use gpio_bit() and generate
24 - fake_out
25 - spi_mosi_int
*/
// then re-sync to pclk (and to sns_mclk) // then re-sync to pclk (and to sns_mclk)
reg spi_nrst_mclk; reg spi_nrst_mclk;
...@@ -269,7 +233,10 @@ module sens_lepton3 #( ...@@ -269,7 +233,10 @@ module sens_lepton3 #(
reg set_ctrl_r; reg set_ctrl_r;
reg set_status_r; reg set_status_r;
reg [ 1:0] sns_mclk_en_lwir_mclk; // reg [ 1:0] sns_mclk_en_lwir_mclk;
reg sns_mclk_r;
reg [3:0] sns_mclk_cntr;
wire spi_clken; // from lower module, clock will be combined wire spi_clken; // from lower module, clock will be combined
...@@ -345,10 +312,19 @@ module sens_lepton3 #( ...@@ -345,10 +312,19 @@ module sens_lepton3 #(
end end
always @(posedge sns_mclk) begin always @(posedge mclk) begin
sns_mclk_en_lwir_mclk[1:0] <= {sns_mclk_en_lwir_mclk[0],sns_mclk_en_mclk}; if (mrst) sns_mclk_r <= 0;
else if (sns_mclk_cntr == 0) sns_mclk_r <= sns_mclk_en_mclk && !sns_mclk_r;
if (mrst || (sns_mclk_cntr == 0)) sns_mclk_cntr <= VOSPI_MCLK_HALFDIV - 1;
else if (sns_mclk_en_mclk || sns_mclk_r) sns_mclk_cntr <= sns_mclk_cntr - 1;
end end
// always @(posedge sns_mclk) begin
// sns_mclk_en_lwir_mclk[1:0] <= {sns_mclk_en_lwir_mclk[0],sns_mclk_en_mclk};
// end
pulse_cross_clock pulse_cross_clock_out_en_single_i ( pulse_cross_clock pulse_cross_clock_out_en_single_i (
.rst (mrst), // input .rst (mrst), // input
.src_clk (mclk), // input .src_clk (mclk), // input
...@@ -386,6 +362,19 @@ module sens_lepton3 #( ...@@ -386,6 +362,19 @@ module sens_lepton3 #(
.dq (spi_clk) // output .dq (spi_clk) // output
); );
// sensor master clock (25MHz) // sensor master clock (25MHz)
iobuf #( // lwir_mclk
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) lwir_mclk_i (
.O (), // output
.IO (lwir_mclk), // inout I/O pad
.I (sns_mclk_r), // input
.T (1'b0) // input - always on
);
/*
oddr_ss #( oddr_ss #(
.IOSTANDARD (PXD_IOSTANDARD), .IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW), .SLEW (PXD_SLEW),
...@@ -401,7 +390,7 @@ module sens_lepton3 #( ...@@ -401,7 +390,7 @@ module sens_lepton3 #(
.tin (1'b0), // input .tin (1'b0), // input
.dq (lwir_mclk) // output .dq (lwir_mclk) // output
); );
*/
iobuf #( // spi_miso iobuf #( // spi_miso
.DRIVE (PXD_DRIVE), .DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR), .IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
......
sensor/sensor_channel.v
View file @ 37190574
...@@ -229,20 +229,20 @@ module sensor_channel#( ...@@ -229,20 +229,20 @@ module sensor_channel#(
`ifdef HISPI `ifdef HISPI
`elsif LWIR `elsif LWIR
parameter VOSPI_EN = 0, parameter VOSPI_MRST = 0,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 2,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 4,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 6,
parameter VOSPI_RESET_CRC = 7,
parameter VOSPI_MRST = 8,
parameter VOSPI_MRST_BITS = 2, parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 10, parameter VOSPI_PWDN = 2,
parameter VOSPI_PWDN_BITS = 2, parameter VOSPI_PWDN_BITS = 2,
parameter VOSPI_MCLK = 12, parameter VOSPI_MCLK = 4,
parameter VOSPI_MCLK_BITS = 2, parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_EN = 6,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 8,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12,
parameter VOSPI_RESET_CRC = 13,
parameter VOSPI_SPI_CLK = 14, parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2, parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16, parameter VOSPI_GPIO = 16,
...@@ -259,6 +259,8 @@ module sensor_channel#( ...@@ -259,6 +259,8 @@ module sensor_channel#(
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
`else `else
//sensor_fifo parameters //sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12, parameter SENSOR_DATA_WIDTH = 12,
...@@ -1022,20 +1024,20 @@ module sensor_channel#( ...@@ -1022,20 +1024,20 @@ module sensor_channel#(
.SENS_SS_MODE (SENS_SS_MODE), .SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD), .SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.STATUS_ALIVE_WIDTH (STATUS_ALIVE_WIDTH), .STATUS_ALIVE_WIDTH (STATUS_ALIVE_WIDTH),
.VOSPI_EN (VOSPI_EN), // 0, .VOSPI_MRST (VOSPI_MRST), // 0,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 2,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 4,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 6,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 7,
.VOSPI_MRST (VOSPI_MRST), // 8,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2, .VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 10, .VOSPI_PWDN (VOSPI_PWDN), // 2,
.VOSPI_PWDN_BITS (VOSPI_PWDN_BITS), // 2, .VOSPI_PWDN_BITS (VOSPI_PWDN_BITS), // 2,
.VOSPI_MCLK (VOSPI_MCLK), // 12, .VOSPI_MCLK (VOSPI_MCLK), // 4,
.VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2, .VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2,
.VOSPI_EN (VOSPI_EN), // 6,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 8,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 10,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 12,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 13,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14, .VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2, .VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16, .VOSPI_GPIO (VOSPI_GPIO), // 16,
...@@ -1051,7 +1053,8 @@ module sensor_channel#( ...@@ -1051,7 +1053,8 @@ module sensor_channel#(
.VOSPI_PACKET_LAST (VOSPI_PACKET_LAST), // 60, .VOSPI_PACKET_LAST (VOSPI_PACKET_LAST), // 60,
.VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20, .VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20,
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 2, .VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 2,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF) // 2, .VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV) // 4
) sens_lepton3_i ( ) sens_lepton3_i (
.mrst (mrst), // input .mrst (mrst), // input
.mclk (mclk), // input .mclk (mclk), // input
...@@ -1063,8 +1066,7 @@ module sensor_channel#( ...@@ -1063,8 +1066,7 @@ module sensor_channel#(
.prst (prst), // input .prst (prst), // input
.prsts (prsts), // output .prsts (prsts), // output
.pclk (pclk), // input .pclk (pclk), // input
.sns_mclk(), // input // .sns_mclk(), // input
.spi_miso (sns_dp40[0]), // inout .spi_miso (sns_dp40[0]), // inout
.spi_mosi (sns_dn40[0]), // inout .spi_mosi (sns_dn40[0]), // inout
.spi_cs (sns_dp40[1]), // inout .spi_cs (sns_dp40[1]), // inout
......
sensor/sensors393.v
View file @ 37190574
...@@ -225,20 +225,20 @@ module sensors393 #( ...@@ -225,20 +225,20 @@ module sensors393 #(
`ifdef HISPI `ifdef HISPI
`elsif LWIR `elsif LWIR
parameter VOSPI_EN = 0, parameter VOSPI_MRST = 0,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 2,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 4,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 6,
parameter VOSPI_RESET_CRC = 7,
parameter VOSPI_MRST = 8,
parameter VOSPI_MRST_BITS = 2, parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 10, parameter VOSPI_PWDN = 2,
parameter VOSPI_PWDN_BITS = 2, parameter VOSPI_PWDN_BITS = 2,
parameter VOSPI_MCLK = 12, parameter VOSPI_MCLK = 4,
parameter VOSPI_MCLK_BITS = 2, parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_EN = 6,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 8,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12,
parameter VOSPI_RESET_CRC = 13,
parameter VOSPI_SPI_CLK = 14, parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2, parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16, parameter VOSPI_GPIO = 16,
...@@ -255,6 +255,8 @@ module sensors393 #( ...@@ -255,6 +255,8 @@ module sensors393 #(
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
`else `else
//sensor_fifo parameters //sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12, parameter SENSOR_DATA_WIDTH = 12,
...@@ -678,20 +680,20 @@ module sensors393 #( ...@@ -678,20 +680,20 @@ module sensors393 #(
.NUM_FRAME_BITS (NUM_FRAME_BITS), .NUM_FRAME_BITS (NUM_FRAME_BITS),
`ifdef HISPI `ifdef HISPI
`elsif LWIR `elsif LWIR
.VOSPI_EN (VOSPI_EN), // 0, .VOSPI_MRST (VOSPI_MRST), // 0,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 2,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 4,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 6,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 7,
.VOSPI_MRST (VOSPI_MRST), // 8,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2, .VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 10, .VOSPI_PWDN (VOSPI_PWDN), // 2,
.VOSPI_PWDN_BITS (VOSPI_PWDN_BITS), // 2, .VOSPI_PWDN_BITS (VOSPI_PWDN_BITS), // 2,
.VOSPI_MCLK (VOSPI_MCLK), // 12, .VOSPI_MCLK (VOSPI_MCLK), // 4,
.VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2, .VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2,
.VOSPI_EN (VOSPI_EN), // 6,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 8,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 10,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 12,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 13,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14, .VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2, .VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16, .VOSPI_GPIO (VOSPI_GPIO), // 16,
...@@ -708,6 +710,7 @@ module sensors393 #( ...@@ -708,6 +710,7 @@ module sensors393 #(
.VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20, .VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20,
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 2, .VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 2,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2, .VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV), // 4
`else `else
.SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH), .SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH),
......
sensor/vospi_segment_61.v
View file @ 37190574
...@@ -49,6 +49,7 @@ module vospi_segment_61#( ...@@ -49,6 +49,7 @@ module vospi_segment_61#(
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2 // minimal clock cycles from HACT to HACT or to EOF parameter VOSPI_HACT_TO_HACT_EOF = 2 // minimal clock cycles from HACT to HACT or to EOF
// parameter VOSPI_HACT_TO_EOF = 2 // clock cycles from HACT to EOF // parameter VOSPI_HACT_TO_EOF = 2 // clock cycles from HACT to EOF
)( )(
input rst, input rst,
......
x393.v
View file @ 37190574
...@@ -1836,20 +1836,20 @@ assign axi_grst = axi_rst_pre; ...@@ -1836,20 +1836,20 @@ assign axi_grst = axi_rst_pre;
.SENSI2C_SLEW (SENSI2C_SLEW), .SENSI2C_SLEW (SENSI2C_SLEW),
`ifdef HISPI `ifdef HISPI
`elsif LWIR `elsif LWIR
.VOSPI_EN (VOSPI_EN), // 0, .VOSPI_MRST (VOSPI_MRST), // 0,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 2,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 4,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 6,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 7,
.VOSPI_MRST (VOSPI_MRST), // 8,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2, .VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 10, .VOSPI_PWDN (VOSPI_PWDN), // 2,
.VOSPI_PWDN_BITS (VOSPI_PWDN_BITS), // 2, .VOSPI_PWDN_BITS (VOSPI_PWDN_BITS), // 2,
.VOSPI_MCLK (VOSPI_MCLK), // 12, .VOSPI_MCLK (VOSPI_MCLK), // 4,
.VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2, .VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2,
.VOSPI_EN (VOSPI_EN), // 6,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 8,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 10,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 12,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 13,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14, .VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2, .VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16, .VOSPI_GPIO (VOSPI_GPIO), // 16,
...@@ -1866,6 +1866,8 @@ assign axi_grst = axi_rst_pre; ...@@ -1866,6 +1866,8 @@ assign axi_grst = axi_rst_pre;
.VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20, .VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20,
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 2, .VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 2,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2, .VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV), // 4
`else `else
......
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