Commit 37190574 authored by Andrey Filippov's avatar Andrey Filippov

more code for LWIR sensor

parent 691579c0
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -538,20 +538,20 @@
//`ifdef HISPI
//`elsif LWIR
parameter VOSPI_EN = 0,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 2,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 4,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 6,
parameter VOSPI_RESET_CRC = 7,
parameter VOSPI_MRST = 8,
parameter VOSPI_MRST = 0,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 10,
parameter VOSPI_PWDN = 2,
parameter VOSPI_PWDN_BITS = 2,
parameter VOSPI_MCLK = 12,
parameter VOSPI_MCLK = 4,
parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_EN = 6,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 8,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12,
parameter VOSPI_RESET_CRC = 13,
parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16,
......@@ -568,7 +568,7 @@
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
//`else
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
......@@ -993,11 +993,20 @@
parameter CLKOUT_DIV_PCLK = 4, // 220 MHz
parameter CLKOUT_DIV_PCLK2X = 2, // 440 MHz
`else
// Python program bug - does not support elseif??
`ifdef LWIR
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
parameter CLKOUT_DIV_PCLK = 48, // 20 MHz
parameter CLKOUT_DIV_PCLK2X = 24, // 40 MHz
`else
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
parameter CLKOUT_DIV_PCLK = 10, // 96MHz
parameter CLKOUT_DIV_PCLK2X = 5, // 192 MHz
`endif
`endif
parameter PHASE_CLK2X_PCLK = 0.000,
parameter BUF_CLK1X_PCLK = "BUFG",
......
......@@ -237,6 +237,7 @@ SENSI2C_ABS_RADDR__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__RAW = str
CLKFBOUT_MULT = int
RTC_STATUS_REG_ADDR__RAW = str
VOSPI_MCLK_HALFDIV__RAW = str
SENS_LENS_C_MASK__RAW = str
SIMULATE_CMPRS_CMODE0__RAW = str
NUM_CYCLES_11__TYPE = str
......@@ -417,6 +418,7 @@ SENS_LENS_BY_MASK__RAW = str
SENS_CTRL_GP0__TYPE = str
DFLT_REFRESH_ADDR = int
DLY_DQS_ODELAY__TYPE = str
DFLT_REFRESH_PERIOD__RAW = str
TEST01_SUSPEND__RAW = str
SENS_GAMMA_HEIGHT01__TYPE = str
LWIR_TELEMETRY_AGC_LOW__RAW = str
......@@ -612,6 +614,7 @@ NUM_CYCLES_12 = int
MCNTRL_SCANLINE_FRAME_PAGE_RESET__TYPE = str
MCNTRL_TILED_CHN2_ADDR__TYPE = str
NUM_CYCLES_11 = int
HIST_SAXI_ADDR_REL__TYPE = str
SENS_GAMMA_ADDR_MASK = int
NUM_CYCLES_10 = int
MEMCLK_IBUF_LOW_PWR__TYPE = str
......@@ -758,7 +761,7 @@ SENS_GAMMA_HEIGHT2 = int
DLY_LD_MASK__TYPE = str
STATUS_MSB_RSHFT__TYPE = str
MCONTR_BUF0_RD_ADDR = int
HIST_SAXI_ADDR_REL__TYPE = str
VOSPI_RESET_CRC = int
CMPRS_CBIT_CMODE_JPEG20 = int
CMPRS_TIMEOUT_BITS = int
CAMSYNC_PRE_MAGIC = int
......@@ -1597,6 +1600,7 @@ SENS_CTRL_IGNORE_EMBED = int
RTC_MASK__TYPE = str
MCNTRL_TILED_PENDING_CNTR_BITS = int
NUM_CYCLES_00__TYPE = str
VOSPI_MCLK_HALFDIV = int
CMPRS_MASK__RAW = str
MEMBRIDGE_CTRL_IRQ__TYPE = str
MCNTRL_TEST01_MASK__RAW = str
......@@ -1676,6 +1680,7 @@ LOGGER_PAGE_MSG = int
SENS_HIGH_PERFORMANCE_MODE = str
WINDOW_X0 = int
INITIALIZE_OFFSET__TYPE = str
VOSPI_RESET_CRC__TYPE = str
LOGGER_CONF_IMU_BITS__TYPE = str
LWIR_TELEMETRY_AGC_ROI_RIGHT__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI__TYPE = str
......@@ -2202,7 +2207,7 @@ MULT_SAXI_CNTRL_MODE__RAW = str
SENS_GAMMA_ADDR_DATA__TYPE = str
VOSPI_OUT_EN__TYPE = str
CAMSYNC_DELAY__TYPE = str
DFLT_REFRESH_PERIOD__RAW = str
VOSPI_RESET_CRC__RAW = str
SENS_REF_JITTER1__TYPE = str
SENS_LENS_RADDR__RAW = str
MCONTR_PHY_0BIT_DCI_RST__TYPE = str
......@@ -2464,6 +2469,7 @@ WRITE_BLOCK_OFFSET__RAW = str
SENS_GAMMA_MODE_EN_SET = int
MCONTR_LINTILE_SINGLE__RAW = str
MCNTRL_TILED_FRAME_PAGE_RESET__RAW = str
VOSPI_MCLK_HALFDIV__TYPE = str
SENS_GAMMA_BUFFER__TYPE = str
SLEW_DQ__TYPE = str
MCONTR_BUF4_RD_ADDR = int
......
......@@ -2127,6 +2127,12 @@ class X393ExportC(object):
def _enc_sensio_ctrl_vospi(self):
dw=[]
dw.append(("mrst", vrlg.VOSPI_MRST, 1, 0, "RESET signal level to the sensor (0 - low(active), 1 - high (inactive)"))
dw.append(("mrst_set", vrlg.VOSPI_MRST + 1, 1, 0, "When set to 1, RESET is set to the 'rst' field value"))
dw.append(("pwdn", vrlg.VOSPI_PWDN, 1, 0, "POWER DOWN signal level to the sensor (0 - low(active), 1 - high (inactive)"))
dw.append(("pwdn_set", vrlg.VOSPI_PWDN + 1, 1, 0, "When set to 1, POWER DOWN is set to the 'pwdn' field value"))
dw.append(("mclk", vrlg.VOSPI_MCLK, 1, 0, "Enable master clock (25MHz) to sensor"))
dw.append(("mclk_set", vrlg.VOSPI_MCLK + 1, 1, 0, "When set to 1, MCLK enable is set to the 'mclk' field value"))
dw.append(("spi_en", vrlg.VOSPI_EN, 2, 0, "SPI Reset/enable: 0 - NOP, 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable"))
dw.append(("segm_zero", vrlg.VOSPI_SEGM0_OK, 1, 0, "OK to input segment 0 (invalid, valid are 1,2,3,4)"))
dw.append(("segm_zero_set",vrlg.VOSPI_SEGM0_OK + 1, 1, 0, "Enable setting of segm_zero"))
......@@ -2134,12 +2140,6 @@ class X393ExportC(object):
dw.append(("out_en_set", vrlg.VOSPI_OUT_EN + 1, 1, 0, "Set enable sensor data to memory"))
dw.append(("out_single", vrlg.VOSPI_OUT_EN_SINGL, 1, 0, "Enable single sensor frame to memory"))
dw.append(("reset_crc", vrlg.VOSPI_RESET_CRC, 1, 0, "Reset CRC error status bit"))
dw.append(("rst", vrlg.VOSPI_MRST, 1, 0, "RESET signal level to the sensor (0 - low(active), 1 - high (inactive)"))
dw.append(("rst_set", vrlg.VOSPI_MRST + 1, 1, 0, "When set to 1, RESET is set to the 'rst' field value"))
dw.append(("pwdn", vrlg.VOSPI_PWDN, 1, 0, "POWER DOWN signal level to the sensor (0 - low(active), 1 - high (inactive)"))
dw.append(("pwdn_set", vrlg.VOSPI_PWDN + 1, 1, 0, "When set to 1, POWER DOWN is set to the 'pwdn' field value"))
dw.append(("mclk", vrlg.VOSPI_MCLK, 1, 0, "Enable master clock (25MHz) to sensor"))
dw.append(("mclk_set", vrlg.VOSPI_MCLK + 1, 1, 0, "When set to 1, MCLK enable is set to the 'mclk' field value"))
dw.append(("spi_clk", vrlg.VOSPI_SPI_CLK, 1, 0, "Enable continuous SPI clock (0 - only when SPI CS is active)"))
dw.append(("spi_clk_set", vrlg.VOSPI_SPI_CLK + 1, 1, 0, "When set to 1, SPI CLK enable is set to the 'spi_clk' field value"))
dw.append(("gpio0", vrlg.VOSPI_GPIO , 2, 0, "Output control for GPIO0: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
......
......@@ -98,24 +98,26 @@ module sens_lepton3 #(
parameter STATUS_ALIVE_WIDTH = 4,
// mode bits
parameter VOSPI_EN = 0,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 2,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 4,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 6,
parameter VOSPI_RESET_CRC = 7,
parameter VOSPI_MRST = 8,
parameter VOSPI_MRST = 0,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 10,
parameter VOSPI_PWDN = 2,
parameter VOSPI_PWDN_BITS = 2,
parameter VOSPI_MCLK = 12,
parameter VOSPI_MCLK = 4,
parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_EN = 6,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 8,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12,
parameter VOSPI_RESET_CRC = 13,
parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16,
parameter VOSPI_GPIO_BITS = 8,
parameter VOSPI_FAKE_OUT = 24, // to keep hardware
parameter VOSPI_MOSI = 25, // pot used
parameter VOSPI_PACKET_WORDS = 80,
......@@ -127,7 +129,8 @@ module sens_lepton3 #(
parameter VOSPI_PACKET_LAST = 60,
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2 // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4 // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
)(
// programming interface
input mrst, // @posedge mclk, sync reset
......@@ -142,7 +145,7 @@ module sens_lepton3 #(
output prsts, // @pclk - includes sensor reset and sensor PLL reset
input pclk, // global clock input, SPI rate (10-20 MHz) - defines internal pixel rate
input sns_mclk, // 25Mz for the sensor
// input sns_mclk, // 25Mz for the sensor
// sensor pads excluding i2c
inout spi_miso, // input
......@@ -189,45 +192,6 @@ module sens_lepton3 #(
segment_id [3:0],
out_busy | in_busy, senspgm_int
};
/*
xfpgatdo_byte[7:0],
vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm,
clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
ps_rdy, ps_out,
xfpgatdo, senspgmin}; // go to bits 24, 25 when read
*/
// mode register (4 bits + 8 + 1)
/*
bits 0,1: 0: nop
1 - nreset=0 disable
2 - nreset, disable
3 - nreset, enable
2,3: 0,1 - nop
2 - disable invalid segments
3 - enabl;e invalid segments
4,5: 0,1 - nop
2 - disable out_en
3 - enabl;e out_en
6: 0 - nop,
1 - single frame out_en
7: reset CRC error
8,9: 0,1 - nop
2 - lwir_mrst <= 0 (active reset)
3 - lwir_mrst <= 1 (inactive)
10,11: 0,1 - nop
2 - lwir_pwdn <= 0 (active, disable sensor)
3 - lwir_pwdn <= 1 (inactive)
12,13: 0,1 - nop
2 - disable sns_mclk (25 MHz clock to sensor)
3 - enable sns_mclk
14,15: 0,1 - nop
2 - disable spi_clk (stop between CS acvtive)
3 - enabl;e spi_clk (continuously run evenwhen CS is acvtive)
16-23: GPIO[3:0] - use gpio_bit() and generate
24 - fake_out
25 - spi_mosi_int
*/
// then re-sync to pclk (and to sns_mclk)
reg spi_nrst_mclk;
......@@ -269,7 +233,10 @@ module sens_lepton3 #(
reg set_ctrl_r;
reg set_status_r;
reg [ 1:0] sns_mclk_en_lwir_mclk;
// reg [ 1:0] sns_mclk_en_lwir_mclk;
reg sns_mclk_r;
reg [3:0] sns_mclk_cntr;
wire spi_clken; // from lower module, clock will be combined
......@@ -344,10 +311,19 @@ module sens_lepton3 #(
else if (crc_err_w) crc_err_r <= 1;
end
always @(posedge sns_mclk) begin
sns_mclk_en_lwir_mclk[1:0] <= {sns_mclk_en_lwir_mclk[0],sns_mclk_en_mclk};
always @(posedge mclk) begin
if (mrst) sns_mclk_r <= 0;
else if (sns_mclk_cntr == 0) sns_mclk_r <= sns_mclk_en_mclk && !sns_mclk_r;
if (mrst || (sns_mclk_cntr == 0)) sns_mclk_cntr <= VOSPI_MCLK_HALFDIV - 1;
else if (sns_mclk_en_mclk || sns_mclk_r) sns_mclk_cntr <= sns_mclk_cntr - 1;
end
// always @(posedge sns_mclk) begin
// sns_mclk_en_lwir_mclk[1:0] <= {sns_mclk_en_lwir_mclk[0],sns_mclk_en_mclk};
// end
pulse_cross_clock pulse_cross_clock_out_en_single_i (
.rst (mrst), // input
......@@ -386,6 +362,19 @@ module sens_lepton3 #(
.dq (spi_clk) // output
);
// sensor master clock (25MHz)
iobuf #( // lwir_mclk
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) lwir_mclk_i (
.O (), // output
.IO (lwir_mclk), // inout I/O pad
.I (sns_mclk_r), // input
.T (1'b0) // input - always on
);
/*
oddr_ss #(
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW),
......@@ -401,7 +390,7 @@ module sens_lepton3 #(
.tin (1'b0), // input
.dq (lwir_mclk) // output
);
*/
iobuf #( // spi_miso
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
......
......@@ -229,20 +229,20 @@ module sensor_channel#(
`ifdef HISPI
`elsif LWIR
parameter VOSPI_EN = 0,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 2,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 4,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 6,
parameter VOSPI_RESET_CRC = 7,
parameter VOSPI_MRST = 8,
parameter VOSPI_MRST = 0,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 10,
parameter VOSPI_PWDN = 2,
parameter VOSPI_PWDN_BITS = 2,
parameter VOSPI_MCLK = 12,
parameter VOSPI_MCLK = 4,
parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_EN = 6,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 8,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12,
parameter VOSPI_RESET_CRC = 13,
parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16,
......@@ -259,6 +259,8 @@ module sensor_channel#(
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
`else
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
......@@ -1022,20 +1024,20 @@ module sensor_channel#(
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.STATUS_ALIVE_WIDTH (STATUS_ALIVE_WIDTH),
.VOSPI_EN (VOSPI_EN), // 0,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 2,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 4,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 6,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 7,
.VOSPI_MRST (VOSPI_MRST), // 8,
.VOSPI_MRST (VOSPI_MRST), // 0,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 10,
.VOSPI_PWDN (VOSPI_PWDN), // 2,
.VOSPI_PWDN_BITS (VOSPI_PWDN_BITS), // 2,
.VOSPI_MCLK (VOSPI_MCLK), // 12,
.VOSPI_MCLK (VOSPI_MCLK), // 4,
.VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2,
.VOSPI_EN (VOSPI_EN), // 6,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 8,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 10,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 12,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 13,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16,
......@@ -1051,7 +1053,8 @@ module sensor_channel#(
.VOSPI_PACKET_LAST (VOSPI_PACKET_LAST), // 60,
.VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20,
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 2,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF) // 2,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV) // 4
) sens_lepton3_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1063,8 +1066,7 @@ module sensor_channel#(
.prst (prst), // input
.prsts (prsts), // output
.pclk (pclk), // input
.sns_mclk(), // input
// .sns_mclk(), // input
.spi_miso (sns_dp40[0]), // inout
.spi_mosi (sns_dn40[0]), // inout
.spi_cs (sns_dp40[1]), // inout
......
......@@ -225,20 +225,20 @@ module sensors393 #(
`ifdef HISPI
`elsif LWIR
parameter VOSPI_EN = 0,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 2,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 4,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 6,
parameter VOSPI_RESET_CRC = 7,
parameter VOSPI_MRST = 8,
parameter VOSPI_MRST = 0,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 10,
parameter VOSPI_PWDN = 2,
parameter VOSPI_PWDN_BITS = 2,
parameter VOSPI_MCLK = 12,
parameter VOSPI_MCLK = 4,
parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_EN = 6,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 8,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 10,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 12,
parameter VOSPI_RESET_CRC = 13,
parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16,
......@@ -255,6 +255,8 @@ module sensors393 #(
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
parameter VOSPI_MCLK_HALFDIV = 4, // divide mclk (200Hhz) to get 50 MHz, then divide by 2 and use for sensor 25MHz clock
`else
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
......@@ -678,20 +680,20 @@ module sensors393 #(
.NUM_FRAME_BITS (NUM_FRAME_BITS),
`ifdef HISPI
`elsif LWIR
.VOSPI_EN (VOSPI_EN), // 0,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 2,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 4,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 6,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 7,
.VOSPI_MRST (VOSPI_MRST), // 8,
.VOSPI_MRST (VOSPI_MRST), // 0,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 10,
.VOSPI_PWDN (VOSPI_PWDN), // 2,
.VOSPI_PWDN_BITS (VOSPI_PWDN_BITS), // 2,
.VOSPI_MCLK (VOSPI_MCLK), // 12,
.VOSPI_MCLK (VOSPI_MCLK), // 4,
.VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2,
.VOSPI_EN (VOSPI_EN), // 6,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 8,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 10,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 12,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 13,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16,
......@@ -708,6 +710,7 @@ module sensors393 #(
.VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20,
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 2,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV), // 4
`else
.SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH),
......
......@@ -49,6 +49,7 @@ module vospi_segment_61#(
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2 // minimal clock cycles from HACT to HACT or to EOF
// parameter VOSPI_HACT_TO_EOF = 2 // clock cycles from HACT to EOF
)(
input rst,
......
......@@ -46,6 +46,9 @@ module simul_lwir160x120_vospi # (
parameter TELEMETRY = 1, // 0 - disabled, 1 - as header, 2 - as footer
parameter FRAME_PERIOD = 946969, // 26.4 fps @25 MHz
parameter SEGMENT_PERIOD = 10000, // 236742, // 26.4 fps @25 MHz
parameter SEGMENTS_SEQ = 8, // 12 With ITAR
parameter FRAME_DELAY = 100, // mclk period to start first frame 1
parameter MS_PERIOD = 25 // ahould actually be 25000
)(
......@@ -90,15 +93,21 @@ module simul_lwir160x120_vospi # (
localparam SEGMENT_PACKETS = 60; // w/o telemetry
localparam SEGMENT_PACKETS_TELEMETRY = SEGMENT_PACKETS + ((TELEMETRY > 0)? 1 : 0);
localparam FRAME_SEGMENTS = 4;
localparam FRAME_PACKETS = SEGMENT_PACKETS * FRAME_SEGMENTS;
localparam FRAME_PACKETS = SEGMENT_PACKETS * FRAME_SEGMENTS;
localparam FRAME_PACKETS_FULL = FRAME_PACKETS + ((TELEMETRY==0) ? 0 : 4);
localparam FRAMES = 2; // 2 frames in a ping-pong buffer
localparam FRAME_WORDS = FRAME_SEGMENTS * (SEGMENT_PACKETS + ((TELEMETRY>0)?1 : 0)) * PACKET_WORDS;
localparam FRAMES = 2; // 2 frames in a ping-pong buffer
localparam FRAME_WORDS = FRAME_SEGMENTS * (SEGMENT_PACKETS + ((TELEMETRY>0)?1 : 0)) * PACKET_WORDS;
localparam SEGMENT_PACKETS_FULL = SEGMENT_PACKETS + ((TELEMETRY>0)?1 : 0);
localparam SEGMENT_WORDS = SEGMENT_PACKETS_FULL * PACKET_WORDS;
localparam SEGMENTS_MIN = 4; // minimal segments ready to be able to read
localparam SEGMENTS_MAX = 6; // maximum segments ready before sync is lost
wire rst = !mrst;
reg [OUT_BITS-1:0] sensor_data[0 : WINDOW_WIDTH * WINDOW_HEIGHT - 1]; // SuppressThisWarning VEditor - Will be assigned by $readmem
reg [OUT_BITS-1:0] packed_data[0: FRAMES * FRAME_WORDS -1];
reg [OUT_BITS-1:0] packet_bad [0: PACKET_WORDS-1];
wire [160*16-1:0] telemetry_a;
wire [160*16-1:0] telemetry_b;
......@@ -107,20 +116,29 @@ module simul_lwir160x120_vospi # (
//'0xe7319'
reg [19:0] frame_dly_cntr; // delay till next frame start
reg [19:0] segment_dly_cntr; // delay till next frame segment
reg frame_start;
reg segment_start;
reg [ 3:0] segments_cntr;
wire [ 3:0] segment_id;
reg copy_page;
reg copy_run;
wire copy_done;
reg segment_run;
wire segment_done;
// reg [2:0] copy_segment; // 4 - copy average and telemetry
reg [7:0] copy_packet; // 240 image packets, then telemetry
reg [7:0] copy_packet; // number of a packet in a frame 240 image packets, then telemetry
reg [6:0] segment_packet; // 60/61 packets
reg [6:0] copy_word; // word number to copy in a packet (0..82), last one copies CRC to word 1
reg copy_crc;
wire [7:0] copy_packet_full;
wire [7:0] copy_telemetry_packet; // only 2 LSB
wire [7:0] copy_packet_segment;
// wire [7:0] copy_packet_segment;
wire [11:0] copy_packet_indx; // high bits are always 0
wire [7:0] copy_packet_ttt;
wire [3:0] copy_packet_ttt;
reg [15:0] copy_pxd;
reg [30:0] frame_sum;
......@@ -137,7 +155,7 @@ module simul_lwir160x120_vospi # (
wire [15:0] copy_din;
wire [ 6:0] copy_wa; // address in a packet where to write data
wire [15:0] copy_wa_full;
wire [15:0] copy_wa_full;
wire [15:0] crc_in;
wire [15:0] crc_out;
reg en_avg; // write frame average value to telemetry
......@@ -145,6 +163,51 @@ module simul_lwir160x120_vospi # (
reg [31:0] time_ms;
reg [31:0] ms_cntr;
//----------------
wire start_segm_rd; // starting readout page, spi_clk domain
wire start_segm_rd_mclk; // starting readout page, resync to mclk
reg readout_page; // readout page number
reg [ 1:0] readout_segment; // actually just 2 (2 bits, but will use FRAME_SEGMENTS==4
reg [ 5:0] readout_packet; // number of packet read out in a segment
reg [ 6:0] readout_word_indx; // number of word in a readout packet
reg [ 3:0] readout_bit; // 0 - msb, 15 - lsb
reg [15:0] readout_sr_good;
reg [15:0] readout_sr_bad;
reg [ 3:0] segments_ready;
reg segment_av; // segments avalable for readout
reg sync_lost;
reg packet_sent;
// reg packet_skipped; // sent invalid packet
reg packet_re_last;
wire readout_last_segment; // reading last segment in a frame
wire readout_last_packet; // reading last packet in a segment
wire readout_last_word; // reading last word in a packet
wire readout_pre_last_bit; // reading out pre-last bit
wire readout_pre_first_bit; // reading out pre-first bit in a word
reg readout_last_bit;
reg readout_first_bit = 1;
wire [15:0] readout_address; // buffer readout address
wire readout_good_w ; // should be valid at first negative transition of the spi_clk
reg readout_good; // reading out/sending valid packet
assign readout_last_segment = readout_segment == (FRAME_SEGMENTS - 1);
assign readout_last_packet = readout_packet == (SEGMENT_PACKETS_TELEMETRY -1);
assign readout_last_word = readout_word_indx == (PACKET_WORDS -1);
assign readout_pre_last_bit = readout_bit[3:0] == 14;
assign readout_pre_first_bit = readout_bit[3:0] == 15;
assign readout_address = readout_word_indx +
(PACKET_WORDS * readout_packet) +
(SEGMENT_WORDS * readout_segment) +
(FRAME_WORDS * readout_page);
assign readout_good_w = segment_av;
assign spi_miso = readout_good ? readout_sr_good[15] : readout_sr_bad[15];
assign start_segm_rd = (readout_word_indx == 0) && readout_last_bit && !spi_cs;
// wire [ 2:0] copy_segment;
//946,969 '0xe7319'
......@@ -161,6 +224,8 @@ module simul_lwir160x120_vospi # (
assign copy_done = copy_run && copy_crc && (copy_packet== (FRAME_PACKETS_FULL -1));
assign segment_done = copy_run && copy_crc && (segment_packet== (SEGMENT_PACKETS_FULL -1));
assign segment_id = (segments_cntr < 4) ? (segments_cntr +1) : 4'b0;
assign copy_packet_full = (copy_packet < FRAME_PACKETS)?(copy_packet + ((TELEMETRY == 1) ? 4 : 0)):(copy_packet - ((TELEMETRY == 1)?FRAME_PACKETS: 0)) ;
......@@ -168,9 +233,11 @@ module simul_lwir160x120_vospi # (
assign copy_pix_or_tel = copy_run && (copy_word < PACKET_PIXELS); // && (copy_packet < FRAME_PACKETS);
assign copy_pix_only = copy_pix_or_tel && (copy_packet < FRAME_PACKETS);
assign copy_tel_only = copy_pix_or_tel && (copy_packet >= FRAME_PACKETS);
assign copy_packet_segment = copy_packet_full / SEGMENT_PACKETS_TELEMETRY;
// assign copy_packet_segment = copy_packet_full / SEGMENT_PACKETS_TELEMETRY; ///
assign copy_packet_indx = copy_packet_full % SEGMENT_PACKETS_TELEMETRY;
assign copy_packet_ttt = (copy_packet_indx == 20) ? (copy_packet_segment + 1): 8'b0;
assign copy_packet_ttt = (copy_packet_indx == 20) ? segment_id: 4'b0;
assign crc_in = (copy_word == 0) ? {4'b0,copy_packet_indx[11:0]}:(
(copy_word == 1) ?16'b0:copy_d[15:0]);
......@@ -190,42 +257,71 @@ module simul_lwir160x120_vospi # (
`define ROOTPATH "."
`endif
`endif
integer i;
initial begin
// $readmemh({`ROOTPATH,"/input_data/sensor_16.dat"},sensor_data);
$readmemh(DATA_FILE,sensor_data,0);
$readmemh(DATA_FILE,sensor_data,0);
// reg [OUT_BITS-1:0] packet_bad [0: PACKET_WORDS-1];
packet_bad[0] <= 'h0f00;
packet_bad[1] <= 'h0000; // calculate and put crc?
for (i = 2; i < PACKET_WORDS; i = i+1) begin
packet_bad[i] <= 0;
end
end
always @ (posedge mclk) begin
if (rst || (ms_cntr == 0)) ms_cntr <= MS_PERIOD -1;
else ms_cntr <= ms_cntr - 1;
else ms_cntr <= ms_cntr - 1;
if (rst) time_ms <= 0;
else if ((ms_cntr == 0)) time_ms <= time_ms + 1;
if (rst) time_ms <= 0;
else if ((ms_cntr == 0)) time_ms <= time_ms + 1;
//restarting frames
if (rst) frame_dly_cntr <= FRAME_DELAY;
else if (frame_start) frame_dly_cntr <= FRAME_PERIOD;
else frame_dly_cntr <= frame_dly_cntr - 1;
if (rst) segment_dly_cntr <= FRAME_DELAY;
else if (segment_start) segment_dly_cntr <= SEGMENT_PERIOD;
else segment_dly_cntr <= segment_dly_cntr - 1;
segment_start <= !rst && (segment_dly_cntr == 0);
if (rst || segment_done) segment_run <= 0;
else if (segment_start) segment_run <= 1;
if (rst) frame_dly_cntr <= FRAME_DELAY;
else if (frame_start) frame_dly_cntr <= FRAME_PERIOD;
else frame_dly_cntr <= frame_dly_cntr - 1;
frame_start <= !rst && (frame_dly_cntr == 0);
if (rst) frame_num <= 0;
else if (frame_start) frame_num <= frame_num + 1;
if (rst) frame_num <= 0;
else if (frame_start) frame_num <= frame_num + 1;
if (rst) copy_page <= 0;
else if (frame_start) copy_page <= !copy_page;
if (rst) copy_page <= 0;
else if (frame_start) copy_page <= !copy_page;
if (rst || copy_done) copy_run <= 0;
else if (frame_start) copy_run <= 1;
else if (frame_start) copy_run <= 1;
copy_crc <= copy_word == (PACKET_WORDS - 1);
if (!copy_run || copy_crc) copy_word <= 0;
else copy_word <= copy_word + 1;
if (!copy_run) copy_packet <= 0;
else if (copy_crc) copy_packet <= copy_packet + 1;
if (!copy_run) copy_packet <= 0;
else if (copy_crc) copy_packet <= copy_packet + 1;
// if (rst || frame_start) segment_packet <= 0;
// else if (copy_run && copy_crc) segment_packet <= (copy_packet== (FRAME_PACKETS_FULL -1))? 0: (segment_packet + 1);
if (rst || segment_start) segment_packet <= 0;
else if (segment_run && copy_crc) segment_packet <= segment_packet + 1;
if (rst) segments_cntr <= 0;
else if (segment_done) segments_cntr <= (segments_cntr == (SEGMENTS_SEQ - 1)) ? 0: (segments_cntr + 1);
if (copy_pix_only) copy_pxd <= sensor_data[copy_packet * PACKET_PIXELS + copy_word];
else copy_pxd <= 'bx;
if (copy_pix_only) copy_pxd <= sensor_data[copy_packet * PACKET_PIXELS + copy_word];
else copy_pxd <= 'bx;
if (copy_tel_only) copy_telemetry_d <= copy_telemetry_packet[1]?
telemetry_b[(PACKET_PIXELS * (2 - copy_telemetry_packet[0])-copy_word - 1)*16 +: 16]:
......@@ -234,9 +330,7 @@ always @ (posedge mclk) begin
copy_d <= (copy_packet < FRAME_PACKETS) ? copy_pxd : copy_telemetry_d;
// copy_pixels_r <= copy_pix_or_tel;
copy_pixels_pix <= copy_pix_or_tel && (copy_packet < FRAME_PACKETS);
// copy_pixels_tel <= copy_pix_or_tel && (copy_packet >= FRAME_PACKETS);
if (frame_start) frame_sum <= 0;
else if (copy_pixels_pix) frame_sum <= frame_sum + copy_pxd;
......@@ -244,9 +338,69 @@ always @ (posedge mclk) begin
if (copy_run) packed_data[copy_wa_full] <= copy_din; // copy_d;
en_avg <= copy_crc && (copy_packet == (FRAME_PACKETS - 1)); // 1 cycle after last pixel written
end
// readout, mclk part
always @ (posedge mclk) begin
if (rst) segments_ready <= 0;
else if ( segment_done && !start_segm_rd_mclk) segments_ready <= segments_ready + 1;
else if (!segment_done && start_segm_rd_mclk) segments_ready <= segments_ready - 1;
segment_av <= !rst && !sync_lost && (segments_ready >= SEGMENTS_MIN);
if (rst) sync_lost <= 0;
else if (segments_ready >= SEGMENTS_MAX) sync_lost <= 1;
end
// readout, spi_clk part
always @ (posedge rst or negedge spi_clk) begin
if (rst) readout_bit <= 0;
else if (!spi_cs) readout_bit <= readout_bit + 1;
if (rst) readout_last_bit <= 0;
else if (!spi_cs) readout_last_bit <= readout_pre_last_bit;
if (rst) readout_first_bit <= 1;
else if (!spi_cs) readout_first_bit <= readout_pre_first_bit;
if (rst) readout_good <= 0;
else if (!spi_cs && readout_first_bit && (readout_word_indx == 0)) readout_good <= readout_good_w;
if (!spi_cs) begin
if (readout_first_bit) begin
readout_sr_good <= packed_data[readout_address];
readout_sr_bad <= packet_bad[readout_word_indx];
end else begin
readout_sr_good <= {readout_sr_good[14:0], 1'b0};
readout_sr_bad <= {readout_sr_bad[14:0], 1'b0};
end
end
if (rst) readout_word_indx <= 0;
else if (!spi_cs && readout_last_bit) readout_word_indx <=packet_re_last ? 0 : (readout_word_indx + 1);
if (rst) begin
packet_re_last <= 0;
packet_sent <= 0;
// packet_skipped <= 0;
end else if (!spi_cs) begin
packet_re_last <= readout_last_word && readout_pre_last_bit;
packet_sent <= readout_last_word && readout_pre_last_bit && readout_good;
// packet_skipped <= readout_last_word && readout_pre_last_bit && !readout_good;
end
if (rst) readout_packet <= 0;
else if (!spi_cs && packet_sent) readout_packet <= readout_last_packet ? 0 : (readout_packet + 1);
if (rst) readout_segment <= 0;
else if (!spi_cs && packet_sent&& readout_last_packet) readout_segment <= readout_last_segment ? 0 : (readout_segment + 1);
if (rst) readout_page <= 0;
else if (!spi_cs && packet_sent && readout_last_packet && readout_last_segment) readout_page <= !readout_page;
end
crc16_x16x12x5x0 crc16_x16x12x5x0_i (
.clk (mclk), // input
......@@ -283,11 +437,21 @@ end
.telemetry_b (telemetry_b) // output[2559:0] reg
);
pulse_cross_clock pulse_cross_clock_start_segm_i (
.rst (rst), // input extended to include sensor reset and rst_mmcm
.src_clk (!spi_clk), // input
.dst_clk (mclk), // input
.in_pulse (start_segm_rd), // input
.out_pulse (start_segm_rd_mclk), // output
.busy() // output
);
endmodule
/*
// Most significant bit first (big-endian)
// x^16+x^12+x^5+1 = (1) 0001 0000 0010 0001 = 0x1021
......
......@@ -1836,20 +1836,20 @@ assign axi_grst = axi_rst_pre;
.SENSI2C_SLEW (SENSI2C_SLEW),
`ifdef HISPI
`elsif LWIR
.VOSPI_EN (VOSPI_EN), // 0,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 2,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 4,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 6,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 7,
.VOSPI_MRST (VOSPI_MRST), // 8,
.VOSPI_MRST (VOSPI_MRST), // 0,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 10,
.VOSPI_PWDN (VOSPI_PWDN), // 2,
.VOSPI_PWDN_BITS (VOSPI_PWDN_BITS), // 2,
.VOSPI_MCLK (VOSPI_MCLK), // 12,
.VOSPI_MCLK (VOSPI_MCLK), // 4,
.VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2,
.VOSPI_EN (VOSPI_EN), // 6,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 8,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 10,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 12,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 13,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16,
......@@ -1866,6 +1866,8 @@ assign axi_grst = axi_rst_pre;
.VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20,
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 2,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
.VOSPI_MCLK_HALFDIV (VOSPI_MCLK_HALFDIV), // 4
`else
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment