Updated Python code, added some missing comments

.project

@@ -62,42 +62,42 @@
 		<link>
 			<name>vivado_logs/VivadoBitstream.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150818191452916.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150826180314606.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOpt.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150818190618667.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150826180314606.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPhys.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150818191452916.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150826180314606.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPower.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150818190618667.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150826180314606.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoPlace.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150818190618667.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150826180314606.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoRoute.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150818191452916.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150826180314606.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150818185615292.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150826175759893.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150818191452916.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150826180314606.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
@@ -107,32 +107,32 @@
 		<link>
 			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150818191452916.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150826180314606.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150818185615292.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150826175759893.log</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-opt-phys.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150818191452916.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150826180314606.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-place.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-place-20150818190618667.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-place-20150826180314606.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-route.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-route-20150818191452916.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-route-20150826180314606.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-synth.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150818185615292.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150826175759893.dcp</location>
 		</link>
 	</linkedResources>
 </projectDescription>

py393/hargs-auto

@@ -3,6 +3,5 @@
 -f /usr/local/verilog/x393_parameters.vh   /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
 -l /usr/local/verilog/x393_cur_params_target.vh
 -p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
--c measure_all "ICWRPOASZB" 1 2 2 0xaa None 1 3
--c set_phase_delays
+-c measure_all "*ICWRPOASZB" 1 2 2 0xaa 1 0 0 3
 -c save

py393/vrlg.py

@@ -119,729 +119,1952 @@ def restore_default(vname=None):
 
 #### PyDev predefines
 
-DFLT_REFRESH_ADDR__TYPE = str
-NUM_CYCLES_09__RAW = str
-MEMBRIDGE_SIZE64__TYPE = str
-DQSTRI_LAST__TYPE = str
-DLY_LD_MASK__TYPE = str
-STATUS_MSB_RSHFT__TYPE = str
-MCONTR_BUF0_RD_ADDR = int
-MCNTRL_SCANLINE_WINDOW_WH__RAW = str
-MCNTRL_TEST01_STATUS_REG_CHN4_ADDR = int
-WSEL = int
-MCNTRL_TEST01_CHN3_STATUS_CNTRL = int
-LD_DLY_LANE1_IDELAY = int
+#### PyDev predefines
+
+SS_EN__RAW = str
+CLKIN_PERIOD_PCLK = int
+SENSI2C_STATUS_REG_REL__TYPE = str
+SENSI2C_CMD_RUN_PBITS__RAW = str
+HIST_SAXI_AWCACHE__RAW = str
+CLK_STATUS_REG_ADDR__TYPE = str
 MCONTR_TOP_16BIT_STATUS_CNTRL__TYPE = str
+HIST_SAXI_ADDR_MASK = int
 CONTROL_RBACK_ADDR_MASK = int
-MCNTRL_TILED_CHN4_ADDR = int
-WINDOW_Y0__RAW = str
-DLY_LD__RAW = str
-MCNTRL_TEST01_CHN3_MODE__RAW = str
+CMPRS_CBIT_QBANK__TYPE = str
+CLKOUT_DIV_PCLK__RAW = str
+SENS_GAMMA_CTRL__RAW = str
 DFLT_INV_CLK_DIV__RAW = str
-NUM_CYCLES_12__TYPE = str
-DLY_LANE0_DQS_WLV_IDELAY__TYPE = str
-IBUF_LOW_PWR__RAW = str
-DLY_LANE1_ODELAY__RAW = str
+SENS_LENS_SCALES_MASK__TYPE = str
+CONTROL_RBACK_DEPTH = int
+LOGGER_ADDR__RAW = str
+DFLT_DQ_TRI_OFF_PATTERN = int
+NUM_CYCLES_30__RAW = str
 DLY_DQ_IDELAY__TYPE = str
-MCONTR_TOP_0BIT_ADDR_MASK = int
 MCNTRL_TEST01_STATUS_REG_CHN4_ADDR__TYPE = str
+MCONTR_LINTILE_RST_FRAME = int
+CMPRS_CBIT_CMODE_MONO6__RAW = str
 MCONTR_PHY_0BIT_DCI_RST = int
-TILED_STARTX__TYPE = str
+SENSOR_FIFO_2DEPTH = int
 HIGH_PERFORMANCE_MODE__TYPE = str
-MCONTR_PHY_STATUS_REG_ADDR__TYPE = str
-MCONTR_TOP_16BIT_ADDR__TYPE = str
 AFI_LO_ADDR64__TYPE = str
-WBUF_DLY_WLV__TYPE = str
-TEST01_SUSPEND = int
-MCONTR_TOP_16BIT_CHN_EN = int
-NUM_XFER_BITS__TYPE = str
+CAMSYNC_TRIG_DELAY2 = int
 AFI_SIZE64 = int
-DLY_LANE1_IDELAY__TYPE = str
-REF_JITTER1__RAW = str
-MCNTRL_TILED_MASK__TYPE = str
+LOGGER_CONF_IMU_BITS = int
+SENS_JTAG_TCK__RAW = str
 MCNTRL_SCANLINE_MASK__TYPE = str
-DFLT_DQ_TRI_ON_PATTERN = int
 MCONTR_PHY_0BIT_SDRST_ACT = int
-DEFAULT_STATUS_MODE = int
-MEMBRIDGE_START64__TYPE = str
+SENSI2C_IBUF_LOW_PWR = str
+CLKOUT_DIV_PCLK2X__RAW = str
 TILED_EXTRA_PAGES__TYPE = str
-DLY_LD__TYPE = str
+DQSTRI_LAST = int
 MCNTRL_TEST01_CHN2_STATUS_CNTRL__TYPE = str
-MCNTRL_SCANLINE_FRAME_PAGE_RESET = int
 STATUS_2LSB_SHFT__TYPE = str
+SENS_SS_EN__TYPE = str
+MEMBRIDGE_LEN64__TYPE = str
+LOGGER_CONF_EN__RAW = str
+HIST_CONFIRM_WRITE = int
+CMPRS_GROUP_ADDR__TYPE = str
+CMDFRAMESEQ_ADDR_INC = int
+CAMSYNC_TRIG_PERIOD = int
+CMPRS_CBIT_FRAMES_BITS = int
+SENSOR_HIST_EN_BITS__TYPE = str
+CMDSEQMUX_STATUS__TYPE = str
+DFLT_DQS_PATTERN__TYPE = str
+MCONTR_LINTILE_SINGLE = int
+MCNTRL_TEST01_ADDR__RAW = str
+SENS_GAMMA_MODE_PAGE__RAW = str
+CLKFBOUT_PHASE_SENSOR = float
+DFLT_REFRESH_PERIOD = int
+MCONTR_TOP_0BIT_REFRESH_EN__TYPE = str
+NUM_CYCLES_20__TYPE = str
+SENS_JTAG_PGMEN = int
+NUM_CYCLES_03__TYPE = str
+CMPRS_CBIT_RUN_BITS__TYPE = str
+LD_DLY_LANE1_IDELAY__TYPE = str
+TILED_EXTRA_PAGES__RAW = str
+CMPRS_NUM_AFI_CHN = int
+CAMSYNC_TRIG_SRC__RAW = str
+MEMCLK_CAPACITANCE = str
+MULT_SAXI_ADV_RD__TYPE = str
+SENSIO_WIDTH__TYPE = str
+MCNTRL_TEST01_CHN3_STATUS_CNTRL__TYPE = str
+CONTROL_RBACK_ADDR__RAW = str
+CMPRS_AFIMUX_CYCBITS = int
+RTC_MHZ = int
+SENS_LENS_C_MASK = int
+MCONTR_PHY_16BIT_EXTRA = int
+HIST_SAXI_EN__TYPE = str
+MCONTR_PHY_16BIT_PATTERNS_TRI = int
+WINDOW_Y0__RAW = str
+CMPRS_STATUS_CNTRL = int
+CLK_STATUS_REG_ADDR__RAW = str
+CMPRS_CSAT_CB_BITS__TYPE = str
+SENSI2C_SLEW__TYPE = str
+MEMBRIDGE_WIDTH64__RAW = str
+LOGGER_CONF_MSG_BITS__RAW = str
+SENS_GAMMA_MODE_REPET = int
+CLKFBOUT_MULT_REF = int
+CMPRS_CBIT_BAYER_BITS__TYPE = str
+MCONTR_CMPRS_STATUS_INC = int
+MCONTR_PHY_0BIT_CMDA_EN__TYPE = str
+MCNTRL_TEST01_STATUS_REG_CHN1_ADDR = int
+RTC_SET_STATUS__TYPE = str
+CMPRS_CBIT_QBANK_BITS__RAW = str
+FFCLK0_IBUF_DELAY_VALUE__RAW = str
+WINDOW_HEIGHT = int
+CAMSYNC_TRIG_DELAY0__RAW = str
+MCONTR_SENS_STATUS_INC__RAW = str
+SENSOR_HIST_NRST_BITS = int
+SENSI2C_ABS_RADDR__RAW = str
+MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__RAW = str
+CLKFBOUT_MULT = int
+RTC_STATUS_REG_ADDR__RAW = str
+SENS_LENS_C_MASK__RAW = str
+NUM_CYCLES_11__TYPE = str
+CMPRS_CBIT_QBANK_BITS__TYPE = str
+SENS_GAMMA_MODE_TRIG = int
+RTC_SET_USEC = int
+RTC_BITC_PREDIV__TYPE = str
+LD_DLY_CMDA = int
+DLY_SET__RAW = str
+DFLT_REFRESH_ADDR__RAW = str
+MCNTRL_PS_ADDR__RAW = str
+NUM_FRAME_BITS__RAW = str
+LOGGER_CONF_GPS__TYPE = str
+HIST_SAXI_EN__RAW = str
+SENSOR_16BIT_BIT__RAW = str
+HIST_SAXI_AWCACHE__TYPE = str
+SENSI2C_CMD_RUN_PBITS__TYPE = str
+LOGGER_CONF_SYN_BITS__TYPE = str
+SENS_LENS_FAT0_OUT__RAW = str
+CAMSYNC_TRIG_SRC = int
+CLKOUT_DIV_PCLK__TYPE = str
+LOGGER_PAGE_IMU = int
+MEMCLK_IOSTANDARD__RAW = str
+CLKFBOUT_MULT_SYNC__TYPE = str
+MAX_TILE_HEIGHT__RAW = str
+BUF_IPCLK2X_SENS3__TYPE = str
+IBUF_LOW_PWR = str
+CMD_DONE_BIT = int
+NUM_CYCLES_31 = int
+NUM_CYCLES_30 = int
+CMPRS_CBIT_QBANK__RAW = str
+SENS_SYNC_MASK__TYPE = str
+MCONTR_BUF0_RD_ADDR__RAW = str
+SENS_PHASE_WIDTH = int
+HIST_SAXI_MODE_ADDR_MASK__TYPE = str
+MCONTR_CMPRS_STATUS_BASE__RAW = str
+SENS_LENS_RADDR__TYPE = str
+CAMSYNC_PRE_MAGIC__TYPE = str
+MCNTRL_TEST01_CHN3_STATUS_CNTRL__RAW = str
+FFCLK0_DQS_BIAS = str
+CMPRS_JP4DIFF__TYPE = str
+LOGGER_CONF_DBG__RAW = str
+FRAME_START_ADDRESS_INC__TYPE = str
+DLY_DQS_IDELAY__TYPE = str
+CLK_PHASE = float
+MCNTRL_TILED_FRAME_PAGE_RESET = int
+MCONTR_SENS_STATUS_BASE__TYPE = str
+CMPRS_FORMAT__TYPE = str
+DLY_LANE1_DQS_WLV_IDELAY__RAW = str
+SENS_LENS_RADDR = int
+PXD_IOSTANDARD = str
+MAX_TILE_HEIGHT = int
+BUF_CLK1X_PCLK = str
+LOGGER_CONF_DBG_BITS = int
+SENS_CTRL_ARO__TYPE = str
+SENS_LENS_SCALES_MASK__RAW = str
+MCNTRL_TILED_STATUS_REG_CHN2_ADDR__TYPE = str
+MCONTR_LINTILE_BYTE32__RAW = str
+HISTOGRAM_WIDTH_HEIGHT = int
+SENSOR_HIST_NRST_BITS__RAW = str
+MCONTR_RD_MASK__TYPE = str
+MULT_SAXI_CNTRL_MASK = int
+NUM_CYCLES_23__RAW = str
+REF_JITTER1__RAW = str
+CAMSYNC_MASK__TYPE = str
+SENS_JTAG_PGMEN__RAW = str
+MCONTR_LINTILE_EXTRAPG_BITS__TYPE = str
+SENS_CTRL_RST_MMCM = int
+LOGGER_CONF_EN_BITS__TYPE = str
+CLKIN_PERIOD_PCLK__RAW = str
+SENS_LENS_POST_SCALE_MASK = int
+BUF_IPCLK2X_SENS1__RAW = str
+SENSOR_MODE_WIDTH__RAW = str
+SENS_LENS_FAT0_OUT_MASK = int
+SENS_SYNC_MULT__TYPE = str
+NUM_CYCLES_27__RAW = str
+SENSI2C_IOSTANDARD__RAW = str
+SCANLINE_EXTRA_PAGES__TYPE = str
+MCONTR_SENS_BASE__RAW = str
+CMPRS_CBIT_CMODE_JP4DIFF__RAW = str
+CMPRS_AFIMUX_MASK__TYPE = str
+MCONTR_SENS_INC = int
+CAMSYNC_TRIG_PERIOD__TYPE = str
+DFLT_DQS_PATTERN = int
+SENSI2C_CMD_SCL__TYPE = str
+SENS_GAMMA_ADDR_DATA__RAW = str
+DLY_LANE1_IDELAY__RAW = str
+SLEW_CLK = str
+CMPRS_JP4DIFF = int
+RTC_STATUS_REG_ADDR = int
+SENS_LENS_BY_MASK__TYPE = str
+CMPRS_CBIT_CMODE__RAW = str
+CMPRS_JP4__TYPE = str
+AFI_MUX_BUF_LATENCY = int
+WINDOW_WIDTH = int
+CLK_CNTRL__RAW = str
+MCONTR_LINTILE_EXTRAPG_BITS = int
+MCONTR_LINTILE_RST_FRAME__TYPE = str
+LAST_BUF_FRAME__RAW = str
+CMPRS_AFIMUX_RADDR1__RAW = str
+MCNTRL_TEST01_CHN1_STATUS_CNTRL__RAW = str
+CMPRS_CBIT_DCSUB_BITS__RAW = str
+SENS_CTRL_LD_DLY__RAW = str
+HIST_SAXI_MODE_ADDR_REL__TYPE = str
+CMPRS_CBIT_CMODE_JP46__TYPE = str
+NUM_CYCLES_17__RAW = str
 DFLT_WBUF_DELAY__RAW = str
+CAMSYNC_POST_MAGIC__RAW = str
+MCNTRL_TEST01_CHN2_MODE__TYPE = str
+NUM_CYCLES_24__RAW = str
+NUM_CYCLES_13__RAW = str
+LOGGER_CONF_MSG__RAW = str
+MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
+LAST_FRAME_BITS__RAW = str
+SENS_DIVCLK_DIVIDE = int
+SENS_LENS_COEFF__RAW = str
+CMPRS_CONTROL_REG = int
+GPIO_STATUS_REG_ADDR = int
+MCNTRL_SCANLINE_WINDOW_WH__TYPE = str
+CMPRS_AFIMUX_RADDR0__TYPE = str
+MCNTRL_TILED_WINDOW_WH__RAW = str
+DLY_DM_ODELAY__RAW = str
+CMPRS_FRMT_MBRM1_BITS = int
+CAMSYNC_EXTERNAL_BIT = int
+CMPRS_STATUS_REG_BASE__TYPE = str
+AFI_MUX_BUF_LATENCY__TYPE = str
+SENSOR_CTRL_RADDR = int
+FRAME_WIDTH_BITS__RAW = str
+ADDRESS_NUMBER__RAW = str
+STATUS_PSHIFTER_RDY_MASK__TYPE = str
+SENSI2C_ADDR_MASK = int
+LD_DLY_LANE1_IDELAY = int
+SENS_SYNC_MASK = int
+DIVCLK_DIVIDE = int
+CMD_PAUSE_BITS__RAW = str
+IDELAY_VALUE__RAW = str
+MCONTR_CMPRS_STATUS_BASE = int
+BUFFER_DEPTH32 = int
+SENS_CTRL_QUADRANTS__TYPE = str
+SENS_LENS_BY_MASK__RAW = str
+DFLT_REFRESH_ADDR = int
+SENS_LENS_BX_MASK__TYPE = str
+TEST01_SUSPEND__RAW = str
+SENS_GAMMA_HEIGHT01__TYPE = str
+CMPRS_HIFREQ_REG_INC = int
+STATUS_ADDR_MASK__TYPE = str
+MCONTR_TOP_0BIT_ADDR_MASK__RAW = str
+TEST01_START_FRAME = int
+RTC_SET_USEC__RAW = str
+LOGGER_CONF_SYN_BITS__RAW = str
+CAMSYNC_ADDR__TYPE = str
+DIVCLK_DIVIDE_AXIHP__RAW = str
+CMPRS_CBIT_CMODE_JP4DIFFDIV2__TYPE = str
+SENSI2C_CMD_SCL__RAW = str
+MULT_SAXI_BSLOG1__TYPE = str
+LOGGER_CONF_MSG_BITS__TYPE = str
+LOGGER_ADDR = int
+MCONTR_PHY_0BIT_DCI_RST__RAW = str
+REFCLK_FREQUENCY__RAW = str
+LOGGER_BIT_HALF_PERIOD__RAW = str
+MCNTRL_TEST01_STATUS_REG_CHN3_ADDR__TYPE = str
+DLY_DQ_ODELAY__TYPE = str
+SENSOR_FIFO_2DEPTH__TYPE = str
+NUM_CYCLES_28 = int
+NUM_CYCLES_29 = int
+NUM_CYCLES_26 = int
+NUM_CYCLES_27 = int
+NUM_CYCLES_24 = int
+NUM_CYCLES_25 = int
+NUM_CYCLES_22 = int
+NUM_CYCLES_23 = int
+NUM_CYCLES_20 = int
+NUM_CYCLES_21 = int
+FRAME_FULL_WIDTH__TYPE = str
+CAMSYNC_TRIG_DELAY2__TYPE = str
+SENSI2C_CMD_BYTES_PBITS__TYPE = str
+CMDFRAMESEQ_REL__TYPE = str
+PICKLE = str
+AFI_SIZE64__TYPE = str
+NUM_CYCLES_LOW_BIT__TYPE = str
+MCONTR_PHY_0BIT_ADDR_MASK = int
+DFLT_WBUF_DELAY__TYPE = str
+MCNTRL_TEST01_CHN1_STATUS_CNTRL = int
+SENSI2C_STATUS_REG_INC__TYPE = str
+CMPRS_FRMT_MBRM1_BITS__RAW = str
+SCANLINE_EXTRA_PAGES = int
+LD_DLY_LANE1_ODELAY__RAW = str
+LOGGER_CONF_EN_BITS__RAW = str
+DIVCLK_DIVIDE_SYNC__RAW = str
+SENS_LENS_FAT0_IN_MASK__TYPE = str
+PHASE_CLK2X_XCLK = float
+RSEL = int
+CMPRS_CBIT_DCSUB_BITS__TYPE = str
+AXI_RD_ADDR_BITS__TYPE = str
+CAMSYNC_CHN_EN_BIT__TYPE = str
+CMDFRAMESEQ_ADDR_BASE__RAW = str
+CONTROL_ADDR__RAW = str
+SENSI2C_CMD_RESET = int
+CMPRS_FRMT_MBCM1_BITS__TYPE = str
+SENS_CTRL_QUADRANTS_EN__RAW = str
+NUM_CYCLES_14__TYPE = str
+MCONTR_CMPRS_INC__TYPE = str
+TILED_EXTRA_PAGES = int
+DLY_DQS_ODELAY__RAW = str
+CLKIN_PERIOD_PCLK__TYPE = str
+FFCLK1_DIFF_TERM__RAW = str
+SENS_JTAG_TDI__RAW = str
+MCONTR_SENS_STATUS_BASE = int
+AXI_WR_ADDR_BITS__RAW = str
+SENSI2C_CMD_RUN__TYPE = str
+CMPRS_CORING_MODE = int
+DIVCLK_DIVIDE_SYNC__TYPE = str
+LOGGER_STATUS__TYPE = str
+DFLT_REFRESH_PERIOD__TYPE = str
+SENSI2C_CMD_SCL_WIDTH = int
+MCNTRL_TILED_FRAME_FULL_WIDTH__RAW = str
+MCNTRL_TILED_MASK = int
+SENSIO_JTAG__RAW = str
+MCONTR_PHY_16BIT_ADDR_MASK__RAW = str
+SENSIO_STATUS__TYPE = str
+CLKIN_PERIOD_AXIHP__TYPE = str
+LOGGER_CONF_SYN__TYPE = str
+CAMSYNC_DELAY__RAW = str
+LOGGER_CONF_DBG_BITS__RAW = str
+FRAME_HEIGHT_BITS__RAW = str
+MCONTR_LINTILE_KEEP_OPEN = int
+CLKFBOUT_MULT_SYNC = int
+DLY_CMDA_ODELAY = long
+SENS_LENS_C = int
+MCONTR_ARBIT_ADDR_MASK = int
+MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR = int
+MCNTRL_SCANLINE_WINDOW_WH = int
+WBUF_DLY_WLV__RAW = str
+MCNTRL_TILED_FRAME_LAST = int
+MCNTRL_TEST01_CHN2_MODE__RAW = str
+CMPRS_AFIMUX_REG_ADDR0__TYPE = str
+RTC_SEC_USEC_ADDR = int
+LOGGER_CONF_DBG = int
+CAMSYNC_EN_BIT__TYPE = str
+LD_DLY_LANE0_IDELAY = int
+NUM_CYCLES_01__TYPE = str
+NUM_CYCLES_24__TYPE = str
+MCLK_PHASE__TYPE = str
+DIVCLK_DIVIDE_XCLK__RAW = str
+SENSI2C_DRIVE__TYPE = str
+SENS_CTRL_RST_MMCM__RAW = str
+GPIO_SET_STATUS = int
+GPIO_SLEW__TYPE = str
+SENS_LENS_BX__RAW = str
+TEST_INITIAL_BURST = int
+SENS_REF_JITTER1__RAW = str
+MCNTRL_TILED_FRAME_FULL_WIDTH = int
+CMDFRAMESEQ_DEPTH = int
+SENS_LENS_POST_SCALE__TYPE = str
+CMPRS_TABLES__TYPE = str
+FRAME_HEIGHT_BITS = int
+HIST_SAXI_ADDR_MASK__TYPE = str
+SENS_CTRL_LD_DLY = int
+CLKOUT_DIV_SYNC__RAW = str
+SENS_LENS_FAT0_IN_MASK__RAW = str
+SENS_LENS_AY_MASK__RAW = str
+MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE = str
+MCONTR_LINTILE_DIS_NEED__TYPE = str
+DFLT_DQS_PATTERN__RAW = str
+MCNTRL_PS_STATUS_CNTRL__TYPE = str
+MCONTR_PHY_16BIT_ADDR = int
+REF_JITTER1__TYPE = str
+FFCLK1_DIFF_TERM = str
+FFCLK0_IOSTANDARD__TYPE = str
+STATUS_MSB_RSHFT = int
+CMPRS_CONTROL_REG__RAW = str
+CLKIN_PERIOD__TYPE = str
+SENS_GAMMA_CTRL = int
+CLKFBOUT_MULT_AXIHP__RAW = str
+SENSIO_RADDR = int
+BUF_CLK1X_PCLK__RAW = str
+BUF_CLK1X_XCLK2X = str
+GPIO_N__TYPE = str
+MCONTR_BUF4_RD_ADDR__TYPE = str
+NUM_CYCLES_16__RAW = str
+LD_DLY_LANE0_ODELAY__TYPE = str
+MCONTR_TOP_16BIT_ADDR__RAW = str
+SENSIO_STATUS = int
+HIST_SAXI_MODE_ADDR_REL = int
+MCONTR_PHY_0BIT_SDRST_ACT__TYPE = str
+BUFFER_DEPTH32__TYPE = str
+CLKIN_PERIOD_AXIHP = int
+MCONTR_TOP_16BIT_REFRESH_ADDRESS = int
+HISTOGRAM_RADDR0__TYPE = str
+LOGGER_CONF_SYN_BITS = int
+NUM_CYCLES_19 = int
+MCNTRL_TEST01_MASK__TYPE = str
+SENS_CTRL_QUADRANTS_WIDTH__RAW = str
+SENSOR_FIFO_DELAY__RAW = str
+DLY_SET = int
+CMDFRAMESEQ_CTRL__TYPE = str
+NUM_CYCLES_12 = int
+SENSI2C_CMD_DLY = int
+MCNTRL_SCANLINE_FRAME_PAGE_RESET__TYPE = str
+MCNTRL_TILED_CHN2_ADDR__TYPE = str
+NUM_CYCLES_11 = int
+SENS_GAMMA_ADDR_MASK = int
+NUM_CYCLES_10 = int
+MEMCLK_IBUF_LOW_PWR__TYPE = str
+CMPRS_HIFREQ_REG_BASE__TYPE = str
+SENS_HIGH_PERFORMANCE_MODE__RAW = str
+MCNTRL_SCANLINE_FRAME_PAGE_RESET__RAW = str
+DQTRI_LAST__TYPE = str
+LD_DLY_LANE1_ODELAY__TYPE = str
+DLY_DQ_ODELAY = long
+BUF_IPCLK_SENS1__TYPE = str
+FFCLK0_IFD_DELAY_VALUE__TYPE = str
+MCONTR_TOP_16BIT_ADDR = int
+CMPRS_TIMEOUT = int
+CMPRS_AFIMUX_RST = int
+NUM_CYCLES_18 = int
+SENS_LENS_POST_SCALE_MASK__RAW = str
+NUM_CYCLES_13 = int
+CMPRS_FRMT_MBRM1__TYPE = str
+VERBOSE__RAW = str
+LOGGER_CONF_IMU_BITS__RAW = str
+NUM_CYCLES_17 = int
+NUM_CYCLES_16 = int
+NUM_CYCLES_15 = int
+NUM_CYCLES_21__TYPE = str
+CMPRS_CBIT_BAYER = int
+GPIO_PORTEN__RAW = str
+SLEW_CLK__TYPE = str
+MCONTR_PHY_0BIT_DLY_SET = int
+CLKFBOUT_DIV_REF__RAW = str
+CMD_PAUSE_BITS = int
+CMPRS_CBIT_CMODE_JP4DIFFHDR__RAW = str
+SENSIO_STATUS_REG_REL = int
+BUF_IPCLK_SENS3__TYPE = str
+MCNTRL_TILED_MODE = int
+MCNTRL_TILED_WINDOW_STARTXY__TYPE = str
+MCNTRL_TEST01_CHN2_STATUS_CNTRL__RAW = str
+LOGGER_CONF_SYN = int
+MCNTRL_TILED_CHN4_ADDR__RAW = str
+CLK_DIV_PHASE__RAW = str
+MCONTR_PHY_16BIT_PATTERNS__TYPE = str
+MCONTR_PHY_0BIT_CKE_EN__RAW = str
+NUM_CYCLES_26__TYPE = str
+PICKLE__RAW = str
+DQSTRI_LAST__RAW = str
+SENSI2C_CMD_DLY_PBITS__TYPE = str
+WRITELEV_OFFSET__TYPE = str
+CMPRS_BASE_INC = int
+GPIO_IOSTANDARD__TYPE = str
+FFCLK1_IBUF_LOW_PWR = str
+HIST_SAXI_ADDR_REL__RAW = str
+CMPRS_CBIT_CMODE_MONO4__TYPE = str
+HIST_SAXI_MODE_WIDTH__RAW = str
+SENS_LENS_AX = int
+MCONTR_PHY_16BIT_PATTERNS = int
+SENSOR_CTRL_ADDR_MASK__TYPE = str
+CMPRS_MONO16__RAW = str
+RTC_ADDR = int
+MCLK_PHASE__RAW = str
+SENSIO_RADDR__TYPE = str
+CLKFBOUT_MULT_PCLK__TYPE = str
+CLK_ADDR__TYPE = str
+CMPRS_FORMAT = int
+FFCLK1_CAPACITANCE = str
+CMPRS_CBIT_CMODE_BITS__RAW = str
+CMPRS_TABLES = int
+HIST_SAXI_MODE_WIDTH = int
+CMPRS_AFIMUX_RADDR0__RAW = str
+CAMSYNC_EN_BIT = int
+MCONTR_PHY_16BIT_PATTERNS__RAW = str
+HISTOGRAM_RAM_MODE = str
+SENS_REFCLK_FREQUENCY__TYPE = str
+SENS_GAMMA_MODE_EN__RAW = str
+MULT_SAXI_ADV_WR__RAW = str
+LOGGER_PAGE_GPS = int
+HIST_SAXI_MODE_ADDR_MASK = int
+WRITELEV_OFFSET = int
+LOGGER_CONF_MSG = int
+CMPRS_CSAT_CR__RAW = str
+CMPRS_CBIT_RUN = int
+SENS_LENS_ADDR_MASK__RAW = str
+SENS_CTRL_QUADRANTS__RAW = str
+RTC_MASK__RAW = str
+SENS_LENS_ADDR_MASK__TYPE = str
+FFCLK0_IFD_DELAY_VALUE__RAW = str
+SENS_LENS_AX__TYPE = str
+PXD_DRIVE__TYPE = str
+HIST_SAXI_NRESET = int
+MULT_SAXI_HALF_BRAM_IN__RAW = str
+CMPRS_CBIT_CMODE_JP4DIFFHDR__TYPE = str
+CMPRS_CBIT_CMODE_JP4__RAW = str
+DFLT_DQM_PATTERN__RAW = str
+GPIO_SET_STATUS__RAW = str
+SENS_JTAG_TCK = int
+REFRESH_OFFSET__TYPE = str
+SENS_CTRL_ARST__RAW = str
+CMPRS_CBIT_DCSUB__TYPE = str
+DFLT_INV_CLK_DIV__TYPE = str
+PHASE_CLK2X_XCLK__TYPE = str
+SENS_GAMMA_MODE_BAYER__RAW = str
+MCNTRL_PS_STATUS_REG_ADDR__TYPE = str
+CMPRS_CBIT_FOCUS_BITS__TYPE = str
+STATUS_ADDR__RAW = str
+NUM_CYCLES_30__TYPE = str
+SDCLK_PHASE__RAW = str
+SENS_SYNC_RADDR__TYPE = str
+BUF_IPCLK_SENS0__TYPE = str
+SENSI2C_CMD_RUN__RAW = str
+FFCLK1_IFD_DELAY_VALUE__RAW = str
+SENS_GAMMA_MODE_WIDTH__TYPE = str
+MCNTRL_TILED_STARTADDR__TYPE = str
+DLY_LD_MASK = int
+MCONTR_LINTILE_BYTE32 = int
+NUM_CYCLES_09__RAW = str
+SENS_SYNC_LBITS__RAW = str
+MEMBRIDGE_SIZE64__TYPE = str
+SENS_GAMMA_HEIGHT2 = int
+DLY_LD_MASK__TYPE = str
+STATUS_MSB_RSHFT__TYPE = str
+MCONTR_BUF0_RD_ADDR = int
+MCONTR_LINTILE_RST_FRAME__RAW = str
+CMPRS_CBIT_CMODE_JPEG20 = int
+CMPRS_TIMEOUT_BITS = int
+CAMSYNC_PRE_MAGIC = int
+SENS_JTAG_TMS = int
+MCNTRL_TEST01_CHN3_STATUS_CNTRL = int
+MCNTRL_PS_EN_RST__TYPE = str
+BUF_CLK1X_PCLK2X__TYPE = str
+FFCLK1_IFD_DELAY_VALUE__TYPE = str
+MCNTRL_TILED_CHN4_ADDR = int
+MCONTR_SENS_INC__TYPE = str
+LOGGER_MASK__RAW = str
+IBUF_LOW_PWR__RAW = str
+DLY_CMDA_ODELAY__TYPE = str
+SENS_LENS_FAT0_OUT_MASK__TYPE = str
+SENSI2C_ABS_RADDR__TYPE = str
+MCONTR_PHY_STATUS_REG_ADDR__TYPE = str
+WBUF_DLY_WLV__TYPE = str
+SENS_JTAG_TMS__TYPE = str
+MEMBRIDGE_WIDTH64__TYPE = str
+MCONTR_TOP_16BIT_CHN_EN = int
+BUF_IPCLK2X_SENS1__TYPE = str
+DEFAULT_STATUS_MODE = int
+CMPRS_CBIT_CMODE_JPEG18__TYPE = str
+MULT_SAXI_AWCACHE = int
+MCNTRL_SCANLINE_FRAME_PAGE_RESET = int
 MCNTRL_TILED_FRAME_PAGE_RESET__TYPE = str
-TILE_VSTEP__RAW = str
-MEMBRIDGE_LEN64__TYPE = str
-NUM_CYCLES_04 = int
+CMPRS_CBIT_CMODE_JP46DC__RAW = str
+CMPRS_CSAT_CR_BITS__TYPE = str
 NUM_CYCLES_05 = int
-DLY_LD = int
+NUM_CYCLES_06 = int
 NUM_CYCLES_07 = int
 NUM_CYCLES_00 = int
 NUM_CYCLES_01 = int
-MCNTRL_SCANLINE_CHN1_ADDR__TYPE = str
+NUM_CYCLES_02 = int
 NUM_CYCLES_03 = int
+SENSIO_ADDR_MASK__TYPE = str
+DIVCLK_DIVIDE_XCLK = int
 NUM_CYCLES_08 = int
 NUM_CYCLES_09 = int
 MCNTRL_TEST01_CHN4_STATUS_CNTRL__TYPE = str
-NUM_CYCLES_13__RAW = str
-MCONTR_BUF0_RD_ADDR__TYPE = str
-STATUS_ADDR__RAW = str
-DLY_LANE0_IDELAY__TYPE = str
-MCNTRL_PS_ADDR__TYPE = str
-WINDOW_WIDTH__RAW = str
+SENS_SYNC_LBITS = int
+STATUS_DEPTH__RAW = str
+NUM_CYCLES_25__TYPE = str
+SENSI2C_CMD_DLY_PBITS__RAW = str
+MCONTR_LINTILE_REPEAT = int
 CHNBUF_READ_LATENCY = int
-DFLT_DQS_PATTERN__TYPE = str
+SENS_CTRL_QUADRANTS_WIDTH = int
 STATUS_PSHIFTER_RDY_MASK__RAW = str
-MCNTRL_TEST01_ADDR__RAW = str
 TILE_WIDTH__TYPE = str
-DFLT_REFRESH_PERIOD = int
-MCNTRL_TILED_MASK__RAW = str
+MCNTRL_TILED_FRAME_LAST__RAW = str
 MCONTR_TOP_0BIT_REFRESH_EN__RAW = str
-MCONTR_PHY_16BIT_ADDR__RAW = str
 REFRESH_OFFSET = int
 MCNTRL_PS_EN_RST = int
-DLY_DQS_ODELAY__RAW = str
 MCNTRL_TILED_TILE_WHS = int
-FRAME_START_ADDRESS__TYPE = str
-MCNTRL_TILED_STATUS_REG_CHN2_ADDR = int
-MCNTRL_TILED_STATUS_CNTRL__RAW = str
-MEMBRIDGE_ADDR__RAW = str
-DLY_PHASE = int
-DFLT_DQS_TRI_OFF_PATTERN = int
-NUM_CYCLES_03__TYPE = str
+SENS_GAMMA_ADDR_MASK__TYPE = str
+CMPRS_CSAT_CR = int
+CMPRS_CBIT_RUN_ENABLE = int
+INITIALIZE_OFFSET = int
 MCONTR_TOP_16BIT_CHN_EN__TYPE = str
-LD_DLY_LANE1_IDELAY__TYPE = str
-MCNTRL_SCANLINE_CHN1_ADDR = int
-TILED_EXTRA_PAGES__RAW = str
-T_RFC = int
+CMPRS_CSAT_CB = int
+CLKFBOUT_MULT_AXIHP__TYPE = str
 VERBOSE = int
 DLY_LANE1_ODELAY = long
-MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE = str
-CMD_DONE_BIT__TYPE = str
-MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__RAW = str
+LOGGER_PERIOD__RAW = str
 MCNTRL_SCANLINE_STATUS_CNTRL__TYPE = str
-CLKFBOUT_DIV_AXIHP = int
-NUM_CYCLES_13__TYPE = str
+SENS_LENS_AX_MASK = int
 AXI_RD_ADDR_BITS__RAW = str
-MCNTRL_TEST01_CHN3_STATUS_CNTRL__TYPE = str
-CONTROL_RBACK_ADDR__RAW = str
-MCONTR_WR_MASK__RAW = str
-MCNTRL_TILED_WINDOW_STARTXY = int
-MCONTR_TOP_0BIT_MCONTR_EN = int
-SCANLINE_EXTRA_PAGES__RAW = str
+RTC_BITC_PREDIV = int
+SENS_SS_MOD_PERIOD__TYPE = str
+BUF_CLK1X_SYNC__RAW = str
+SENS_JTAG_PGMEN__TYPE = str
 MEMBRIDGE_LEN64__RAW = str
-MCONTR_PHY_16BIT_EXTRA = int
+MCONTR_LINTILE_EN = int
+GPIO_N = int
 MCONTR_ARBIT_ADDR_MASK__TYPE = str
+SENS_CTRL_MRST__TYPE = str
+FFCLK0_IBUF_LOW_PWR__TYPE = str
+FFCLK1_DQS_BIAS__TYPE = str
+SENSI2C_CMD_SDA_WIDTH = int
+SENS_GAMMA_RADDR = int
+NUM_CYCLES_14__RAW = str
+CMPRS_AFIMUX_MASK__RAW = str
+PHASE_WIDTH__TYPE = str
+CMPRS_JP4__RAW = str
+CMPRS_HIFREQ_REG_BASE__RAW = str
+SS_MOD_PERIOD = int
+MCONTR_CMPRS_BASE__TYPE = str
+TEST01_SUSPEND__TYPE = str
+SENS_LENS_POST_SCALE = int
+LOGGER_STATUS_REG_ADDR__TYPE = str
+MEMBRIDGE_LO_ADDR64__TYPE = str
+MCONTR_CMD_WR_ADDR__RAW = str
+CMDFRAMESEQ_CTRL = int
+DLY_LD__TYPE = str
+MCNTRL_SCANLINE_STARTADDR__TYPE = str
+SENS_JTAG_PROG__RAW = str
+CMDFRAMESEQ_REL__RAW = str
+CMPRS_AFIMUX_MASK = int
+DLY_PHASE = int
+CONTROL_RBACK_DEPTH__RAW = str
+MCONTR_LINTILE_NRESET__RAW = str
+CLKOUT_DIV_XCLK2X__RAW = str
+PHASE_WIDTH = int
+DFLT_DQ_TRI_OFF_PATTERN__TYPE = str
+MCNTRL_SCANLINE_MASK = int
+CLKOUT_DIV_XCLK2X = int
+MULT_SAXI_BSLOG3__TYPE = str
+CLKFBOUT_MULT__RAW = str
+CMPRS_STATUS_REG_INC__RAW = str
+HISTOGRAM_RADDR0__RAW = str
+STATUS_ADDR_MASK = int
+SENS_LENS_AY = int
+CMPRS_CBIT_CMODE_MONO6__TYPE = str
+HISTOGRAM_RAM_MODE__RAW = str
+SENS_LENS_AX_MASK__RAW = str
+CMPRS_FRMT_MBCM1__TYPE = str
+SENSOR_HIST_EN_BITS__RAW = str
+MULT_SAXI_ADV_WR = int
+NUM_CYCLES_10__TYPE = str
+MCONTR_LINTILE_EXTRAPG__RAW = str
+SENS_LENS_FAT0_IN__RAW = str
+CMPRS_AFIMUX_STATUS_CNTRL__TYPE = str
+LOGGER_CONFIG__RAW = str
+LD_DLY_LANE0_ODELAY__RAW = str
+CMPRS_FRMT_LMARG_BITS = int
+CMDSEQMUX_ADDR = int
+CLKOUT_DIV_AXIHP = int
+MCNTRL_SCANLINE_PENDING_CNTR_BITS__TYPE = str
+DLY_DQS_IDELAY__RAW = str
+CONTROL_RBACK_ADDR_MASK__TYPE = str
+MCONTR_BUF4_WR_ADDR = int
+SENS_DIVCLK_DIVIDE__RAW = str
+SENSOR_BASE_INC__RAW = str
+CMPRS_CBIT_DCSUB_BITS = int
+MCONTR_TOP_16BIT_ADDR_MASK = int
+PXD_IBUF_LOW_PWR__TYPE = str
+MCONTR_LINTILE_REPEAT__TYPE = str
+GPIO_ADDR__TYPE = str
+HISTOGRAM_RADDR2__RAW = str
+SENSI2C_STATUS = int
+CMPRS_CBIT_CMODE_JP4DIFF__TYPE = str
+SENS_SYNC_LATE_DFLT = int
+SENSI2C_STATUS_REG_BASE__RAW = str
+AFI_LO_ADDR64__RAW = str
+BUF_IPCLK_SENS1__RAW = str
+MCNTRL_SCANLINE_STARTADDR__RAW = str
+SENSI2C_STATUS_REG_BASE__TYPE = str
+MCONTR_PHY_16BIT_WBUF_DELAY = int
+DLY_LANE1_DQS_WLV_IDELAY__TYPE = str
+TILE_HEIGHT__RAW = str
+MEMBRIDGE_MODE__RAW = str
+CMPRS_CBIT_RUN_STANDALONE = int
+READ_BLOCK_OFFSET__RAW = str
+HISTOGRAM_LEFT_TOP__TYPE = str
+MCONTR_CMPRS_INC = int
+CMPRS_CBIT_RUN_ENABLE__TYPE = str
+LOGGER_CONF_IMU = int
+DLY_DQS_IDELAY = long
+HISTOGRAM_WIDTH_HEIGHT__TYPE = str
+TEST01_NEXT_PAGE = int
+MCNTRL_TEST01_STATUS_REG_CHN4_ADDR__RAW = str
+PXD_IBUF_LOW_PWR = str
+NUM_CYCLES_17__TYPE = str
+SLEW_CLK__RAW = str
+MCONTR_BUF2_WR_ADDR = int
+SENS_LENS_FAT0_IN__TYPE = str
+SENSIO_CTRL__TYPE = str
+SENSIO_WIDTH__RAW = str
+CMPRS_MASK__TYPE = str
+MEMBRIDGE_SIZE64__RAW = str
+SENSI2C_CMD_SDA_WIDTH__TYPE = str
+MCNTRL_PS_STATUS_CNTRL = int
+CLKOUT_DIV_SYNC = int
+SS_MODE__TYPE = str
+SENSI2C_STATUS__RAW = str
+CMPRS_MASK = int
+MCONTR_BUF4_RD_ADDR__RAW = str
+T_RFC__TYPE = str
+MCONTR_LINTILE_NRESET__TYPE = str
+SENS_NUM_SUBCHN__RAW = str
+CMPRS_CBIT_RUN_ENABLE__RAW = str
+BUF_IPCLK_SENS3__RAW = str
+CLK_STATUS__RAW = str
+FRAME_WIDTH_BITS = int
+READ_PATTERN_OFFSET__TYPE = str
+MCONTR_BUF3_RD_ADDR__TYPE = str
+MAX_TILE_WIDTH__TYPE = str
+MCONTR_CMD_WR_ADDR = int
+REF_JITTER1 = float
+CMDSEQMUX_STATUS = int
+TILE_WIDTH = int
+GPIO_MASK = int
+DLY_LANE0_ODELAY = long
+NUM_XFER_BITS = int
+MCNTRL_TEST01_STATUS_REG_CHN2_ADDR = int
+DLY_DQS_ODELAY__TYPE = str
+DLY_LANE0_ODELAY__RAW = str
+MCONTR_BUF3_WR_ADDR__TYPE = str
+SCANLINE_STARTX__TYPE = str
+WRITE_BLOCK_OFFSET = int
+FRAME_FULL_WIDTH__RAW = str
+LOGGER_CONF_EN__TYPE = str
+LOGGER_PAGE_IMU__RAW = str
+SENS_SYNC_MINPER__RAW = str
+CMPRS_AFIMUX_MODE__RAW = str
+SENS_SYNC_LATE__RAW = str
+MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__RAW = str
+CHNBUF_READ_LATENCY__TYPE = str
+CMPRS_CBIT_CMODE_BITS__TYPE = str
+LOGGER_BIT_DURATION__TYPE = str
+RTC_MHZ__RAW = str
+SENSI2C_CMD_BYTES_PBITS__RAW = str
+TEST_INITIAL_BURST__TYPE = str
+NUM_CYCLES_19__RAW = str
+MCNTRL_PS_MASK__RAW = str
+CMPRS_CBIT_CMODE_JPEG20__TYPE = str
+CMPRS_TIMEOUT_BITS__RAW = str
+MEMBRIDGE_LO_ADDR64__RAW = str
+MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR = int
+RTC_SET_USEC__TYPE = str
+MULT_SAXI_BSLOG3__RAW = str
+CMPRS_TIMEOUT_BITS__TYPE = str
+SENS_GAMMA_MODE_WIDTH__RAW = str
+PHASE_CLK2X_PCLK__TYPE = str
+FFCLK1_DIFF_TERM__TYPE = str
+MCONTR_PHY_0BIT_ADDR_MASK__TYPE = str
+DIVCLK_DIVIDE_AXIHP__TYPE = str
+MULT_SAXI_ADV_RD__RAW = str
+SENS_SYNC_RADDR = int
+T_RFC__RAW = str
+WBUF_DLY_DFLT__TYPE = str
+PXD_SLEW__TYPE = str
+SENSI2C_REL_RADDR__RAW = str
+MCONTR_RD_MASK__RAW = str
+LOGGER_CONF_EN = int
+FFCLK0_CAPACITANCE = str
+SS_EN__TYPE = str
+SENS_GAMMA_MODE_BAYER__TYPE = str
+FRAME_START_ADDRESS_INC = int
+TILED_STARTY = int
+MEMBRIDGE_MODE__TYPE = str
+LOGGER_MASK = int
+MCNTRL_SCANLINE_FRAME_FULL_WIDTH = int
+WINDOW_Y0 = int
+CAMSYNC_PRE_MAGIC__RAW = str
+MCNTRL_TILED_TILE_WHS__TYPE = str
+SENSOR_CHN_EN_BIT = int
+LD_DLY_LANE0_ODELAY = int
+FFCLK1_IBUF_DELAY_VALUE__RAW = str
+CMPRS_MONO16__TYPE = str
+READ_PATTERN_OFFSET__RAW = str
+MEMBRIDGE_SIZE64 = int
+MCONTR_PHY_0BIT_CKE_EN__TYPE = str
+CMPRS_FRMT_MBCM1_BITS = int
+HISTOGRAM_RAM_MODE__TYPE = str
+AFI_LO_ADDR64 = int
+NUM_CYCLES_07__TYPE = str
+SENS_LENS_FAT0_IN = int
+CMPRS_FRMT_LMARG_BITS__TYPE = str
+HISTOGRAM_RADDR1__TYPE = str
+CAMSYNC_MASTER_BIT__TYPE = str
+HISTOGRAM_ADDR_MASK = int
+MCONTR_BUF2_RD_ADDR__RAW = str
+MCONTR_TOP_16BIT_ADDR_MASK__RAW = str
+VERBOSE__TYPE = str
+BUF_CLK1X_PCLK__TYPE = str
+BUF_CLK1X_AXIHP__TYPE = str
+MULT_SAXI_BSLOG1__RAW = str
+CLKFBOUT_MULT_PCLK__RAW = str
+MCONTR_SENS_STATUS_INC__TYPE = str
+CAMSYNC_TRIG_DELAY0__TYPE = str
+CLKFBOUT_PHASE__TYPE = str
+MCNTRL_TILED_WINDOW_WH = int
+CMDFRAMESEQ_MASK = int
+CLK_ADDR = int
+MCNTRL_TILED_WINDOW_X0Y0__TYPE = str
+NUM_XFER_BITS__RAW = str
+MCNTRL_TILED_WINDOW_STARTXY__RAW = str
+CMPRS_CSAT_CB_BITS__RAW = str
+CMPRS_CBIT_RUN__RAW = str
+SENS_GAMMA_RADDR__RAW = str
+SENS_CTRL_EXT_CLK = int
+MCNTRL_SCANLINE_FRAME_LAST = int
+MCNTRL_TILED_STATUS_REG_CHN4_ADDR = int
+GPIO_SET_PINS__RAW = str
+SENS_CTRL_RST_MMCM__TYPE = str
+AFI_MUX_BUF_LATENCY__RAW = str
+CMPRS_CBIT_CMODE_JP46__RAW = str
+GPIO_DRIVE__RAW = str
+GPIO_IBUF_LOW_PWR__TYPE = str
+SENS_SYNC_FBITS__RAW = str
+CMPRS_CORING_MODE__TYPE = str
+CMPRS_FRMT_MBRM1_BITS__TYPE = str
+MCNTRL_TILED_TILE_WHS__RAW = str
+SENS_REFCLK_FREQUENCY = float
+CMD_PAUSE_BITS__TYPE = str
+SENS_CTRL_EXT_CLK__TYPE = str
+SENS_LENS_BY = int
+SENS_LENS_BX = int
+NUM_CYCLES_02__TYPE = str
+MCNTRL_TILED_STARTADDR = int
+TILE_HEIGHT__TYPE = str
+MCNTRL_TILED_CHN4_ADDR__TYPE = str
+CMPRS_JP4 = int
+TILED_STARTX__TYPE = str
+FFCLK0_DIFF_TERM__RAW = str
+MCNTRL_PS_STATUS_CNTRL__RAW = str
+MCONTR_TOP_STATUS_REG_ADDR = int
+SENSI2C_STATUS_REG_INC__RAW = str
+SDCLK_PHASE = float
+SLEW_CMDA = str
+MCNTRL_SCANLINE_MODE__TYPE = str
+GPIO_N__RAW = str
 TEST01_NEXT_PAGE__TYPE = str
+CMPRS_CBIT_CMODE_JPEG18 = int
+CONTROL_RBACK_ADDR = int
+T_REFI__RAW = str
+CLKFBOUT_MULT_SENSOR = int
+CMPRS_AFIMUX_EN = int
+COLADDR_NUMBER = int
+MCNTRL_TILED_STARTADDR__RAW = str
+CAMSYNC_DELAY = int
+BUF_IPCLK2X_SENS2__TYPE = str
+MCNTRL_TEST01_CHN1_MODE__RAW = str
+FFCLK0_IOSTANDARD__RAW = str
+DFLT_DQS_TRI_ON_PATTERN__TYPE = str
+MCONTR_PHY_0BIT_DLY_RST__TYPE = str
+TILED_KEEP_OPEN__RAW = str
+MCONTR_TOP_0BIT_ADDR__TYPE = str
+CLKFBOUT_PHASE_SENSOR__RAW = str
+MCONTR_SENS_BASE = int
+CMPRS_CBIT_RUN__TYPE = str
+SENS_LENS_FAT0_OUT = int
+MCNTRL_SCANLINE_FRAME_SIZE = int
+STATUS_DEPTH = int
+SENSI2C_CMD_SCL = int
+NUM_CYCLES_20__RAW = str
+MCNTRL_SCANLINE_WINDOW_STARTXY__RAW = str
+CAMSYNC_EXTERNAL_BIT__RAW = str
+BUF_CLK1X_XCLK2X__RAW = str
+MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str
+SENSI2C_CMD_BYTES = int
+HIST_SAXI_MODE_WIDTH__TYPE = str
+MCONTR_PHY_0BIT_ADDR__TYPE = str
+MCONTR_CMPRS_INC__RAW = str
+CMPRS_HIFREQ_REG_INC__RAW = str
+SENSOR_DATA_WIDTH__RAW = str
+MEMBRIDGE_MASK = int
+DLY_SET__TYPE = str
+CMPRS_STATUS_REG_INC = int
+FFCLK0_CAPACITANCE__TYPE = str
+LAST_FRAME_BITS__TYPE = str
+CLK_MASK__RAW = str
+DLY_DM_ODELAY = long
+MEMBRIDGE_STATUS_CNTRL__RAW = str
+MEMBRIDGE_STATUS_REG = int
+CMPRS_CBIT_CMODE_JPEG18__RAW = str
+IPCLK2X_PHASE = float
+CMPRS_CBIT_FOCUS_BITS = int
+LOGGER_CONF_SYN__RAW = str
+CMPRS_COLOR20 = int
+SENSIO_DELAYS__TYPE = str
+ADDRESS_NUMBER__TYPE = str
+WSEL__TYPE = str
+FFCLK1_IBUF_DELAY_VALUE = str
+CMPRS_AFIMUX_CYCBITS__RAW = str
+NUM_CYCLES_09__TYPE = str
+LD_DLY_LANE0_IDELAY__RAW = str
+FRAME_WIDTH_BITS__TYPE = str
+SENS_SYNC_LBITS__TYPE = str
+NUM_CYCLES_25__RAW = str
+SENSOR_NUM_HISTOGRAM__RAW = str
+CMPRS_CBIT_CMODE = int
+HIST_SAXI_ADDR_MASK__RAW = str
+MEMBRIDGE_STATUS_REG__TYPE = str
+CLKIN_PERIOD__RAW = str
+SENS_SYNC_MULT__RAW = str
+SENS_LENS_BY__TYPE = str
+NUM_CYCLES_02__RAW = str
+MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__RAW = str
+MCNTRL_TILED_WINDOW_X0Y0 = int
+MCONTR_TOP_16BIT_REFRESH_PERIOD__RAW = str
+MULT_SAXI_WLOG__TYPE = str
+STATUS_2LSB_SHFT = int
+CMPRS_CBIT_CMODE_JP4DC = int
+NUM_CYCLES_08__TYPE = str
+NUM_CYCLES_LOW_BIT__RAW = str
+MCONTR_PHY_16BIT_WBUF_DELAY__RAW = str
+SENS_SYNC_MINBITS = int
+MCNTRL_SCANLINE_WINDOW_STARTXY = int
+BUF_IPCLK_SENS2__RAW = str
+CMPRS_STATUS_CNTRL__TYPE = str
+MCONTR_RD_MASK = int
+CMPRS_COLOR_SATURATION = int
+NUM_CYCLES_21__RAW = str
+SENSIO_DELAYS__RAW = str
+CMDFRAMESEQ_RUN_BIT = int
+SENS_SYNC_MINPER = int
+CMPRS_FRMT_MBRM1__RAW = str
+DFLT_CHN_EN__TYPE = str
+LOGGER_BIT_HALF_PERIOD = int
+CMPRS_CBIT_CMODE_JP4 = int
+CAMSYNC_TRIGGERED_BIT = int
+SENSI2C_CMD_SDA__TYPE = str
+LOGGER_PAGE_IMU__TYPE = str
+LOGGER_PAGE_GPS__RAW = str
+SENS_PHASE_WIDTH__TYPE = str
+CMPRS_COLOR18__TYPE = str
+CMPRS_HIFREQ_REG_INC__TYPE = str
+MCNTRL_TILED_CHN2_ADDR = int
+MCNTRL_TILED_STATUS_CNTRL = int
+NUM_CYCLES_29__RAW = str
+GPIO_SET_STATUS__TYPE = str
+SENSIO_STATUS_REG_REL__RAW = str
+FFCLK0_CAPACITANCE__RAW = str
+CMDFRAMESEQ_ABS = int
+CMPRS_MONO8 = int
+MULT_SAXI_ADDR__RAW = str
+FFCLK1_IBUF_DELAY_VALUE__TYPE = str
+TILED_KEEP_OPEN = int
+MCNTRL_SCANLINE_MASK__RAW = str
+MULT_SAXI_STATUS_REG__RAW = str
+MCONTR_LINTILE_EN__RAW = str
+SENSI2C_ADDR_MASK__TYPE = str
+CAMSYNC_EXTERNAL_BIT__TYPE = str
+CMPRS_BASE_INC__RAW = str
+SENS_SYNC_FBITS = int
+BUF_IPCLK_SENS0__RAW = str
+MCNTRL_TEST01_ADDR = int
+MCONTR_TOP_0BIT_MCONTR_EN__TYPE = str
+MEMBRIDGE_CTRL__TYPE = str
+TILED_KEEP_OPEN__TYPE = str
+CMPRS_CBIT_RUN_RST__TYPE = str
+LOGGER_CONF_GPS_BITS__RAW = str
+CLK_STATUS_REG_ADDR = int
+CLK_DIV_PHASE__TYPE = str
+MULT_SAXI_BSLOG0__RAW = str
+PXD_DRIVE__RAW = str
+GPIO_SET_PINS = int
+SENSOR_CHN_EN_BIT__TYPE = str
+LOGGER_BIT_DURATION = int
+CAMSYNC_MODE__TYPE = str
+CHNBUF_READ_LATENCY__RAW = str
+NUM_CYCLES_12__RAW = str
+CMPRS_CBIT_RUN_BITS__RAW = str
+CMPRS_AFIMUX_RST__TYPE = str
+LD_DLY_PHASE = int
+SENSI2C_CTRL_RADDR__TYPE = str
+SENSIO_ADDR_MASK__RAW = str
+LOGGER_CONF_EN_BITS = int
+NUM_CYCLES_22__RAW = str
+CAMSYNC_POST_MAGIC = int
+PXD_IBUF_LOW_PWR__RAW = str
+PXD_DRIVE = int
+MULT_SAXI_BSLOG2__RAW = str
+CLK_CNTRL__TYPE = str
+GPIO_MASK__RAW = str
+DFLT_REFRESH_ADDR__TYPE = str
+SENS_GAMMA_MODE_REPET__TYPE = str
+CAMSYNC_TRIG_PERIOD__RAW = str
+SENS_BANDWIDTH__RAW = str
+SENSI2C_CMD_DLY_PBITS = int
+MCNTRL_TEST01_STATUS_REG_CHN4_ADDR = int
+LOGGER_PERIOD__TYPE = str
+WSEL = int
+SENS_REFCLK_FREQUENCY__RAW = str
+LOGGER_STATUS_MASK__TYPE = str
+LOGGER_CONF_IMU__RAW = str
+CMPRS_CBIT_CMODE_JP4DC__RAW = str
+MCNTRL_TEST01_CHN3_MODE__RAW = str
+MCNTRL_TEST01_CHN1_MODE__TYPE = str
+SENS_SYNC_FBITS__TYPE = str
+MCONTR_TOP_0BIT_ADDR_MASK = int
+CMDFRAMESEQ_REL = int
+CAMSYNC_POST_MAGIC__TYPE = str
+NUM_CYCLES_29__TYPE = str
+RTC_SET_SEC__TYPE = str
+CAMSYNC_ADDR = int
+RTC_SET_CORR__TYPE = str
+DLY_LANE1_IDELAY__TYPE = str
+SLEW_DQ__RAW = str
+CMPRS_CBIT_CMODE_JPEG20__RAW = str
+FFCLK0_IBUF_DELAY_VALUE = str
+CLK_STATUS = int
+GPIO_ADDR__RAW = str
+MEMBRIDGE_START64__TYPE = str
+CMPRS_CBIT_CMODE_JP46 = int
+MEMCLK_CAPACITANCE__TYPE = str
+MCONTR_BUF0_WR_ADDR__RAW = str
+SENS_GAMMA_MODE_WIDTH = int
+SENS_SS_MODE = str
+CAMSYNC_TRIG_DST = int
+DLY_LANE1_ODELAY__TYPE = str
+CMPRS_AFIMUX_WIDTH__TYPE = str
+TILE_VSTEP__RAW = str
+CMPRS_CBIT_QBANK = int
+CMPRS_AFIMUX_WIDTH = int
+HISTOGRAM_ADDR_MASK__TYPE = str
+HISTOGRAM_RADDR3__TYPE = str
+SENSOR_NUM_HISTOGRAM = int
+HIST_SAXI_NRESET__RAW = str
+CMPRS_COLOR18 = int
+LOGGER_CONF_MSG__TYPE = str
+MCNTRL_TILED_MASK__RAW = str
+MCNTRL_TILED_STATUS_REG_CHN2_ADDR = int
+MCNTRL_TILED_STATUS_CNTRL__RAW = str
+CMPRS_CBIT_BAYER__RAW = str
+DFLT_DQS_TRI_OFF_PATTERN = int
+SENSIO_JTAG__TYPE = str
+SENSOR_GROUP_ADDR__RAW = str
+LOGGER_MASK__TYPE = str
+T_RFC = int
+CAMSYNC_TRIG_DELAY3__RAW = str
+FFCLK1_IOSTANDARD__RAW = str
+CMD_DONE_BIT__TYPE = str
+SENSOR_DATA_WIDTH__TYPE = str
+SENS_LENS_SCALES__RAW = str
+SENSOR_MODE_WIDTH = int
+RTC_BITC_PREDIV__RAW = str
+CMPRS_CORING_BITS__TYPE = str
+STATUS_DEPTH__TYPE = str
+CMPRS_AFIMUX_CYCBITS__TYPE = str
+SENS_SS_EN__RAW = str
+SENS_LENS_ADDR_MASK = int
+SENSOR_CTRL_RADDR__TYPE = str
+CMPRS_CBIT_FRAMES_SINGLE__RAW = str
+CLKOUT_DIV_PCLK = int
 MCONTR_PHY_0BIT_DLY_SET__TYPE = str
+PXD_IOSTANDARD__TYPE = str
 MCONTR_PHY_STATUS_REG_ADDR = int
-NUM_CYCLES_LOW_BIT = int
-CLKFBOUT_MULT_REF = int
-NUM_CYCLES_14__RAW = str
-MCONTR_PHY_0BIT_CMDA_EN__TYPE = str
-MCNTRL_TEST01_STATUS_REG_CHN1_ADDR = int
-DFLT_DQ_TRI_ON_PATTERN__RAW = str
-MCNTRL_TEST01_CHN1_MODE__TYPE = str
+LAST_BUF_FRAME = int
+SENS_REF_JITTER1 = float
+SENS_REF_JITTER2 = float
+MCNTRL_TILED_FRAME_SIZE__RAW = str
+MULT_SAXI_HALF_BRAM__RAW = str
 DFLT_DQS_TRI_ON_PATTERN__RAW = str
 SLEW_DQ = str
-PHASE_WIDTH__TYPE = str
-STATUS_2LSB_SHFT = int
-COLADDR_NUMBER__RAW = str
-CONTROL_ADDR_MASK = int
-SS_MOD_PERIOD = int
-WINDOW_HEIGHT = int
-MCONTR_BUF0_WR_ADDR = int
-MCNTRL_PS_STATUS_REG_ADDR__RAW = str
+SENS_GAMMA_MODE_REPET__RAW = str
+SENSOR_DATA_WIDTH = int
 MCONTR_PHY_16BIT_PATTERNS_TRI__TYPE = str
-MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__RAW = str
-CLKFBOUT_MULT = int
-MCNTRL_TILED_STATUS_CNTRL__TYPE = str
+SLEW_DQS__TYPE = str
+DIVCLK_DIVIDE_AXIHP = int
+SENSIO_ADDR_MASK = int
 SCANLINE_STARTY = int
 SCANLINE_STARTX = int
-SS_MODE = str
-MCONTR_CMD_WR_ADDR__RAW = str
-NUM_CYCLES_06 = int
-MCONTR_BUF2_WR_ADDR__RAW = str
-NUM_CYCLES_11__TYPE = str
-MCNTRL_SCANLINE_STARTADDR__TYPE = str
+FFCLK0_DIFF_TERM__TYPE = str
 WBUF_DLY_DFLT__RAW = str
+LD_DLY_CMDA__TYPE = str
+MCONTR_TOP_0BIT_REFRESH_EN = int
+CMPRS_CBIT_RUN_RST = int
+IPCLK2X_PHASE__RAW = str
+SENS_SYNC_MINBITS__TYPE = str
+SENSI2C_IOSTANDARD__TYPE = str
+REFCLK_FREQUENCY__TYPE = str
+CLKOUT_DIV_PCLK2X__TYPE = str
+MEMBRIDGE_CTRL = int
+CMPRS_TIMEOUT__TYPE = str
+MCONTR_PHY_STATUS_CNTRL = int
+SENSOR_GROUP_ADDR = int
+NUM_CYCLES_14 = int
+CMPRS_CBIT_RUN_STANDALONE__TYPE = str
+TILED_STARTX__RAW = str
+WRITE_BLOCK_OFFSET__TYPE = str
+SENS_SYNC_LATE_DFLT__TYPE = str
+BUF_CLK1X_SYNC__TYPE = str
+CAMSYNC_MODE = int
+CLK_MASK__TYPE = str
+MCNTRL_SCANLINE_STARTADDR = int
+CONTROL_ADDR = int
+DQSTRI_FIRST__TYPE = str
+MULT_SAXI_HALF_BRAM_IN__TYPE = str
+SENSI2C_CMD_SDA = int
+MCNTRL_SCANLINE_WINDOW_X0Y0 = int
+STATUS_ADDR = int
+CLKOUT_DIV_XCLK = int
+WINDOW_X0__RAW = str
+FRAME_START_ADDRESS = int
+CONTROL_ADDR__TYPE = str
+CLKFBOUT_MULT_PCLK = int
+DIVCLK_DIVIDE_SYNC = int
+CMPRS_GROUP_ADDR = int
+LOGGER_CONF_GPS_BITS__TYPE = str
+SENS_LENS_AX_MASK__TYPE = str
+HISTOGRAM_RADDR0 = int
+HISTOGRAM_RADDR1 = int
+HISTOGRAM_RADDR2 = int
+HISTOGRAM_RADDR3 = int
+MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__RAW = str
+SENS_LENS_AY_MASK__TYPE = str
+READ_BLOCK_OFFSET__TYPE = str
+CONTROL_ADDR_MASK__RAW = str
+LD_DLY_CMDA__RAW = str
+SENSI2C_STATUS_REG_REL__RAW = str
+NUM_CYCLES_18__TYPE = str
+MCNTRL_TEST01_CHN2_MODE = int
+MCNTRL_TILED_WINDOW_WH__TYPE = str
+SS_MOD_PERIOD__RAW = str
+CMPRS_NUM_AFI_CHN__RAW = str
+MULT_SAXI_ADV_RD = int
+MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str
+DLY_PHASE__TYPE = str
+MCONTR_TOP_0BIT_ADDR_MASK__TYPE = str
+MCONTR_TOP_STATUS_REG_ADDR__TYPE = str
+BUF_IPCLK_SENS2 = str
+BUF_IPCLK_SENS3 = str
+BUF_IPCLK_SENS0 = str
+BUF_IPCLK_SENS1 = str
+FFCLK0_IFD_DELAY_VALUE = str
+SLEW_CMDA__TYPE = str
+NUM_CYCLES_19__TYPE = str
+CMPRS_CORING_MODE__RAW = str
+MEMBRIDGE_ADDR = int
+CMPRS_CSAT_CR_BITS__RAW = str
+CMPRS_CBIT_FOCUS = int
+FFCLK1_CAPACITANCE__TYPE = str
+SENSOR_FIFO_DELAY = int
+MCNTRL_TEST01_CHN1_STATUS_CNTRL__TYPE = str
+WBUF_DLY_DFLT = int
+SENS_JTAG_PROG = int
+MCONTR_PHY_16BIT_WBUF_DELAY__TYPE = str
+FFCLK0_IOSTANDARD = str
+SENS_GAMMA_ADDR_MASK__RAW = str
+PHASE_WIDTH__RAW = str
+SENS_LENS_BY_MASK = int
+MEMBRIDGE_ADDR__RAW = str
+CMPRS_COLOR_SATURATION__RAW = str
+AXI_RD_ADDR_BITS = int
+CMPRS_CBIT_CMODE_JP46DC__TYPE = str
+CMPRS_STATUS_CNTRL__RAW = str
+TEST01_START_FRAME__TYPE = str
+SENSI2C_CMD_SCL_WIDTH__TYPE = str
+SENS_CTRL_ARO = int
+LOGGER_CONF_DBG_BITS__TYPE = str
+RTC_SEC_USEC_ADDR__TYPE = str
+BUF_CLK1X_XCLK__RAW = str
+WINDOW_X0__TYPE = str
+CMPRS_CBIT_QBANK_BITS = int
+MCNTRL_TEST01_CHN1_MODE = int
+DLY_CMDA = long
+SENS_GAMMA_MODE_BAYER = int
+LAST_BUF_FRAME__TYPE = str
+CMPRS_HIFREQ_REG_BASE = int
+MCONTR_ARBIT_ADDR = int
+MEMBRIDGE_CTRL__RAW = str
+CMPRS_CBIT_RUN_RST__RAW = str
+NUM_CYCLES_04__TYPE = str
+WSEL__RAW = str
+CLKOUT_DIV_XCLK__TYPE = str
+RTC_MASK__TYPE = str
+MCNTRL_TILED_PENDING_CNTR_BITS = int
+NUM_CYCLES_00__TYPE = str
+CMPRS_MASK__RAW = str
+STATUS_SEQ_SHFT__RAW = str
+MCNTRL_TEST01_MASK__RAW = str
+MCONTR_PHY_16BIT_ADDR_MASK = int
+CAMSYNC_TRIG_DELAY1__TYPE = str
+HIGH_PERFORMANCE_MODE = str
+DQTRI_LAST__RAW = str
+MCNTRL_TEST01_CHN4_STATUS_CNTRL = int
+DFLT_DQM_PATTERN = int
+SENSI2C_CMD_RUN = int
+CLKOUT_DIV_AXIHP__TYPE = str
+CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__TYPE = str
+NUM_CYCLES_04 = int
+SENS_LENS_C__TYPE = str
+MCONTR_PHY_16BIT_EXTRA__TYPE = str
+CAMSYNC_TRIGGERED_BIT__RAW = str
+CMPRS_CSAT_CR__TYPE = str
+SENS_LENS_POST_SCALE__RAW = str
+DLY_LANE1_IDELAY = long
+HIST_SAXI_NRESET__TYPE = str
+MCNTRL_SCANLINE_CHN1_ADDR__TYPE = str
+CMPRS_AFIMUX_SA_LEN__TYPE = str
+MCNTRL_SCANLINE_FRAME_SIZE__TYPE = str
+DLY_LANE0_ODELAY__TYPE = str
+SENS_LENS_FAT0_IN_MASK = int
+CMPRS_CBIT_CMODE_JP4__TYPE = str
+LOGGER_CONF_GPS = int
+MULT_SAXI_AWCACHE__RAW = str
+MCONTR_PHY_0BIT_CKE_EN = int
+CMPRS_AFIMUX_STATUS_CNTRL = int
+CMPRS_CBIT_FRAMES__RAW = str
+SLEW_DQS = str
+MCONTR_WR_MASK = int
+CMPRS_FRMT_MBCM1 = int
+MEMBRIDGE_STATUS_CNTRL__TYPE = str
+CMPRS_FRMT_LMARG = int
+FFCLK0_IBUF_DELAY_VALUE__TYPE = str
+CMPRS_TIMEOUT__RAW = str
+MEMCLK_IBUF_LOW_PWR__RAW = str
+SENS_LENS_FAT0_OUT_MASK__RAW = str
+CMPRS_STATUS_REG_INC__TYPE = str
+RTC_ADDR__TYPE = str
+SENSI2C_ABS_RADDR = int
+PXD_IOSTANDARD__RAW = str
+CMPRS_CBIT_FRAMES = int
+SENS_GAMMA_HEIGHT01__RAW = str
+CONTROL_RBACK_DEPTH__TYPE = str
+CMPRS_CBIT_CMODE_MONO1__RAW = str
+GPIO_PORTEN__TYPE = str
+CMDSEQMUX_ADDR__RAW = str
+DLY_DM_ODELAY__TYPE = str
+SENSIO_CTRL = int
+MULT_SAXI_MASK__TYPE = str
+CLKIN_PERIOD_SYNC__RAW = str
+SENS_PCLK_PERIOD = float
+SCANLINE_STARTY__RAW = str
+GPIO_ADDR = int
+SENS_SYNC_MINBITS__RAW = str
+SENS_SS_MOD_PERIOD__RAW = str
+COLADDR_NUMBER__TYPE = str
+CAMSYNC_CHN_EN_BIT__RAW = str
+LOGGER_PAGE_MSG = int
+MCONTR_LINTILE_WRITE__TYPE = str
+WINDOW_X0 = int
+INITIALIZE_OFFSET__TYPE = str
+SENSOR_FIFO_DELAY__TYPE = str
+LOGGER_CONF_IMU_BITS__TYPE = str
+IDELAY_VALUE__TYPE = str
+CMPRS_CBIT_CMODE_JP4DC__TYPE = str
+PICKLE__TYPE = str
+SENSOR_MODE_WIDTH__TYPE = str
+MCONTR_LINTILE_WRITE__RAW = str
+MCNTRL_TILED_CHN2_ADDR__RAW = str
+CLKFBOUT_MULT_XCLK__RAW = str
+CMPRS_CONTROL_REG__TYPE = str
+SENS_CTRL_ARST__TYPE = str
+CMPRS_CBIT_FOCUS__RAW = str
+CMPRS_MONO8__TYPE = str
+NUM_CYCLES_00__RAW = str
+IPCLK_PHASE__RAW = str
+SENSI2C_CTRL = int
+SENSI2C_CMD_DLY__RAW = str
+MEMCLK_IBUF_DELAY_VALUE__RAW = str
+SENS_SYNC_MULT = int
+CLK_ADDR__RAW = str
+SENSIO_CTRL__RAW = str
+MCONTR_PHY_16BIT_ADDR__TYPE = str
+CLKOUT_DIV_XCLK__RAW = str
+NUM_CYCLES_03__RAW = str
+MULT_SAXI_HALF_BRAM = int
+DLY_LANE1_DQS_WLV_IDELAY = long
+HIST_SAXI_ADDR_REL = int
+CMDFRAMESEQ_ADDR_BASE = int
+CMPRS_AFIMUX_RADDR1 = int
+CMPRS_AFIMUX_RADDR0 = int
+CMPRS_FRMT_MBCM1_BITS__RAW = str
+SENSI2C_CMD_SDA__RAW = str
+CMPRS_AFIMUX_REG_ADDR1__TYPE = str
+CMPRS_CBIT_FRAMES__TYPE = str
+MCONTR_TOP_0BIT_ADDR = int
+NUM_CYCLES_05__RAW = str
+MEMBRIDGE_MODE = int
+MCNTRL_TILED_FRAME_LAST__TYPE = str
+MCONTR_LINTILE_DIS_NEED = int
+MCONTR_CMPRS_STATUS_INC__RAW = str
+CMPRS_CBIT_CMODE_JP4DIFFHDR = int
+BUF_CLK1X_SYNC = str
+SENSI2C_CMD_RESET__TYPE = str
+CMPRS_CBIT_CMODE_JP4DIFFDIV2__RAW = str
+MCONTR_ARBIT_ADDR__TYPE = str
+CAMSYNC_TRIG_DELAY1__RAW = str
+ADDRESS_NUMBER = int
+SENS_SYNC_LATE__TYPE = str
+MCNTRL_TILED_STATUS_REG_CHN4_ADDR__TYPE = str
+GPIO_STATUS_REG_ADDR__TYPE = str
+HIST_SAXI_AWCACHE = int
+SENSI2C_CMD_RUN_PBITS = int
+CMPRS_MONO8__RAW = str
+CMPRS_AFIMUX_REG_ADDR1 = int
+CMPRS_AFIMUX_REG_ADDR0 = int
+SENS_BANDWIDTH__TYPE = str
+LD_DLY_LANE0_IDELAY__TYPE = str
+CLKFBOUT_PHASE__RAW = str
+NUM_CYCLES_08__RAW = str
+GPIO_IBUF_LOW_PWR__RAW = str
+HISTOGRAM_RADDR3__RAW = str
+NUM_XFER_BITS__TYPE = str
+HISTOGRAM_ADDR_MASK__RAW = str
+BUF_IPCLK2X_SENS2__RAW = str
+MCNTRL_TEST01_CHN4_MODE__TYPE = str
+MULT_SAXI_ADDR__TYPE = str
+CMPRS_CBIT_DCSUB__RAW = str
+SENS_LENS_AY__TYPE = str
+CMPRS_CBIT_CMODE_JP46DC = int
+CAMSYNC_MODE__RAW = str
+REFCLK_FREQUENCY = float
+STATUS_ADDR_MASK__RAW = str
+CMPRS_AFIMUX_MODE = int
+DLY_CMDA__RAW = str
+BUFFER_DEPTH32__RAW = str
+DIVCLK_DIVIDE__RAW = str
+MCNTRL_PS_CMD__RAW = str
+CAMSYNC_ADDR__RAW = str
+CLKFBOUT_MULT_SYNC__RAW = str
+MCONTR_BUF3_WR_ADDR = int
+SENS_NUM_SUBCHN__TYPE = str
+REFRESH_OFFSET__RAW = str
+MULT_SAXI_CNTRL_ADDR__TYPE = str
+MULT_SAXI_STATUS_REG__TYPE = str
+MEMCLK_IOSTANDARD__TYPE = str
+NUM_CYCLES_27__TYPE = str
+CMPRS_CBIT_BAYER_BITS = int
+PXD_SLEW__RAW = str
+MULT_SAXI_STATUS_REG = int
+CMPRS_STATUS_REG_BASE__RAW = str
+MEMCLK_IFD_DELAY_VALUE__RAW = str
+SENS_LENS_BY__RAW = str
+MCNTRL_PS_CMD__TYPE = str
+SENS_SYNC_MASK__RAW = str
+MEMBRIDGE_START64__RAW = str
+SENS_CTRL_QUADRANTS_WIDTH__TYPE = str
+SENSI2C_DRIVE = int
+NUM_CYCLES_04__RAW = str
+SENS_GAMMA_HEIGHT2__RAW = str
+SENSI2C_SLEW = str
+MULT_SAXI_BSLOG0__TYPE = str
+DQTRI_FIRST__RAW = str
+DIVCLK_DIVIDE__TYPE = str
+WBUF_DLY_WLV = int
+MCONTR_BUF3_WR_ADDR__RAW = str
+MEMBRIDGE_WIDTH64 = int
+MCNTRL_TEST01_CHN3_MODE = int
+LD_DLY_PHASE__RAW = str
+TEST_INITIAL_BURST__RAW = str
+CMPRS_CBIT_FRAMES_BITS__TYPE = str
+CMPRS_FRMT_MBCM1__RAW = str
+FFCLK0_DIFF_TERM = str
+DIVCLK_DIVIDE_PCLK__TYPE = str
+SENSOR_HIST_EN_BITS = int
+DFLT_DQS_TRI_OFF_PATTERN__RAW = str
+CMPRS_FRMT_MBRM1 = int
+CAMSYNC_SNDEN_BIT__RAW = str
+MCONTR_ARBIT_ADDR_MASK__RAW = str
+WINDOW_WIDTH__TYPE = str
+MCONTR_CMPRS_STATUS_INC__TYPE = str
+DFLT_INV_CLK_DIV = int
+DEFAULT_STATUS_MODE__TYPE = str
+HISTOGRAM_LEFT_TOP = int
+PHASE_CLK2X_PCLK = float
+GPIO_SLEW__RAW = str
+TEST01_START_FRAME__RAW = str
+CMDFRAMESEQ_ABS__RAW = str
+CMPRS_AFIMUX_SA_LEN__RAW = str
+BUF_IPCLK2X_SENS0__RAW = str
+CLKIN_PERIOD_SYNC = int
+MCONTR_BUF4_WR_ADDR__RAW = str
+CLK_STATUS__TYPE = str
+CMPRS_COLOR20__TYPE = str
+T_REFI__TYPE = str
+MCONTR_CMD_WR_ADDR__TYPE = str
+CLKFBOUT_MULT_SENSOR__RAW = str
+CMPRS_CSAT_CR_BITS = int
+HIST_SAXI_ADDR_REL__TYPE = str
+LOGGER_CONFIG__TYPE = str
+TEST01_NEXT_PAGE__RAW = str
+HIST_SAXI_MODE_ADDR_MASK__RAW = str
+CMPRS_AFIMUX_EN__RAW = str
+MCONTR_LINTILE_EXTRAPG__TYPE = str
+NUM_CYCLES_06__TYPE = str
+SCANLINE_STARTX__RAW = str
+SLEW_DQS__RAW = str
+FRAME_HEIGHT_BITS__TYPE = str
+CMPRS_CBIT_BAYER__TYPE = str
+MCONTR_PHY_0BIT_ADDR = int
+MCONTR_PHY_16BIT_EXTRA__RAW = str
+MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__TYPE = str
+MAX_TILE_HEIGHT__TYPE = str
+MCONTR_TOP_16BIT_CHN_EN__RAW = str
+FFCLK0_DQS_BIAS__TYPE = str
+HISTOGRAM_WIDTH_HEIGHT__RAW = str
+WRITELEV_OFFSET__RAW = str
+READ_PATTERN_OFFSET = int
+CLK_PHASE__TYPE = str
+SENSOR_16BIT_BIT = int
+MCNTRL_PS_STATUS_REG_ADDR = int
+SENS_CTRL_EXT_CLK__RAW = str
+LOGGER_PAGE_GPS__TYPE = str
+T_REFI = int
+HIST_CONFIRM_WRITE__TYPE = str
+HISTOGRAM_LEFT_TOP__RAW = str
+MCNTRL_SCANLINE_FRAME_FULL_WIDTH__TYPE = str
+LOGGER_STATUS_REG_ADDR = int
+CMDSEQMUX_ADDR__TYPE = str
+SENSI2C_STATUS_REG_INC = int
+SENS_JTAG_TDI__TYPE = str
+SENS_GAMMA_MODE_PAGE = int
+MCNTRL_TILED_STATUS_REG_CHN4_ADDR__RAW = str
+MCONTR_TOP_16BIT_STATUS_CNTRL__RAW = str
+MCONTR_PHY_0BIT_ADDR_MASK__RAW = str
+CAMSYNC_MASTER_BIT = int
+CLKFBOUT_MULT_REF__RAW = str
+DLY_LD_MASK__RAW = str
+CMDFRAMESEQ_RST_BIT__TYPE = str
+LD_DLY_LANE1_ODELAY = int
+NUM_CYCLES_28__RAW = str
+MCNTRL_TILED_WINDOW_X0Y0__RAW = str
+SENS_GAMMA_MODE_PAGE__TYPE = str
+CMPRS_COLOR_SATURATION__TYPE = str
+CLKIN_PERIOD_SYNC__TYPE = str
+CLKFBOUT_DIV_REF = int
+CMPRS_AFIMUX_SA_LEN = int
+SENS_CTRL_QUADRANTS_EN__TYPE = str
+MCNTRL_PS_EN_RST__RAW = str
+CMPRS_CBIT_BAYER_BITS__RAW = str
+GPIO_IOSTANDARD__RAW = str
+MEMBRIDGE_MASK__RAW = str
+CMPRS_CBIT_CMODE_JP4DIFFDIV2 = int
+RTC_SET_CORR__RAW = str
+TILED_STARTY__TYPE = str
+HIGH_PERFORMANCE_MODE__RAW = str
+DFLT_DQM_PATTERN__TYPE = str
+STATUS_ADDR__TYPE = str
+MEMCLK_IFD_DELAY_VALUE__TYPE = str
+MCONTR_PHY_0BIT_CMDA_EN = int
+CMPRS_AFIMUX_WIDTH__RAW = str
+BUF_CLK1X_PCLK2X = str
+MCNTRL_TEST01_CHN4_MODE = int
+MCNTRL_PS_STATUS_REG_ADDR__RAW = str
+MAX_TILE_WIDTH = int
+CMPRS_CBIT_RUN_STANDALONE__RAW = str
+CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = int
+DFLT_DQ_TRI_OFF_PATTERN__RAW = str
+CMPRS_CBIT_DCSUB = int
+CMPRS_CBIT_CMODE_JP4DIFF = int
+MULT_SAXI_CNTRL_MASK__TYPE = str
+SENS_PCLK_PERIOD__TYPE = str
+INITIALIZE_OFFSET__RAW = str
+CMD_DONE_BIT__RAW = str
+CMPRS_AFIMUX_RST__RAW = str
+SENSI2C_CMD_BYTES_PBITS = int
+CAMSYNC_TRIG_DST__RAW = str
+CLKIN_PERIOD_XCLK__TYPE = str
+MCONTR_TOP_16BIT_REFRESH_PERIOD__TYPE = str
+CAMSYNC_TRIG_DELAY3__TYPE = str
+FRAME_START_ADDRESS__RAW = str
+IPCLK_PHASE = float
+SENSI2C_CTRL_RADDR = int
+HIST_SAXI_MODE_ADDR_REL__RAW = str
+CLKOUT_DIV_XCLK2X__TYPE = str
+SENS_CTRL_QUADRANTS_EN = int
+MCNTRL_SCANLINE_WINDOW_WH__RAW = str
+SENSI2C_STATUS_REG_BASE = int
+BUF_IPCLK2X_SENS2 = str
+BUF_IPCLK2X_SENS3 = str
+BUF_IPCLK2X_SENS0 = str
+BUF_IPCLK2X_SENS1 = str
+LOGGER_CONFIG = int
+DLY_LD__RAW = str
+NUM_CYCLES_12__TYPE = str
+MCONTR_LINTILE_EXTRAPG = int
+MEMCLK_IOSTANDARD = str
+DLY_LANE1_ODELAY__RAW = str
+SENSI2C_IBUF_LOW_PWR__RAW = str
+SENSI2C_STATUS_REG_REL = int
+MULT_SAXI_HALF_BRAM__TYPE = str
+SENSOR_CTRL_ADDR_MASK = int
+NUM_CYCLES_16__TYPE = str
+DIVCLK_DIVIDE_XCLK__TYPE = str
+SS_MODE = str
+CMDFRAMESEQ_MASK__RAW = str
+SENS_CTRL_LD_DLY__TYPE = str
+MCONTR_TOP_16BIT_ADDR__TYPE = str
+PXD_SLEW = str
+MCONTR_CMPRS_BASE__RAW = str
+TEST01_SUSPEND = int
+NUM_FRAME_BITS = int
+LOGGER_STATUS_REG_ADDR__RAW = str
+CMPRS_CBIT_FRAMES_BITS__RAW = str
+MCNTRL_TILED_MASK__TYPE = str
+DFLT_DQ_TRI_ON_PATTERN = int
+CMPRS_FRMT_LMARG__TYPE = str
+SENSIO_JTAG = int
+DLY_LD = int
+CMPRS_CBIT_FRAMES_SINGLE = int
+SENS_SYNC_LATE = int
+CMPRS_TABLES__RAW = str
+CMDFRAMESEQ_CTRL__RAW = str
+SENSIO_DELAYS = int
+MCONTR_BUF0_RD_ADDR__TYPE = str
+CLKIN_PERIOD_XCLK__RAW = str
+DLY_LANE0_IDELAY__TYPE = str
+MCNTRL_PS_ADDR__TYPE = str
+WINDOW_WIDTH__RAW = str
+MCONTR_PHY_16BIT_ADDR__RAW = str
+SENS_CTRL_MRST__RAW = str
+BUF_CLK1X_XCLK = str
+SENS_GAMMA_HEIGHT2__TYPE = str
+IPCLK2X_PHASE__TYPE = str
+MCNTRL_SCANLINE_CHN1_ADDR = int
+MULT_SAXI_HALF_BRAM_IN = int
+CMDFRAMESEQ_ADDR_INC__RAW = str
+IPCLK_PHASE__TYPE = str
+NUM_CYCLES_18__RAW = str
+NUM_CYCLES_13__TYPE = str
+MCONTR_WR_MASK__RAW = str
+MCNTRL_TILED_WINDOW_STARTXY = int
+MCONTR_TOP_0BIT_MCONTR_EN = int
+SENS_LENS_BX__TYPE = str
+LOGGER_CONF_GPS__RAW = str
+SENS_GAMMA_MODE_TRIG__RAW = str
+RTC_SET_CORR = int
+CMPRS_CBIT_FOCUS__TYPE = str
+CMPRS_NUM_AFI_CHN__TYPE = str
+CMPRS_GROUP_ADDR__RAW = str
+SENS_LENS_AX__RAW = str
+CMPRS_JP4DIFF__RAW = str
+SENS_SS_MODE__RAW = str
+CAMSYNC_SNDEN_BIT__TYPE = str
+CMPRS_CBIT_CMODE__TYPE = str
+LOGGER_STATUS_MASK = int
+DFLT_DQ_TRI_ON_PATTERN__RAW = str
+CONTROL_ADDR_MASK = int
+LOGGER_PERIOD = int
+MCONTR_BUF0_WR_ADDR = int
+SENSI2C_CMD_SCL_WIDTH__RAW = str
+LOGGER_STATUS_MASK__RAW = str
+RTC_ADDR__RAW = str
+CMPRS_CBIT_FOCUS_BITS__RAW = str
+CMDFRAMESEQ_RUN_BIT__TYPE = str
+MCNTRL_TILED_STATUS_CNTRL__TYPE = str
+SENSI2C_CTRL__RAW = str
+MCONTR_BUF2_WR_ADDR__RAW = str
+MULT_SAXI_BSLOG0 = int
+MULT_SAXI_BSLOG1 = int
+MULT_SAXI_BSLOG2 = int
+MULT_SAXI_BSLOG3 = int
+SENS_SS_MOD_PERIOD = int
 DQSTRI_FIRST = int
-CONTROL_RBACK_DEPTH__RAW = str
-DLY_CMDA_ODELAY__TYPE = str
-LD_DLY_CMDA = int
-DLY_SET__RAW = str
-DFLT_REFRESH_ADDR__RAW = str
-DFLT_DQ_TRI_OFF_PATTERN__TYPE = str
+SENS_REF_JITTER2__RAW = str
+SCANLINE_EXTRA_PAGES__RAW = str
+CMDSEQMUX_STATUS__RAW = str
 MCONTR_PHY_0BIT_SDRST_ACT__RAW = str
-REFCLK_FREQUENCY__TYPE = str
-MCNTRL_SCANLINE_MASK = int
-TILE_HEIGHT = int
-AXI_WR_ADDR_BITS__TYPE = str
+CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__RAW = str
+DIVCLK_DIVIDE_PCLK = int
 MCNTRL_PS_MASK = int
-MEMBRIDGE_CTRL = int
+SENSI2C_STATUS__TYPE = str
+CMPRS_CSAT_CB_BITS = int
+SENSI2C_IOSTANDARD = str
+GPIO_IOSTANDARD = str
+MCNTRL_SCANLINE_WINDOW_X0Y0__RAW = str
+SENS_SYNC_MINPER__TYPE = str
+SENSI2C_CTRL_RADDR__RAW = str
+SENS_SYNC_LATE_DFLT__RAW = str
+MCONTR_LINTILE_DIS_NEED__RAW = str
+SENS_HIGH_PERFORMANCE_MODE = str
+CAMSYNC_MASTER_BIT__RAW = str
+MEMBRIDGE_STATUS_CNTRL = int
 MCNTRL_TEST01_STATUS_REG_CHN3_ADDR = int
-COLADDR_NUMBER = int
-MCONTR_PHY_STATUS_CNTRL = int
-MCNTRL_PS_ADDR__RAW = str
-MCONTR_BUF2_RD_ADDR__TYPE = str
-CLKFBOUT_DIV_AXIHP__RAW = str
-TILED_STARTX__RAW = str
-WRITE_BLOCK_OFFSET__TYPE = str
-STATUS_ADDR_MASK = int
-MCNTRL_TEST01_ADDR__TYPE = str
-LD_DLY_CMDA__TYPE = str
-TEST01_NEXT_PAGE = int
-CLKFBOUT_MULT__RAW = str
+GPIO_SET_PINS__TYPE = str
 CONTROL_RBACK_ADDR__TYPE = str
-MCNTRL_TEST01_CHN1_STATUS_CNTRL = int
-IBUF_LOW_PWR = str
-CONTROL_ADDR = int
-DQSTRI_FIRST__TYPE = str
+CMPRS_CORING_BITS__RAW = str
+CMDFRAMESEQ_RST_BIT = int
+CAMSYNC_SNDEN_BIT = int
 DQSTRI_FIRST__RAW = str
-CMD_DONE_BIT = int
-NUM_CYCLES_10__TYPE = str
-MCNTRL_SCANLINE_WINDOW_X0Y0 = int
-NEWPAR__TYPE = str
-STATUS_ADDR = int
-LD_DLY_LANE0_ODELAY__RAW = str
-MCONTR_BUF0_RD_ADDR__RAW = str
-MCNTRL_TILED_STARTADDR__RAW = str
-WINDOW_X0__RAW = str
-AXI_RD_ADDR_BITS = int
-MCONTR_BUF2_RD_ADDR__RAW = str
-FRAME_START_ADDRESS = int
-MCNTRL_SCANLINE_PENDING_CNTR_BITS__TYPE = str
-CONTROL_ADDR__TYPE = str
-MCNTRL_TEST01_CHN3_STATUS_CNTRL__RAW = str
-WINDOW_Y0 = int
-DLY_DQS_IDELAY__RAW = str
+SENSI2C_CTRL_MASK__TYPE = str
+SENS_LENS_SCALES__TYPE = str
+SENS_LENS_COEFF__TYPE = str
+LOGGER_STATUS__RAW = str
+SENS_JTAG_TMS__RAW = str
+FFCLK0_IBUF_LOW_PWR__RAW = str
+SENS_CTRL_MRST = int
+MCNTRL_SCANLINE_FRAME_LAST__TYPE = str
+MCONTR_SENS_STATUS_BASE__RAW = str
 MCNTRL_TEST01_CHN3_MODE__TYPE = str
-MCNTRL_SCANLINE_WINDOW_X0Y0__RAW = str
-MCONTR_BUF4_WR_ADDR = int
-DLY_DQS_IDELAY__TYPE = str
+MCONTR_BUF2_RD_ADDR__TYPE = str
+SENS_SYNC_RADDR__RAW = str
 MCNTRL_TEST01_CHN2_STATUS_CNTRL = int
-CLK_PHASE = float
-MCNTRL_TILED_FRAME_PAGE_RESET = int
-MCONTR_TOP_16BIT_ADDR_MASK = int
-DLY_LANE1_DQS_WLV_IDELAY__RAW = str
-READ_BLOCK_OFFSET__TYPE = str
-CONTROL_ADDR_MASK__RAW = str
-LD_DLY_CMDA__RAW = str
-MCONTR_BUF0_WR_ADDR__RAW = str
-LD_DLY_LANE1_ODELAY__RAW = str
-MCNTRL_TILED_WINDOW_WH__TYPE = str
+CLKFBOUT_PHASE_SENSOR__TYPE = str
+SENSOR_HIST_NRST_BITS__TYPE = str
+GPIO_PORTEN = int
+RTC_STATUS_REG_ADDR__TYPE = str
+SENS_JTAG_TCK__TYPE = str
+MCNTRL_TILED_FRAME_SIZE__TYPE = str
+CMPRS_AFIMUX_REG_ADDR1__RAW = str
+SENS_LENS_COEFF = int
+LOGGER_BIT_DURATION__RAW = str
 MCONTR_WR_MASK__TYPE = str
-SS_MOD_PERIOD__RAW = str
-MEMBRIDGE_WIDTH64__TYPE = str
-MAX_TILE_HEIGHT = int
-AFI_LO_ADDR64__RAW = str
-MCNTRL_SCANLINE_STARTADDR__RAW = str
-MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str
+SENS_LENS_C__RAW = str
+CMDFRAMESEQ_ADDR_BASE__TYPE = str
+SENS_GAMMA_HEIGHT01 = int
+RTC_SET_SEC__RAW = str
 MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__TYPE = str
 SS_MODE__RAW = str
-DLY_PHASE__TYPE = str
-MCONTR_TOP_0BIT_ADDR_MASK__TYPE = str
-MCONTR_TOP_STATUS_REG_ADDR__TYPE = str
-MCONTR_PHY_16BIT_WBUF_DELAY = int
+MCNTRL_SCANLINE_CHN3_ADDR = int
+NUM_CYCLES_26__RAW = str
 DEFAULT_STATUS_MODE__RAW = str
-DLY_LANE1_DQS_WLV_IDELAY__TYPE = str
-TILE_HEIGHT__RAW = str
-FRAME_WIDTH_BITS = int
-MCNTRL_TILED_STATUS_REG_CHN2_ADDR__TYPE = str
-MEMBRIDGE_MODE__RAW = str
-MEMBRIDGE_STATUS_CNTRL = int
-SLEW_CMDA__TYPE = str
-MCONTR_RD_MASK__TYPE = str
-READ_BLOCK_OFFSET__RAW = str
+MCONTR_LINTILE_KEEP_OPEN__RAW = str
+CLKOUT_DIV_SYNC__TYPE = str
+CMDFRAMESEQ_RST_BIT__RAW = str
+SENSIO_RADDR__RAW = str
+MCONTR_SENS_BASE__TYPE = str
+MCONTR_PHY_0BIT_ADDR__RAW = str
 MCLK_PHASE = float
-SLEW_DQ__RAW = str
-FRAME_HEIGHT_BITS__TYPE = str
-DLY_DQS_IDELAY = long
-MCONTR_BUF3_RD_ADDR__TYPE = str
-MEMBRIDGE_ADDR = int
-DLY_DQ_ODELAY__TYPE = str
+SENSI2C_SLEW__RAW = str
 MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
-MCNTRL_TEST01_STATUS_REG_CHN4_ADDR__RAW = str
-SLEW_CLK__RAW = str
-MCNTRL_TEST01_CHN1_STATUS_CNTRL__TYPE = str
-WBUF_DLY_DFLT = int
-MCONTR_PHY_16BIT_WBUF_DELAY__TYPE = str
+CMDSEQMUX_MASK = int
+BUF_CLK1X_XCLK__TYPE = str
+SENSI2C_CMD_DLY__TYPE = str
+MEMCLK_CAPACITANCE__RAW = str
 DQTRI_FIRST = int
-MCONTR_BUF2_WR_ADDR = int
-AXI_WR_ADDR_BITS = int
-CONTROL_RBACK_DEPTH = int
+DLY_LANE0_DQS_WLV_IDELAY__TYPE = str
+CAMSYNC_TRIG_DELAY0 = int
+CAMSYNC_TRIG_DELAY1 = int
 MCNTRL_SCANLINE_STATUS_CNTRL__RAW = str
-SCANLINE_EXTRA_PAGES__TYPE = str
-PHASE_WIDTH__RAW = str
-MEMBRIDGE_START64 = int
-MEMBRIDGE_SIZE64__RAW = str
-MAX_TILE_HEIGHT__RAW = str
-DFLT_DQS_PATTERN = int
+CAMSYNC_TRIG_DELAY3 = int
+MCONTR_SENS_STATUS_INC = int
+CAMSYNC_TRIGGERED_BIT__TYPE = str
+SENS_GAMMA_MODE_TRIG__TYPE = str
 DLY_LANE0_DQS_WLV_IDELAY__RAW = str
-MCNTRL_TEST01_CHN2_MODE__TYPE = str
-DLY_LANE1_IDELAY__RAW = str
-MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str
-SLEW_CLK = str
-LD_DLY_LANE1_ODELAY__TYPE = str
-MCNTRL_PS_STATUS_CNTRL = int
-TEST01_START_FRAME__TYPE = str
-SS_MODE__TYPE = str
+CMPRS_FRMT_LMARG_BITS__RAW = str
+MEMBRIDGE_ADDR__TYPE = str
+LAST_FRAME_BITS = int
+SENSOR_FIFO_2DEPTH__RAW = str
+CMPRS_COLOR20__RAW = str
 MCONTR_TOP_16BIT_REFRESH_ADDRESS__RAW = str
 WINDOW_Y0__TYPE = str
-MCONTR_PHY_0BIT_DLY_RST__TYPE = str
-CLKFBOUT_MULT_AXIHP__RAW = str
-BUFFER_DEPTH32__TYPE = str
+SENSI2C_CTRL__TYPE = str
+LOGGER_PAGE_MSG__RAW = str
 MCONTR_TOP_16BIT_STATUS_CNTRL = int
-MCONTR_BUF4_RD_ADDR__RAW = str
-WINDOW_X0__TYPE = str
-T_RFC__TYPE = str
-WINDOW_WIDTH = int
-DQSTRI_LAST = int
-MCNTRL_TEST01_CHN1_MODE = int
-DFLT_CHN_EN__RAW = str
+CMPRS_CBIT_CMODE_MONO4__RAW = str
+MULT_SAXI_MASK = int
 MCNTRL_SCANLINE_WINDOW_STARTXY__TYPE = str
-DLY_CMDA = long
+CMDFRAMESEQ_DEPTH__TYPE = str
 DLY_LANE0_IDELAY__RAW = str
-MCONTR_ARBIT_ADDR = int
-MCNTRL_TEST01_CHN1_STATUS_CNTRL__RAW = str
-MEMBRIDGE_CTRL__RAW = str
+HISTOGRAM_RADDR1__RAW = str
 CLKFBOUT_DIV_REF__TYPE = str
-NUM_CYCLES_04__TYPE = str
-WSEL__RAW = str
+MCONTR_LINTILE_EXTRAPG_BITS__RAW = str
 MCNTRL_SCANLINE_MODE__RAW = str
-READ_PATTERN_OFFSET__TYPE = str
-MCNTRL_TILED_PENDING_CNTR_BITS = int
-NUM_CYCLES_00__TYPE = str
-MAX_TILE_WIDTH__TYPE = str
-MCONTR_CMD_WR_ADDR = int
+LOGGER_BIT_HALF_PERIOD__TYPE = str
+FRAME_START_ADDRESS_INC__RAW = str
 MCONTR_BUF3_RD_ADDR__RAW = str
 CLKIN_PERIOD = int
-DLY_LANE1_ODELAY__TYPE = str
 RSEL__TYPE = str
-MCNTRL_TEST01_MASK__RAW = str
-MCONTR_PHY_16BIT_ADDR_MASK = int
-MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__TYPE = str
-HIGH_PERFORMANCE_MODE = str
+CMDFRAMESEQ_ADDR_INC__TYPE = str
+BUF_CLK1X_XCLK2X__TYPE = str
+LOGGER_CONF_GPS_BITS = int
 NUM_CYCLES_07__RAW = str
-DQTRI_LAST__RAW = str
-TILE_WIDTH = int
 CLKFBOUT_PHASE = float
-DFLT_DQM_PATTERN = int
-MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
-NUM_XFER_BITS = int
-MCNTRL_TEST01_STATUS_REG_CHN2_ADDR = int
-DLY_DQS_ODELAY__TYPE = str
+SENS_GAMMA_ADDR_DATA = int
+SENS_GAMMA_ADDR_DATA__TYPE = str
+CAMSYNC_DELAY__TYPE = str
 DFLT_REFRESH_PERIOD__RAW = str
-DLY_LANE0_ODELAY__RAW = str
-MCONTR_BUF3_WR_ADDR__TYPE = str
-SCANLINE_STARTX__TYPE = str
+SENS_REF_JITTER1__TYPE = str
+SENS_LENS_RADDR__RAW = str
 MCONTR_PHY_0BIT_DCI_RST__TYPE = str
 MAX_TILE_WIDTH__RAW = str
-MCNTRL_SCANLINE_WINDOW_WH__TYPE = str
-FRAME_FULL_WIDTH__RAW = str
+FFCLK1_DQS_BIAS = str
+MCONTR_LINTILE_WRITE = int
 TILE_VSTEP__TYPE = str
 MCONTR_PHY_STATUS_CNTRL__RAW = str
-MCNTRL_TILED_WINDOW_WH__RAW = str
-MCONTR_PHY_16BIT_EXTRA__TYPE = str
 DLY_LANE0_DQS_WLV_IDELAY = long
 MCNTRL_SCANLINE_STATUS_CNTRL = int
-DLY_DM_ODELAY__RAW = str
-DLY_LANE1_IDELAY = long
+CMDSEQMUX_MASK__TYPE = str
+TILED_STARTY__RAW = str
 NUM_CYCLES_01__RAW = str
-MCONTR_PHY_STATUS_CNTRL__TYPE = str
 WINDOW_HEIGHT__RAW = str
-MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__RAW = str
-NUM_CYCLES_02 = int
-CHNBUF_READ_LATENCY__TYPE = str
-NUM_CYCLES_LOW_BIT__TYPE = str
-FRAME_WIDTH_BITS__RAW = str
-ADDRESS_NUMBER__RAW = str
-STATUS_PSHIFTER_RDY_MASK__TYPE = str
+GPIO_IBUF_LOW_PWR = str
+DQTRI_LAST = int
+SENSI2C_CTRL_MASK = int
+PHASE_CLK2X_PCLK__RAW = str
 MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__TYPE = str
 MCONTR_TOP_0BIT_ADDR__RAW = str
-TEST_INITIAL_BURST__TYPE = str
-CMD_PAUSE_BITS__RAW = str
-MCNTRL_PS_CMD__RAW = str
-MCONTR_BUF3_WR_ADDR = int
-NEWPAR = int
-MCNTRL_PS_MASK__RAW = str
+LOGGER_CONF_DBG__TYPE = str
 AFI_SIZE64__RAW = str
-MCONTR_PHY_0BIT_CKE_EN = int
-BUFFER_DEPTH32 = int
-MCNTRL_TILED_CHN2_ADDR__TYPE = str
-SLEW_DQS = str
-DFLT_REFRESH_ADDR = int
-MCONTR_WR_MASK = int
-MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR = int
-TEST01_SUSPEND__RAW = str
-MEMBRIDGE_STATUS_CNTRL__TYPE = str
-T_REFI__TYPE = str
-STATUS_DEPTH__RAW = str
+STATUS_PSHIFTER_RDY_MASK = int
+SENS_LENS_C_MASK__TYPE = str
+MCNTRL_SCANLINE_FRAME_LAST__RAW = str
+CMPRS_CSAT_CB__RAW = str
+SENS_PHASE_WIDTH__RAW = str
+SENS_REF_JITTER2__TYPE = str
+FFCLK0_IBUF_LOW_PWR = str
 DFLT_DQ_TRI_ON_PATTERN__TYPE = str
-MCONTR_TOP_0BIT_ADDR_MASK__RAW = str
-TEST01_START_FRAME = int
+CMPRS_AFIMUX_MODE__TYPE = str
 DQTRI_FIRST__TYPE = str
-MCONTR_PHY_0BIT_ADDR_MASK__TYPE = str
-CONTROL_RBACK_DEPTH__TYPE = str
+MCNTRL_SCANLINE_FRAME_SIZE__RAW = str
+CMPRS_CBIT_CMODE_BITS = int
+MULT_SAXI_CNTRL_ADDR__RAW = str
+FFCLK1_IOSTANDARD__TYPE = str
+CAMSYNC_TRIG_DELAY2__RAW = str
+MCNTRL_TEST01_CHN4_MODE__RAW = str
 DLY_CMDA__TYPE = str
 CLKFBOUT_MULT__TYPE = str
-WBUF_DLY_DFLT__TYPE = str
 MCONTR_PHY_0BIT_CMDA_EN__RAW = str
-STATUS_SEQ_SHFT__RAW = str
-DLY_DM_ODELAY__TYPE = str
-MCNTRL_TEST01_CHN4_MODE__RAW = str
-MCONTR_PHY_0BIT_DCI_RST__RAW = str
-REFCLK_FREQUENCY__RAW = str
-MCONTR_RD_MASK__RAW = str
-MCNTRL_TEST01_STATUS_REG_CHN3_ADDR__TYPE = str
+IDELAY_VALUE = int
+DQSTRI_LAST__TYPE = str
+HISTOGRAM_RADDR2__TYPE = str
+SENS_JTAG_PROG__TYPE = str
 TILE_VSTEP = int
 DFLT_DQS_TRI_OFF_PATTERN__TYPE = str
-SS_EN__TYPE = str
+CAMSYNC_EN_BIT__RAW = str
+BUF_CLK1X_AXIHP = str
+SENSIO_WIDTH = int
 MCONTR_PHY_0BIT_DLY_RST__RAW = str
-SCANLINE_STARTY__RAW = str
-FRAME_FULL_WIDTH__TYPE = str
-WRITE_BLOCK_OFFSET = int
-MEMBRIDGE_MODE__TYPE = str
-COLADDR_NUMBER__TYPE = str
-MCNTRL_SCANLINE_FRAME_FULL_WIDTH = int
-TEST01_SUSPEND__TYPE = str
-PICKLE = str
-AFI_SIZE64__TYPE = str
+BUF_CLK1X_PCLK2X__RAW = str
+SENSI2C_CMD_RESET__RAW = str
+SENSI2C_ADDR_MASK__RAW = str
+SENS_HIGH_PERFORMANCE_MODE__TYPE = str
+MCONTR_LINTILE_KEEP_OPEN__TYPE = str
 NUM_CYCLES_15__RAW = str
-MCONTR_PHY_0BIT_ADDR_MASK = int
-MCNTRL_TILED_TILE_WHS__TYPE = str
 DLY_DQ_IDELAY = long
-WINDOW_X0 = int
-DFLT_WBUF_DELAY__TYPE = str
-INITIALIZE_OFFSET__TYPE = str
-LD_DLY_LANE0_ODELAY = int
-SCANLINE_EXTRA_PAGES = int
-READ_PATTERN_OFFSET__RAW = str
+MCNTRL_TEST01_ADDR__TYPE = str
+CMPRS_STATUS_REG_BASE = int
+MCONTR_LINTILE_NRESET = int
+CMPRS_CBIT_RUN_BITS = int
+MEMCLK_IFD_DELAY_VALUE = str
+SENS_LENS_AY_MASK = int
+BUF_IPCLK2X_SENS3__RAW = str
 MCNTRL_SCANLINE_CHN1_ADDR__RAW = str
 MEMBRIDGE_LEN64 = int
-MEMBRIDGE_SIZE64 = int
-PICKLE__TYPE = str
-MCONTR_PHY_0BIT_CKE_EN__TYPE = str
-AFI_LO_ADDR64 = int
-RSEL = int
-MCNTRL_TILED_MODE__TYPE = str
-DIVCLK_DIVIDE = int
-NUM_CYCLES_07__TYPE = str
+SENSOR_NUM_HISTOGRAM__TYPE = str
+HIST_SAXI_EN = int
+RTC_SET_SEC = int
+MCONTR_LINTILE_SINGLE__TYPE = str
 DLY_DQ_IDELAY__RAW = str
-AXI_RD_ADDR_BITS__TYPE = str
-REF_JITTER1 = float
-CONTROL_ADDR__RAW = str
-TILED_STARTY__RAW = str
-NUM_CYCLES_00__RAW = str
+SENSOR_CTRL_RADDR__RAW = str
+CMPRS_MONO16 = int
+CMPRS_CSAT_CB__TYPE = str
+SENSIO_STATUS__RAW = str
+CLKIN_PERIOD_AXIHP__RAW = str
+SENS_LENS_BX_MASK = int
 DLY_DQ_ODELAY__RAW = str
-MCONTR_TOP_16BIT_ADDR_MASK__RAW = str
 MCNTRL_TILED_PENDING_CNTR_BITS__RAW = str
-NUM_CYCLES_14__TYPE = str
-TILED_EXTRA_PAGES = int
-MCNTRL_PS_EN_RST__RAW = str
-MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__RAW = str
-CLK_PHASE__RAW = str
-MCONTR_PHY_0BIT_DLY_RST = int
-MCONTR_PHY_16BIT_ADDR__TYPE = str
-TILED_STARTY = int
-TILED_STARTX = int
-MEMBRIDGE_MASK__TYPE = str
-AXI_WR_ADDR_BITS__RAW = str
-MCONTR_BUF3_RD_ADDR = int
-DFLT_REFRESH_PERIOD__TYPE = str
-MCNTRL_TILED_FRAME_FULL_WIDTH__RAW = str
-MCNTRL_TILED_MASK = int
-NUM_CYCLES_03__RAW = str
-CLKFBOUT_PHASE__TYPE = str
-MCONTR_PHY_16BIT_ADDR_MASK__RAW = str
-DLY_LANE1_DQS_WLV_IDELAY = long
-MCNTRL_TILED_WINDOW_WH = int
-NUM_CYCLES_06__RAW = str
-MCNTRL_TILED_WINDOW_X0Y0__TYPE = str
-NUM_XFER_BITS__RAW = str
-MCNTRL_TILED_WINDOW_STARTXY__RAW = str
-CONTROL_RBACK_ADDR = int
-DLY_CMDA_ODELAY = long
-MCONTR_TOP_0BIT_ADDR = int
-MEMBRIDGE_LO_ADDR64__TYPE = str
+CMPRS_CORING_BITS = int
+CMDFRAMESEQ_MASK__TYPE = str
+FFCLK1_IOSTANDARD = str
+CLK_PHASE__RAW = str
+MCONTR_PHY_0BIT_DLY_RST = int
+GPIO_MASK__TYPE = str
+MULT_SAXI_BSLOG2__TYPE = str
+TILED_STARTX = int
+MEMBRIDGE_MASK__TYPE = str
+FFCLK1_DQS_BIAS__RAW = str
+SENS_GAMMA_MODE_EN = int
+MCONTR_BUF3_RD_ADDR = int
+NUM_CYCLES_28__TYPE = str
+NUM_CYCLES_31__TYPE = str
+SENSI2C_CMD_BYTES__RAW = str
+CMPRS_CBIT_FRAMES_SINGLE__TYPE = str
+BUF_IPCLK_SENS2__TYPE = str
+SENS_GAMMA_BUFFER = int
+CMDFRAMESEQ_ABS__TYPE = str
+NUM_CYCLES_06__RAW = str
+SENS_JTAG_TDI = int
+CLKFBOUT_MULT_AXIHP = int
+CAMSYNC_CHN_EN_BIT = int
+SENSIO_STATUS_REG_REL__TYPE = str
 MCNTRL_SCANLINE_MODE = int
-MCONTR_ARBIT_ADDR_MASK = int
-NUM_CYCLES_05__RAW = str
-MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR = int
+DLY_LANE0_IDELAY = long
 MCNTRL_PS_CMD = int
-MEMBRIDGE_MODE = int
+MCNTRL_SCANLINE_CHN3_ADDR__TYPE = str
 STATUS_2LSB_SHFT__RAW = str
-WBUF_DLY_WLV__RAW = str
-MCONTR_TOP_0BIT_REFRESH_EN = int
-MCNTRL_TILED_STATUS_REG_CHN4_ADDR = int
+STATUS_MSB_RSHFT__RAW = str
 SLEW_CMDA__RAW = str
-MCNTRL_TEST01_CHN2_MODE__RAW = str
-CLKFBOUT_MULT_AXIHP__TYPE = str
-LD_DLY_PHASE__RAW = str
+GPIO_SLEW = str
 MCONTR_TOP_STATUS_REG_ADDR__RAW = str
-MCONTR_ARBIT_ADDR__TYPE = str
 DFLT_DQS_TRI_ON_PATTERN = int
+SENSI2C_REL_RADDR = int
 MCNTRL_TEST01_STATUS_REG_CHN3_ADDR__RAW = str
 DFLT_CHN_EN = int
-LD_DLY_LANE0_IDELAY = int
+GPIO_STATUS_REG_ADDR__RAW = str
 DLY_DQS_ODELAY = long
-ADDRESS_NUMBER = int
-NUM_CYCLES_01__TYPE = str
-MCLK_PHASE__TYPE = str
-MCNTRL_TILED_TILE_WHS__RAW = str
-MCNTRL_TILED_STATUS_REG_CHN4_ADDR__TYPE = str
-DQTRI_LAST = int
-CMD_PAUSE_BITS__TYPE = str
-MCONTR_BUF2_RD_ADDR = int
-MCONTR_BUF2_WR_ADDR__TYPE = str
-NUM_CYCLES_02__TYPE = str
-DQTRI_LAST__TYPE = str
-TEST_INITIAL_BURST = int
-FRAME_HEIGHT_BITS__RAW = str
-MCNTRL_TILED_STARTADDR = int
+SENSOR_CHN_EN_BIT__RAW = str
+SENS_SS_MODE__TYPE = str
+CAMSYNC_TRIG_SRC__TYPE = str
+LOGGER_CONF_IMU__TYPE = str
+PHASE_CLK2X_XCLK__RAW = str
+SS_EN = str
+CLKFBOUT_MULT_XCLK = int
 WINDOW_HEIGHT__TYPE = str
-MCNTRL_TILED_FRAME_FULL_WIDTH = int
-TILE_HEIGHT__TYPE = str
-CLKFBOUT_DIV_AXIHP__TYPE = str
-MCNTRL_TILED_CHN4_ADDR__TYPE = str
-FRAME_HEIGHT_BITS = int
+IBUF_LOW_PWR__TYPE = str
+FFCLK1_IBUF_LOW_PWR__TYPE = str
+CLK_DIV_PHASE = float
+MCNTRL_TEST01_CHN4_STATUS_CNTRL__RAW = str
 MCONTR_PHY_16BIT_ADDR_MASK__TYPE = str
-SS_EN__RAW = str
-LD_DLY_LANE0_IDELAY__TYPE = str
-MCONTR_PHY_0BIT_ADDR__RAW = str
-CLKFBOUT_PHASE__RAW = str
+SENS_CTRL_ARO__RAW = str
+BUF_IPCLK2X_SENS0__TYPE = str
 MCONTR_PHY_0BIT_DLY_SET__RAW = str
-NUM_CYCLES_08__RAW = str
-DFLT_DQ_TRI_OFF_PATTERN = int
+CLKIN_PERIOD_XCLK = int
 NUM_CYCLES_11__RAW = str
-MCNTRL_PS_STATUS_CNTRL__RAW = str
-PHASE_WIDTH = int
-SDCLK_PHASE = float
-DFLT_DQS_PATTERN__RAW = str
-MCNTRL_TEST01_CHN4_MODE__TYPE = str
-SLEW_CMDA = str
-REFCLK_FREQUENCY = float
-MCNTRL_PS_STATUS_CNTRL__TYPE = str
-MCONTR_PHY_16BIT_ADDR = int
-REF_JITTER1__TYPE = str
-MCNTRL_SCANLINE_MODE__TYPE = str
-STATUS_ADDR_MASK__RAW = str
-MCONTR_PHY_16BIT_PATTERNS_TRI = int
-DLY_CMDA__RAW = str
-MEMBRIDGE_MASK = int
+FFCLK1_CAPACITANCE__RAW = str
+SENSI2C_DRIVE__RAW = str
+CMPRS_CBIT_CMODE_MONO1__TYPE = str
+SENSOR_CTRL_ADDR_MASK__RAW = str
+DFLT_CHN_EN__RAW = str
+NUM_CYCLES_LOW_BIT = int
 READ_BLOCK_OFFSET = int
-T_REFI__RAW = str
-STATUS_MSB_RSHFT = int
-BUFFER_DEPTH32__RAW = str
 RSEL__RAW = str
-CLKIN_PERIOD__TYPE = str
-DIVCLK_DIVIDE__RAW = str
-DLY_LANE0_ODELAY__TYPE = str
-DLY_LANE0_IDELAY = long
+GPIO_DRIVE__TYPE = str
 SDCLK_PHASE__TYPE = str
+NUM_CYCLES_31__RAW = str
+SENSI2C_IBUF_LOW_PWR__TYPE = str
+SENS_LENS_POST_SCALE_MASK__TYPE = str
 SCANLINE_STARTY__TYPE = str
-REFRESH_OFFSET__RAW = str
-MCNTRL_TEST01_CHN2_MODE = int
-MCNTRL_SCANLINE_CHN3_ADDR__TYPE = str
-MCNTRL_TEST01_CHN1_MODE__RAW = str
-MCONTR_BUF4_RD_ADDR__TYPE = str
-LD_DLY_LANE0_ODELAY__TYPE = str
-MCONTR_TOP_16BIT_ADDR__RAW = str
+SENS_LENS_SCALES_MASK = int
+LOGGER_PAGE_MSG__TYPE = str
+CAMSYNC_MASK__RAW = str
+SENSOR_BASE_INC__TYPE = str
+RTC_MHZ__TYPE = str
+MEMBRIDGE_START64 = int
 MEMBRIDGE_LO_ADDR64 = int
-MCNTRL_SCANLINE_PENDING_CNTR_BITS = int
-DFLT_DQS_TRI_ON_PATTERN__TYPE = str
-MCONTR_PHY_0BIT_SDRST_ACT__TYPE = str
-TILED_KEEP_OPEN__RAW = str
-MCNTRL_SCANLINE_STARTADDR = int
-MEMBRIDGE_WIDTH64__RAW = str
-MCONTR_TOP_0BIT_ADDR__TYPE = str
+CMPRS_AFIMUX_EN__TYPE = str
+CMPRS_BASE_INC__TYPE = str
+NUM_FRAME_BITS__TYPE = str
+CLKFBOUT_MULT_SENSOR__TYPE = str
 CLKFBOUT_MULT_REF__TYPE = str
-MCNTRL_PS_CMD__TYPE = str
-MEMBRIDGE_START64__RAW = str
-STATUS_MSB_RSHFT__RAW = str
-STATUS_PSHIFTER_RDY_MASK = int
-NUM_CYCLES_04__RAW = str
-MCNTRL_TEST01_MASK__TYPE = str
-STATUS_DEPTH = int
-MCNTRL_SCANLINE_WINDOW_STARTXY__RAW = str
+SENSI2C_CTRL_MASK__RAW = str
+CLK_CNTRL = int
+BUF_CLK1X_AXIHP__RAW = str
+LOGGER_ADDR__TYPE = str
 NUM_CYCLES_15__TYPE = str
 MCNTRL_TILED_MODE__RAW = str
-DLY_SET = int
-MCNTRL_TILED_CHN2_ADDR__RAW = str
-DQTRI_FIRST__RAW = str
-DIVCLK_DIVIDE__TYPE = str
+CLKOUT_DIV_AXIHP__RAW = str
+SENS_PCLK_PERIOD__RAW = str
+NUM_CYCLES_23__TYPE = str
+MCNTRL_TILED_MODE__TYPE = str
 MCONTR_TOP_0BIT_MCONTR_EN__RAW = str
-MCNTRL_SCANLINE_FRAME_PAGE_RESET__TYPE = str
-VERBOSE__RAW = str
-WBUF_DLY_WLV = int
-MCONTR_BUF3_WR_ADDR__RAW = str
-MEMBRIDGE_LO_ADDR64__RAW = str
-MEMBRIDGE_WIDTH64 = int
-MCNTRL_TEST01_CHN3_MODE = int
+RTC_SET_STATUS__RAW = str
+SENS_CTRL_QUADRANTS = int
 LD_DLY_PHASE__TYPE = str
-MCONTR_PHY_0BIT_ADDR__TYPE = str
-TEST_INITIAL_BURST__RAW = str
-MCNTRL_SCANLINE_FRAME_PAGE_RESET__RAW = str
-MCONTR_ARBIT_ADDR_MASK__RAW = str
+MEMCLK_IBUF_DELAY_VALUE = str
+MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__TYPE = str
+CMDSEQMUX_MASK__RAW = str
 DFLT_WBUF_DELAY = int
-DLY_DQ_ODELAY = long
 CONTROL_RBACK_ADDR_MASK__RAW = str
-MCNTRL_SCANLINE_CHN3_ADDR = int
-DLY_SET__TYPE = str
-MCONTR_TOP_16BIT_ADDR = int
-DLY_DM_ODELAY = long
-MEMBRIDGE_STATUS_CNTRL__RAW = str
-MCONTR_TOP_16BIT_REFRESH_ADDRESS = int
-DFLT_DQS_TRI_OFF_PATTERN__RAW = str
+AXI_WR_ADDR_BITS__TYPE = str
+RTC_SET_STATUS = int
+MULT_SAXI_ADV_WR__TYPE = str
+CMPRS_AFIMUX_STATUS_CNTRL__RAW = str
 FRAME_FULL_WIDTH = int
-MEMBRIDGE_STATUS_REG = int
-NUM_CYCLES_13 = int
-NUM_CYCLES_12 = int
-NUM_CYCLES_11 = int
-NUM_CYCLES_10 = int
-NUM_CYCLES_15 = int
-NUM_CYCLES_14 = int
+CMPRS_AFIMUX_REG_ADDR0__RAW = str
+CMPRS_FRMT_LMARG__RAW = str
+NUM_CYCLES_22__TYPE = str
 DLY_PHASE__RAW = str
-MCNTRL_TEST01_CHN4_MODE = int
-MCNTRL_SCANLINE_WINDOW_WH = int
+MCONTR_SENS_INC__RAW = str
+MULT_SAXI_WLOG__RAW = str
 TILE_WIDTH__RAW = str
-WINDOW_WIDTH__TYPE = str
+CMPRS_FORMAT__RAW = str
+RTC_MASK = int
 MCNTRL_TEST01_MASK = int
-SLEW_CLK__TYPE = str
-DFLT_INV_CLK_DIV = int
-DEFAULT_STATUS_MODE__TYPE = str
-CLKFBOUT_DIV_REF__RAW = str
-CMD_PAUSE_BITS = int
-MCNTRL_PS_STATUS_REG_ADDR = int
-ADDRESS_NUMBER__TYPE = str
-MCNTRL_SCANLINE_FRAME_FULL_WIDTH__TYPE = str
+MEMCLK_IBUF_DELAY_VALUE__TYPE = str
+SENS_GAMMA_CTRL__TYPE = str
+HIST_CONFIRM_WRITE__RAW = str
+SENS_CTRL_ARST = int
 LD_DLY_LANE1_IDELAY__RAW = str
-MCNTRL_TEST01_CHN4_STATUS_CNTRL = int
-TEST01_START_FRAME__RAW = str
+MEMBRIDGE_STATUS_REG__RAW = str
+CMDFRAMESEQ_DEPTH__RAW = str
+SENS_LENS_BX_MASK__RAW = str
 WRITE_BLOCK_OFFSET__RAW = str
-MCNTRL_TILED_MODE = int
-NUM_CYCLES_09__TYPE = str
-MCNTRL_TILED_WINDOW_STARTXY__TYPE = str
-LD_DLY_LANE0_IDELAY__RAW = str
-FRAME_WIDTH_BITS__TYPE = str
-MCNTRL_TEST01_CHN2_STATUS_CNTRL__RAW = str
-TILED_STARTY__TYPE = str
-DFLT_DQM_PATTERN__RAW = str
-MCNTRL_TILED_CHN4_ADDR__RAW = str
+FFCLK0_DQS_BIAS__RAW = str
+MCONTR_LINTILE_SINGLE__RAW = str
 MCNTRL_TILED_FRAME_PAGE_RESET__RAW = str
-MCONTR_CMD_WR_ADDR__TYPE = str
-STATUS_DEPTH__TYPE = str
+SENS_GAMMA_BUFFER__TYPE = str
 SLEW_DQ__TYPE = str
-CLKIN_PERIOD__RAW = str
-INITIALIZE_OFFSET = int
+MCONTR_BUF4_RD_ADDR = int
 MCNTRL_PS_MASK__TYPE = str
-CLK_DIV_PHASE__RAW = str
-MCNTRL_PS_EN_RST__TYPE = str
-MCONTR_PHY_16BIT_PATTERNS__TYPE = str
-MCONTR_PHY_0BIT_CKE_EN__RAW = str
-PICKLE__RAW = str
-NUM_CYCLES_02__RAW = str
-TEST01_NEXT_PAGE__RAW = str
-DQSTRI_LAST__RAW = str
-WRITELEV_OFFSET__TYPE = str
-NUM_CYCLES_06__TYPE = str
-STATUS_ADDR_MASK__TYPE = str
-SCANLINE_STARTX__RAW = str
-SLEW_DQS__RAW = str
-MCNTRL_TILED_WINDOW_X0Y0 = int
-MCONTR_TOP_16BIT_REFRESH_PERIOD__RAW = str
-MCONTR_PHY_0BIT_DLY_SET = int
-WRITELEV_OFFSET__RAW = str
+DIVCLK_DIVIDE_PCLK__RAW = str
+MCONTR_LINTILE_BYTE32__TYPE = str
+FFCLK1_IFD_DELAY_VALUE = str
+MULT_SAXI_CNTRL_ADDR = int
+SENS_GAMMA_MODE_EN__TYPE = str
+FRAME_START_ADDRESS__TYPE = str
+CLK_MASK = int
 MCONTR_BUF4_WR_ADDR__TYPE = str
-MCONTR_PHY_0BIT_ADDR = int
-MCONTR_PHY_16BIT_EXTRA__RAW = str
-MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__TYPE = str
-MAX_TILE_HEIGHT__TYPE = str
-MCONTR_TOP_16BIT_CHN_EN__RAW = str
-NUM_CYCLES_08__TYPE = str
+CAMSYNC_MASK = int
+COLADDR_NUMBER__RAW = str
 STATUS_SEQ_SHFT = int
-NUM_CYCLES_LOW_BIT__RAW = str
-MCONTR_PHY_16BIT_WBUF_DELAY__RAW = str
-READ_PATTERN_OFFSET = int
-CLK_PHASE__TYPE = str
+SENS_GAMMA_BUFFER__RAW = str
+MULT_SAXI_AWCACHE__TYPE = str
 NUM_CYCLES_05__TYPE = str
 MCNTRL_TILED_PENDING_CNTR_BITS__TYPE = str
-MCONTR_RD_MASK = int
-MCONTR_PHY_16BIT_PATTERNS = int
-NEWPAR__RAW = str
-MCLK_PHASE__RAW = str
+AXI_WR_ADDR_BITS = int
+CLKFBOUT_MULT_XCLK__TYPE = str
+FFCLK1_IBUF_LOW_PWR__RAW = str
+MCONTR_LINTILE_REPEAT__RAW = str
 MCONTR_TOP_16BIT_REFRESH_PERIOD = int
-T_REFI = int
-CONTROL_RBACK_ADDR_MASK__TYPE = str
 MCNTRL_TILED_FRAME_FULL_WIDTH__TYPE = str
-WSEL__TYPE = str
 STATUS_SEQ_SHFT__TYPE = str
-DFLT_CHN_EN__TYPE = str
+MCONTR_CMPRS_BASE = int
 MCNTRL_SCANLINE_PENDING_CNTR_BITS__RAW = str
-MCONTR_TOP_STATUS_REG_ADDR = int
+RTC_SEC_USEC_ADDR__RAW = str
 MCNTRL_PS_ADDR = int
-MCNTRL_TILED_STATUS_REG_CHN4_ADDR__RAW = str
-MCONTR_TOP_16BIT_STATUS_CNTRL__RAW = str
-MCONTR_PHY_16BIT_PATTERNS__RAW = str
-MCONTR_PHY_0BIT_ADDR_MASK__RAW = str
-CLKFBOUT_MULT_REF__RAW = str
-DLY_LD_MASK__RAW = str
-MCNTRL_TILED_CHN2_ADDR = int
-MCNTRL_TILED_STATUS_CNTRL = int
-LD_DLY_LANE1_ODELAY = int
+SENS_BANDWIDTH = str
+MEMCLK_IBUF_LOW_PWR = str
+CAMSYNC_TRIG_DST__TYPE = str
+CMPRS_AFIMUX_RADDR1__TYPE = str
+MCONTR_PHY_STATUS_CNTRL__TYPE = str
+SENS_LENS_AY__RAW = str
+MULT_SAXI_WLOG = int
 DLY_CMDA_ODELAY__RAW = str
-MCNTRL_TILED_WINDOW_X0Y0__RAW = str
-SS_EN = str
-DLY_LANE0_ODELAY = long
-CLKFBOUT_DIV_REF = int
-WRITELEV_OFFSET = int
-MEMBRIDGE_ADDR__TYPE = str
+SENSOR_GROUP_ADDR__TYPE = str
+SENSI2C_CMD_SDA_WIDTH__RAW = str
+MCONTR_BUF2_RD_ADDR = int
+MCNTRL_TILED_FRAME_SIZE = int
+MCONTR_BUF2_WR_ADDR__TYPE = str
+CLKOUT_DIV_PCLK2X = int
+MULT_SAXI_ADDR = int
 MCONTR_TOP_16BIT_ADDR_MASK__TYPE = str
-VERBOSE__TYPE = str
-TILED_KEEP_OPEN = int
-MCNTRL_SCANLINE_MASK__RAW = str
-MCNTRL_SCANLINE_WINDOW_STARTXY = int
+SENSOR_BASE_INC = int
+MULT_SAXI_CNTRL_MASK__RAW = str
 MCONTR_ARBIT_ADDR__RAW = str
-MEMBRIDGE_MASK__RAW = str
-MCNTRL_TEST01_ADDR = int
-MCONTR_TOP_0BIT_MCONTR_EN__TYPE = str
-MEMBRIDGE_CTRL__TYPE = str
-MCONTR_BUF4_WR_ADDR__RAW = str
-TILED_KEEP_OPEN__TYPE = str
+MCONTR_LINTILE_EN__TYPE = str
+SENSI2C_REL_RADDR__TYPE = str
+GPIO_DRIVE = int
+SENS_LENS_SCALES = int
 CONTROL_ADDR_MASK__TYPE = str
 MCONTR_PHY_STATUS_REG_ADDR__RAW = str
-HIGH_PERFORMANCE_MODE__RAW = str
-T_RFC__RAW = str
-DFLT_DQM_PATTERN__TYPE = str
-STATUS_ADDR__TYPE = str
-CLKFBOUT_MULT_AXIHP = int
-CLK_DIV_PHASE__TYPE = str
-MCONTR_PHY_0BIT_CMDA_EN = int
+SENSI2C_CMD_BYTES__TYPE = str
+MCNTRL_SCANLINE_PENDING_CNTR_BITS = int
+SENS_DIVCLK_DIVIDE__TYPE = str
+LOGGER_CONF_MSG_BITS = int
+SENS_GAMMA_RADDR__TYPE = str
 MCNTRL_SCANLINE_CHN3_ADDR__RAW = str
-REFRESH_OFFSET__TYPE = str
-DFLT_INV_CLK_DIV__TYPE = str
-MAX_TILE_WIDTH = int
-CHNBUF_READ_LATENCY__RAW = str
-MEMBRIDGE_STATUS_REG__TYPE = str
-MCONTR_BUF4_RD_ADDR = int
+CMPRS_CBIT_CMODE_MONO1 = int
+CMPRS_CBIT_CMODE_MONO6 = int
+SENS_SS_EN = str
+CMPRS_CBIT_CMODE_MONO4 = int
 SS_MOD_PERIOD__TYPE = str
-MCNTRL_PS_STATUS_REG_ADDR__TYPE = str
-DFLT_DQ_TRI_OFF_PATTERN__RAW = str
-IBUF_LOW_PWR__TYPE = str
-LD_DLY_PHASE = int
-SDCLK_PHASE__RAW = str
+TILE_HEIGHT = int
+MULT_SAXI_MASK__RAW = str
+MCONTR_CMPRS_STATUS_BASE__TYPE = str
 NUM_CYCLES_10__RAW = str
-INITIALIZE_OFFSET__RAW = str
-CMD_DONE_BIT__RAW = str
-MCONTR_TOP_0BIT_REFRESH_EN__TYPE = str
-CLK_DIV_PHASE = float
-MEMBRIDGE_STATUS_REG__RAW = str
-MCONTR_TOP_16BIT_REFRESH_PERIOD__TYPE = str
-MCNTRL_TEST01_CHN4_STATUS_CNTRL__RAW = str
+SENS_LENS_FAT0_OUT__TYPE = str
+SENSOR_16BIT_BIT__TYPE = str
+SENS_NUM_SUBCHN = int
 MCONTR_BUF0_WR_ADDR__TYPE = str
-FRAME_START_ADDRESS__RAW = str
-NUM_CYCLES_12__RAW = str
-SLEW_DQS__TYPE = str
-MCNTRL_TILED_STARTADDR__TYPE = str
-DLY_LD_MASK = int
+CMPRS_COLOR18__RAW = str
+LOGGER_STATUS = int
+CMDFRAMESEQ_RUN_BIT__RAW = str

py393/x393_mcntrl_adjust.py

@@ -1108,6 +1108,8 @@ class X393McntrlAdjust(object):
         numPhaseSteps= int(dly_steps['SDCLK_PERIOD']/dly_steps['PHASE_STEP']+0.5)
         cmda_odly_data=self.adjustment_state['cmda_bspe'][phase % numPhaseSteps]
         if (not cmda_odly_data): # phase is invalid for CMDA
+            print ("phase=",phase)
+            print (self.adjustment_state['cmda_bspe'])
             return None
         cmda_odly_lin=cmda_odly_data['ldly']
         self.x393_axi_tasks.enable_refresh(0)
@@ -2862,6 +2864,8 @@ class X393McntrlAdjust(object):
                                quiet)
             if not phase_ok:
                 print ("Failed to set phase=%d for dly=%d- that should not happen (phase_dqso)- "%(phase,dqs_lin))
+                print (self.adjustment_state['cmda_bspe'])
+                
                 return None # no valid CMDA ODELAY exists for this phase
             #set DQS IDELAY and DQ IDELAY matching phase 
             dqs_idelay=dqsi_dqi_for_phase[phase][DQSI_KEY] # 2-element list
@@ -5000,7 +5004,7 @@ write_settings= {
                     prim_steps=1,
                     primary_set_in=2,
                     primary_set_out=2,
-                    dqs_pattern=0x55,
+                    dqs_pattern=0xaa,
                     rsel=None, # None (any) or 0/1
                     wsel=None, # None (any) or 0/1 # Seems wsel=0 has a better fit - consider changing
                     extraTgl=0,
@@ -5016,7 +5020,9 @@ write_settings= {
                              compare with one fine step lower
         @param primary_set_in -  which of the primary sets to use when processing DQi/DQSi results (2 - normal, 0 - other DQS phase)
         @param primary_set_out - which of the primary sets to use when processing DQo/DQSo results (2 - normal, 0 - other DQS phase)
-        @param dqs_pattern -     0x55/0xaa - DQS output toggle pattern. When it is 0x55 primary_set_out is reversed ? 
+        @param dqs_pattern -     0x55/0xaa - DQS output toggle pattern (DFLT_DQS_PATTERN). When it is 0x55 primary_set_out is reversed ? 
+        @param rsel - 0 - use first command time slot for READ, 1 uses second. Should match RSEL parameter
+        @param wsel - 0 - use first command time slot for WRITE, 1 uses second. Should match WSEL parameter
         @param extraTgl - add extra dqs toggle (2 clock cycles)
         @param quiet reduce output
         """