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Commit 35ff16ab authored by Andrey Filippov's avatar Andrey Filippov
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Updated Python code, added some missing comments

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.project
View file @ 35ff16ab
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150818191452916.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150826180314606.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150818190618667.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150826180314606.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150818191452916.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150826180314606.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150818190618667.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150826180314606.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150818190618667.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150826180314606.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150818191452916.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150826180314606.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150818185615292.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150826175759893.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150818191452916.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150826180314606.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......@@ -107,32 +107,32 @@
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150818191452916.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150826180314606.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150818185615292.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150826175759893.log</location>
</link>
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<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150818191452916.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150826180314606.dcp</location>
</link>
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<name>vivado_state/x393-place.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150818190618667.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150826180314606.dcp</location>
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<name>vivado_state/x393-route.dcp</name>
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<location>/home/andrey/git/x393/vivado_state/x393-route-20150818191452916.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150826180314606.dcp</location>
</link>
<link>
<name>vivado_state/x393-synth.dcp</name>
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<location>/home/andrey/git/x393/vivado_state/x393-synth-20150818185615292.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150826175759893.dcp</location>
</link>
</linkedResources>
</projectDescription>
py393/dbg/x393_mcntrl.pickle
View file @ 35ff16ab
This diff is collapsed.
py393/hargs-auto
View file @ 35ff16ab
......@@ -3,6 +3,5 @@
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c measure_all "ICWRPOASZB" 1 2 2 0xaa None 1 3
-c set_phase_delays
-c measure_all "*ICWRPOASZB" 1 2 2 0xaa 1 0 0 3
-c save
py393/vrlg.py
View file @ 35ff16ab
This diff is collapsed.
py393/x393_mcntrl_adjust.py
View file @ 35ff16ab
......@@ -1108,6 +1108,8 @@ class X393McntrlAdjust(object):
numPhaseSteps= int(dly_steps['SDCLK_PERIOD']/dly_steps['PHASE_STEP']+0.5)
cmda_odly_data=self.adjustment_state['cmda_bspe'][phase % numPhaseSteps]
if (not cmda_odly_data): # phase is invalid for CMDA
print ("phase=",phase)
print (self.adjustment_state['cmda_bspe'])
return None
cmda_odly_lin=cmda_odly_data['ldly']
self.x393_axi_tasks.enable_refresh(0)
......@@ -2862,6 +2864,8 @@ class X393McntrlAdjust(object):
quiet)
if not phase_ok:
print ("Failed to set phase=%d for dly=%d- that should not happen (phase_dqso)- "%(phase,dqs_lin))
print (self.adjustment_state['cmda_bspe'])
return None # no valid CMDA ODELAY exists for this phase
#set DQS IDELAY and DQ IDELAY matching phase
dqs_idelay=dqsi_dqi_for_phase[phase][DQSI_KEY] # 2-element list
......@@ -5000,7 +5004,7 @@ write_settings= {
prim_steps=1,
primary_set_in=2,
primary_set_out=2,
dqs_pattern=0x55,
dqs_pattern=0xaa,
rsel=None, # None (any) or 0/1
wsel=None, # None (any) or 0/1 # Seems wsel=0 has a better fit - consider changing
extraTgl=0,
......@@ -5016,7 +5020,9 @@ write_settings= {
compare with one fine step lower
@param primary_set_in - which of the primary sets to use when processing DQi/DQSi results (2 - normal, 0 - other DQS phase)
@param primary_set_out - which of the primary sets to use when processing DQo/DQSo results (2 - normal, 0 - other DQS phase)
@param dqs_pattern - 0x55/0xaa - DQS output toggle pattern. When it is 0x55 primary_set_out is reversed ?
@param dqs_pattern - 0x55/0xaa - DQS output toggle pattern (DFLT_DQS_PATTERN). When it is 0x55 primary_set_out is reversed ?
@param rsel - 0 - use first command time slot for READ, 1 uses second. Should match RSEL parameter
@param wsel - 0 - use first command time slot for WRITE, 1 uses second. Should match WSEL parameter
@param extraTgl - add extra dqs toggle (2 clock cycles)
@param quiet reduce output
"""
......
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