Added interrupts to membridge module

axi/membridge.v

@@ -48,7 +48,8 @@ module  membridge#(
     parameter MEMBRIDGE_START64=                  'h4, // start address relative to lo_addr
     parameter MEMBRIDGE_LEN64=                    'h5, // full length of transfer in 64-bit words
     parameter MEMBRIDGE_WIDTH64=                  'h6, // frame width in 64-bit words (partial last page in each line)
-    parameter MEMBRIDGE_MODE=                     'h7, // bits [3:0] - *_cache, bit [4] - cache debug
+//    parameter MEMBRIDGE_MODE=                     'h7, // bits [3:0] - *_cache, bit [4] - cache debug
+    parameter MEMBRIDGE_CTRL_IRQ=                 'h7,  // offset for IRQ control register (4 dibits): 0 - nop, 1 reset, 2 - disable, 3 - enable
     parameter MEMBRIDGE_STATUS_REG=               'h3b,
     parameter FRAME_HEIGHT_BITS=                   16,   // Maximal frame height bits
     parameter FRAME_WIDTH_BITS=                    13
@@ -70,6 +71,7 @@ module  membridge#(
     output                  [7:0] status_ad,   // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
     output                        status_rq,   // input request to send status downstream
     input                         status_start, // Acknowledge of the first status packet byte (address)
+    output                        irq,          // Masked interrupt request (level, resettable)
     // mcntrl_linear_rw.v interface
     output                        frame_start_chn, // input
     output                        next_page_chn, // input
@@ -182,14 +184,15 @@ module  membridge#(
     wire set_size64_w;
     wire set_start64_w;
     wire set_len64_w;
-    wire set_mode_w;
+    wire set_irq_w;
     wire set_width64_w;
-    reg  [4:0] mode_reg_mclk;
-    reg  [4:0] mode_reg;
+//    reg  [4:0] mode_reg_mclk;
+//    reg  [4:0] mode_reg;
     wire       cache_debug;
-    assign cache_debug=mode_reg[4];
-    assign afi_awcache =       mode_reg[3:0]; // 4'h3;
-    assign afi_arcache =       mode_reg[3:0]; // 4'h3;
+    // Disabling cache modes and debug - cache modes are not supported in Zynq
+    assign cache_debug=         0;    // mode_reg[4];
+    assign afi_awcache =        4'h3; // mode_reg[3:0]; // 4'h3;
+    assign afi_arcache =        4'h3; // mode_reg[3:0]; // 4'h3;
     assign set_ctrl_w =         cmd_we && (cmd_a== MEMBRIDGE_CTRL);
     assign set_lo_addr64_w =    cmd_we && (cmd_a== MEMBRIDGE_LO_ADDR64);
     assign set_size64_w =       cmd_we && (cmd_a== MEMBRIDGE_SIZE64);
@@ -197,7 +200,7 @@ module  membridge#(
     assign set_len64_w =        cmd_we && (cmd_a== MEMBRIDGE_LEN64);
     assign set_width64_w =      cmd_we && (cmd_a== MEMBRIDGE_WIDTH64);
     assign set_status_w =       cmd_we && (cmd_a== MEMBRIDGE_STATUS_CNTRL);
-    assign set_mode_w =         cmd_we && (cmd_a== MEMBRIDGE_MODE);
+    assign set_irq_w =          cmd_we && (cmd_a== MEMBRIDGE_CTRL_IRQ);
     reg [28:0] lo_addr64_mclk;
     reg [28:0] size64_mclk;
     reg [28:0] start64_mclk;
@@ -223,7 +226,12 @@ module  membridge#(
     wire       debug_w_ready;
     assign debug_aw_ready = (!debug_aw_allowed[6] && (|debug_aw_allowed[5:0])) || debug_disable; // > 0
     assign debug_w_ready =  (!debug_w_allowed[8]  && (|debug_w_allowed [7:0]) &&((|debug_w_allowed [7:1]) || !(|debug_bufrd_rd))) || debug_disable; // > 0
-`endif    
+`endif 
+    reg        irq_r = 0;
+    reg        irq_m = 0;
+    wire       done_mclk; // pre_done && !done @ posedge mclk
+    assign irq = irq_r && irq_m;
+       
 //cmd_wrmem
     always @ (posedge mclk) begin
         if (set_lo_addr64_w)    lo_addr64_mclk       <= {cmd_data[28:4],4'b0}; // align to 16-bursts
@@ -244,8 +252,8 @@ module  membridge#(
         if   (mrst) start_mclk <= 0;
         else        start_mclk <= set_ctrl_w & cmd_data[1];
 
-        if      (mrst)       mode_reg_mclk <= 5'h03;
-        else if (set_mode_w) mode_reg_mclk <= cmd_data[4:0];
+//        if      (mrst)       mode_reg_mclk <= 5'h03;
+//        else if (set_mode_w) mode_reg_mclk <= cmd_data[4:0];
 
 `ifdef MEMBRIDGE_DEBUG_READ
         if  (mrst) debug_aw_mclk <= 0;
@@ -259,9 +267,19 @@ module  membridge#(
         
         
 `endif
-
     end
     
+    // IRQ-related
+    always @ (posedge mclk) begin
+        if      (mrst)                              irq_m <= 0;
+        else if (set_irq_w && cmd_data[1])          irq_m <= cmd_data[0];
+        
+        if      (mrst)                              irq_r <= 0;
+        else if (done_mclk)                         irq_r <= 1;
+        else if (set_irq_w && (cmd_data[1:0] == 1)) irq_r <= 0;
+    end    
+    
+    
     // syncronize mclk ->hclk
     
     reg [28:0] lo_addr64;
@@ -310,7 +328,7 @@ module  membridge#(
         size64          <= size64_mclk;
         start64         <= start64_mclk;
         len64           <= len64_mclk;
-        mode_reg        <= mode_reg_mclk;
+//        mode_reg        <= mode_reg_mclk;
         last_in_line64  <= width64_minus1_mclk;
         wr_mode         <= cmd_wrmem;
         rdwr_reset_addr <= rdwr_reset_addr_mclk;
@@ -348,6 +366,9 @@ module  membridge#(
     pulse_cross_clock frame_done_i     (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(frame_done_chn), .out_pulse(frame_done),.busy());
     pulse_cross_clock  reset_page_wr_i (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(xfer_reset_page_wr), .out_pulse(reset_page_wr),.busy());
 
+    //hclk -> mclk
+    pulse_cross_clock done_mclk_i      (.rst(hrst), .src_clk(hclk), .dst_clk(mclk), .in_pulse(pre_done &&!done), .out_pulse(done_mclk),.busy());
+
 `ifdef MEMBRIDGE_DEBUG_READ
     // mclk -> hclk, debug-only
     pulse_cross_clock debug_aw_i         (.rst(hrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(debug_aw_mclk), .out_pulse(debug_aw),.busy());
@@ -744,9 +765,9 @@ module  membridge#(
     status_generate #(
         .STATUS_REG_ADDR  (MEMBRIDGE_STATUS_REG),
 `ifdef MEMBRIDGE_DEBUG_READ
-        .PAYLOAD_BITS     (18) // 2) // With debug
+        .PAYLOAD_BITS     (20) // 2) // With debug
 `else
-        .PAYLOAD_BITS     (18) //2)
+        .PAYLOAD_BITS     (20) //2)
 `endif        
     ) status_generate_i (
         .rst              (1'b0),                                            //   rst), // input
@@ -755,9 +776,9 @@ module  membridge#(
         .we               (set_status_w),                                    // input
         .wd               (cmd_data[7:0]),                                   // input[7:0]
 `ifdef MEMBRIDGE_DEBUG_READ
-        .status           ({debug_aw_allowed, debug_w_allowed, done, busy}), // input[25:0]
+        .status           ({irq_m, irq_r, debug_aw_allowed[7:0], debug_w_allowed[7:0], done, busy}), // input[25:0]
 `else
-        .status           ({axi_arw_requested, wresp_conf, done, busy}),     // input[25:0] 
+        .status           ({irq_m, irq_r, axi_arw_requested[7:0], wresp_conf[7:0], done, busy}),     // input[25:0] 
 `endif
         .ad               (status_ad),                                       // output[7:0] 
         .rq               (status_rq),                                       // output

axi/mult_saxi_wr.v

@@ -47,7 +47,7 @@ module  mult_saxi_wr #(
     parameter MULT_SAXI_CNTRL_ADDR =     'h73c,  // ..'h73e
     parameter MULT_SAXI_CNTRL_MODE =     'h0,  // 'h73c offset for mode register
     parameter MULT_SAXI_CNTRL_STATUS =   'h1,  // 'h73d offset for status control register
-    parameter MULT_SAXI_CNTRL_IRQ =      'h2,  // 'h73e offset for IRQ contgrol register (4 dibits): 0 - nop, 1 reset, 2 - disable, 3 - enable
+    parameter MULT_SAXI_CNTRL_IRQ =      'h2,  // 'h73e offset for IRQ control register (4 dibits): 0 - nop, 1 reset, 2 - disable, 3 - enable
     parameter MULT_SAXI_POINTERS_REG =   'h34,   //..'h37 uses 4 consecutive locations
     parameter MULT_SAXI_STATUS_REG =     'h3c,   //status and IRQ requests and masks
     parameter MULT_SAXI_HALF_BRAM =       1,     // 0 - use full 36Kb BRAM for the buffer, 1 - use just half

includes/tasks_tests_memory.vh

@@ -142,7 +142,7 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
     input [28:0] size64;    // size of the system memory range in 64-bit words
     input        continue;    // 0 start from start64, 1 - continue from where it was
     input        disable_need;
-    input  [4:0] cache_mode;  // 'h3 - normal, 'h13 - debug
+    input  [4:0] cache_mode;  // 'h3 - normal, 'h13 - debug - disabled
     input        rpt;
     
     
@@ -193,8 +193,8 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
             (window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0}, // width64,
             start64,
             lo_addr64,
-            size64,
-            cache_mode);
+            size64); 
+//            cache_mode);
         membridge_start (continue);
 `ifdef MEMBRIDGE_DEBUG_READ    
         // debugging

includes/x393_parameters.vh

@@ -328,7 +328,8 @@
     parameter MEMBRIDGE_START64=                  'h4, // start address relative to lo_addr
     parameter MEMBRIDGE_LEN64=                    'h5, // full length of transfer in 64-bit words
     parameter MEMBRIDGE_WIDTH64=                  'h6, // frame width in 64-bit words (partial last page in each line)
-    parameter MEMBRIDGE_MODE=                     'h7, // AXI cache mode (default == 3). +0x10 - debug cache (replace data with counters)
+//    parameter MEMBRIDGE_MODE=                     'h7, // AXI cache mode (default == 3). +0x10 - debug cache (replace data with counters)
+    parameter MEMBRIDGE_CTRL_IRQ=                 'h7,  // offset for IRQ control register (4 dibits): 0 - nop, 1 reset, 2 - disable, 3 - enable
     parameter MEMBRIDGE_STATUS_REG=               'h3b,
 
     parameter RSEL=                               1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
@@ -833,7 +834,7 @@
     parameter MULT_SAXI_CNTRL_ADDR =     'h73c,  // ..'h73e
     parameter MULT_SAXI_CNTRL_MODE =       'h0,  // 'h73c offset for mode register
     parameter MULT_SAXI_CNTRL_STATUS =     'h1,  // 'h73d offset for status control register
-    parameter MULT_SAXI_CNTRL_IRQ =        'h2,  // 'h73e offset for IRQ contgrol register (4 dibits): 0 - nop, 1 reset, 2 - disable, 3 - enable
+    parameter MULT_SAXI_CNTRL_IRQ =        'h2,  // 'h73e offset for IRQ control register (4 dibits): 0 - nop, 1 reset, 2 - disable, 3 - enable
     parameter MULT_SAXI_POINTERS_REG =   'h34,   //..'h37 uses 4 consecutive locations
     parameter MULT_SAXI_STATUS_REG =     'h3c,   //status and IRQ requests and masks
     parameter MULT_SAXI_HALF_BRAM =       1,     // 0 - use full 36Kb BRAM for the buffer, 1 - use just half

includes/x393_tasks_afi.vh

@@ -42,14 +42,14 @@
     input [28:0] start64;  // relative start address of the transfer (set to 0 when writing lo_addr64)
     input [28:0] lo_addr64; // low address of the system memory range, in 64-bit words 
     input [28:0] size64;    // size of the system memory range in 64-bit words
-    input  [4:0] mode; 
+//    input  [4:0] mode; 
     begin
         write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_LO_ADDR64,        {3'b0,lo_addr64});    
         write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_SIZE64,           {3'b0,size64});    
         write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_START64,          {3'b0,start64});    
         write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_LEN64,            {3'b0,len64});    
         write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_WIDTH64,          {3'b0,width64});    
-        write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_MODE,             {27'b0,mode});    
+//        write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL_IRQ,         {27'b0,mode});    
     end
 endtask
 

py393/cargs

 -d TARGET_MODE=1
 -f ../system_defines.vh
--f ../includes/x393_parameters.vh ../includes/x393_cur_params_target.vh ../includes/x393_localparams.vh
+-f ../includes/x393_parameters.vh ../includes/x393_cur_params_target.vh ../includes/x393_localparams.vh ../includes/x393_simulation_parameters.vh
 -l ../includes/x393_cur_params_target_gen.vh
 -p PICKLE="../includes/x393_mcntrl.pickle"
 -c export_all
\ No newline at end of file

py393/vrlg.py

@@ -180,8 +180,9 @@ NUM_CYCLES_20__TYPE = str
 SENS_JTAG_PGMEN = int
 NUM_CYCLES_03__TYPE = str
 CMPRS_CBIT_RUN_BITS__TYPE = str
-LD_DLY_LANE1_IDELAY__TYPE = str
+SENSOR12BITS_TDDO1 = int
 TILED_EXTRA_PAGES__RAW = str
+MEMBRIDGE_CTRL_IRQ__RAW = str
 CMPRS_NUM_AFI_CHN = int
 CAMSYNC_TRIG_SRC__RAW = str
 MEMCLK_CAPACITANCE = str
@@ -214,6 +215,7 @@ RTC_SET_STATUS__TYPE = str
 CMPRS_CBIT_QBANK_BITS__RAW = str
 DEBUG_READ_REG_ADDR = int
 WINDOW_HEIGHT = int
+NUM_INTERRUPTS__TYPE = str
 CAMSYNC_TRIG_DELAY0__RAW = str
 MCONTR_SENS_STATUS_INC__RAW = str
 SENSOR_HIST_NRST_BITS = int
@@ -222,18 +224,22 @@ MCNTRL_TEST01_STATUS_REG_CHN1_ADDR__RAW = str
 CLKFBOUT_MULT = int
 RTC_STATUS_REG_ADDR__RAW = str
 SENS_LENS_C_MASK__RAW = str
+SIMULATE_CMPRS_CMODE0__RAW = str
 NUM_CYCLES_11__TYPE = str
 DEBUG_ADDR__TYPE = str
 CMPRS_CBIT_QBANK_BITS__TYPE = str
 SENS_GAMMA_MODE_TRIG = int
 RTC_SET_USEC = int
 RTC_BITC_PREDIV__TYPE = str
+SIMULATE_CMPRS_CMODE0__TYPE = str
 LD_DLY_CMDA = int
 DLY_SET__RAW = str
 SENSI2C_CMD_TABLE = int
 MCNTRL_PS_ADDR__RAW = str
+WOI_WIDTH__TYPE = str
 NUM_FRAME_BITS__RAW = str
 SENSI2C_CMD_ACIVE__RAW = str
+HISTOGRAM_TOP__RAW = str
 LOGGER_CONF_GPS__TYPE = str
 HIST_SAXI_EN__RAW = str
 SENSOR_16BIT_BIT__RAW = str
@@ -257,6 +263,7 @@ NUM_CYCLES_30 = int
 HISPI_DELAY_CLK0__TYPE = str
 CMPRS_CBIT_QBANK__RAW = str
 SENS_SYNC_MASK__TYPE = str
+MEMCLK_PERIOD__TYPE = str
 MCONTR_BUF0_RD_ADDR__RAW = str
 HISPI_MMCM1 = str
 SENS_PHASE_WIDTH = int
@@ -280,6 +287,7 @@ DLY_LANE1_DQS_WLV_IDELAY__RAW = str
 SENS_LENS_RADDR = int
 SENSI2C_CMD_TABLE__TYPE = str
 PXD_IOSTANDARD = str
+SENSOR12BITS_TMD__RAW = str
 MAX_TILE_HEIGHT = int
 BUF_CLK1X_PCLK = str
 LOGGER_CONF_DBG_BITS = int
@@ -303,6 +311,7 @@ MAX_TILE_WIDTH__TYPE = str
 MULTICLK_DIV_DLYREF__TYPE = str
 MULTICLK_MULT = int
 SENS_LENS_POST_SCALE_MASK = int
+MEMCLK_PERIOD = float
 BUF_IPCLK2X_SENS1__RAW = str
 SENSOR_MODE_WIDTH__RAW = str
 SENS_LENS_FAT0_OUT_MASK = int
@@ -324,12 +333,14 @@ RTC_STATUS_REG_ADDR = int
 SENS_LENS_BY_MASK__TYPE = str
 CMPRS_CBIT_CMODE__RAW = str
 TILED_EXTRA_PAGES__TYPE = str
+AXI_RDADDR_LATENCY = int
 AFI_MUX_BUF_LATENCY = int
 WINDOW_WIDTH = int
 CLK_CNTRL__RAW = str
 MCONTR_LINTILE_EXTRAPG_BITS = int
 MCONTR_LINTILE_RST_FRAME__TYPE = str
-LAST_BUF_FRAME__RAW = str
+HISTOGRAM_TOP = int
+FCLK1_PERIOD = float
 CMPRS_AFIMUX_RADDR1__RAW = str
 MCNTRL_TEST01_CHN1_STATUS_CNTRL__RAW = str
 CMPRS_CBIT_DCSUB_BITS__RAW = str
@@ -342,6 +353,7 @@ DFLT_WBUF_DELAY__RAW = str
 CAMSYNC_POST_MAGIC__RAW = str
 NUM_CYCLES_07__RAW = str
 NUM_CYCLES_24__RAW = str
+NUM_INTERRUPTS = int
 NUM_CYCLES_13__RAW = str
 LOGGER_CONF_MSG__RAW = str
 MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
@@ -349,8 +361,9 @@ LAST_FRAME_BITS__RAW = str
 SENS_DIVCLK_DIVIDE = int
 SENSI2C_CMD_SOFT_SDA__TYPE = str
 SENS_LENS_COEFF__RAW = str
-CMPRS_CONTROL_REG = int
+GPIO_MASK = int
 GPIO_STATUS_REG_ADDR = int
+AXI_TASK_HOLD__RAW = str
 MCNTRL_SCANLINE_WINDOW_WH__TYPE = str
 CMPRS_AFIMUX_RADDR0__TYPE = str
 MCNTRL_TILED_WINDOW_WH__RAW = str
@@ -410,6 +423,7 @@ NUM_CYCLES_21 = int
 FRAME_FULL_WIDTH__TYPE = str
 CAMSYNC_TRIG_DELAY2__TYPE = str
 MULTICLK_BUF_DLYREF__RAW = str
+FCLK0_PERIOD = float
 CMDFRAMESEQ_REL__TYPE = str
 HISPI_DELAY_CLK0 = str
 MAX_TILE_WIDTH__RAW = str
@@ -437,6 +451,7 @@ MCONTR_LINTILE_SKIP_LATE__TYPE = str
 DEBUG_ADDR__RAW = str
 CONTROL_ADDR__RAW = str
 TILED_STARTY__RAW = str
+RTC_BITC_PREDIV = int
 CMPRS_FRMT_MBCM1_BITS__TYPE = str
 SENS_CTRL_QUADRANTS_EN__RAW = str
 HISPI_DELAY_CLK1__TYPE = str
@@ -454,7 +469,7 @@ MULTICLK_DIV_SYNC__RAW = str
 CMPRS_CORING_MODE = int
 LOGGER_STATUS__TYPE = str
 DFLT_REFRESH_PERIOD__TYPE = str
-SENS_JTAG_TMS__TYPE = str
+FFCLK1_IOSTANDARD = str
 MCNTRL_TILED_MASK = int
 MULTICLK_DIV_AXIHP = int
 SENSIO_JTAG__RAW = str
@@ -469,11 +484,12 @@ MCONTR_LINTILE_KEEP_OPEN = int
 SENS_SYNC_LATE__RAW = str
 SENSI2C_TBL_NBRD_BITS__RAW = str
 DLY_CMDA_ODELAY = long
-SENS_LENS_C = int
+GPIO_PORTEN__RAW = str
 MCONTR_ARBIT_ADDR_MASK = int
 MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR = int
 MCNTRL_SCANLINE_WINDOW_WH = int
 WBUF_DLY_WLV__RAW = str
+SIMULATE_CMPRS_CMODE3__RAW = str
 TABLE_HUFFMAN_INDEX = int
 MCNTRL_TILED_FRAME_LAST = int
 MCNTRL_TEST01_CHN2_MODE__RAW = str
@@ -486,6 +502,7 @@ CAMSYNC_EN_BIT__TYPE = str
 LD_DLY_LANE0_IDELAY = int
 NUM_CYCLES_01__TYPE = str
 NUM_CYCLES_24__TYPE = str
+FCLK0_PERIOD__RAW = str
 MCLK_PHASE__TYPE = str
 SENSI2C_DRIVE__TYPE = str
 SENS_CTRL_RST_MMCM__RAW = str
@@ -498,11 +515,12 @@ MCNTRL_TILED_FRAME_FULL_WIDTH = int
 CMDFRAMESEQ_DEPTH = int
 SENS_LENS_POST_SCALE__TYPE = str
 RTC_MHZ__RAW = str
-FRAME_HEIGHT_BITS = int
+SENSOR_PRIORITY__RAW = str
 HIST_SAXI_ADDR_MASK__TYPE = str
 SENS_CTRL_LD_DLY = int
 SENS_LENS_FAT0_IN_MASK__RAW = str
 SENS_LENS_AY_MASK__RAW = str
+SENSOR_IMAGE_TYPE1__TYPE = str
 MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE = str
 MCONTR_LINTILE_DIS_NEED__TYPE = str
 DFLT_DQS_PATTERN__RAW = str
@@ -513,6 +531,7 @@ REF_JITTER1__TYPE = str
 FFCLK1_DIFF_TERM = str
 MULTICLK_PHASE_AXIHP__TYPE = str
 FFCLK0_IOSTANDARD__TYPE = str
+WOI_WIDTH__RAW = str
 STATUS_MSB_RSHFT = int
 CMPRS_CONTROL_REG__RAW = str
 CLKIN_PERIOD__TYPE = str
@@ -549,8 +568,9 @@ NUM_CYCLES_11 = int
 SENS_GAMMA_ADDR_MASK = int
 NUM_CYCLES_10 = int
 MEMCLK_IBUF_LOW_PWR__TYPE = str
+HISTOGRAM_HEIGHT__TYPE = str
 CMPRS_HIFREQ_REG_BASE__TYPE = str
-SENS_HIGH_PERFORMANCE_MODE__RAW = str
+FCLK0_PERIOD__TYPE = str
 MCNTRL_SCANLINE_FRAME_PAGE_RESET__RAW = str
 DQTRI_LAST__TYPE = str
 MULTICLK_DIVCLK__TYPE = str
@@ -571,7 +591,6 @@ NUM_CYCLES_16 = int
 NUM_CYCLES_15 = int
 NUM_CYCLES_21__TYPE = str
 CMPRS_CBIT_BAYER = int
-GPIO_PORTEN__RAW = str
 SLEW_CLK__TYPE = str
 MCONTR_PHY_0BIT_DLY_SET = int
 HISPI_DIFF_TERM__TYPE = str
@@ -583,6 +602,7 @@ SENSI2C_TBL_SA__TYPE = str
 BUF_IPCLK_SENS3__TYPE = str
 MCNTRL_TILED_MODE = int
 MCNTRL_TILED_WINDOW_STARTXY__TYPE = str
+HISTOGRAM_HEIGHT = int
 MCNTRL_TEST01_CHN2_STATUS_CNTRL__RAW = str
 LOGGER_CONF_SYN = int
 MCNTRL_TILED_CHN4_ADDR__RAW = str
@@ -594,6 +614,10 @@ PICKLE__RAW = str
 DQSTRI_LAST__RAW = str
 WRITELEV_OFFSET__TYPE = str
 CMPRS_BASE_INC = int
+SIMULATE_CMPRS_CMODE2 = int
+SIMULATE_CMPRS_CMODE3 = int
+SIMULATE_CMPRS_CMODE0 = int
+SIMULATE_CMPRS_CMODE1 = int
 MULT_SAXI_CNTRL_ADDR = int
 MULTICLK_BUF_SYNC__TYPE = str
 HIST_SAXI_ADDR_REL__RAW = str
@@ -619,13 +643,15 @@ CAMSYNC_EN_BIT = int
 MCONTR_PHY_16BIT_PATTERNS__RAW = str
 HISTOGRAM_RAM_MODE = str
 SENS_REFCLK_FREQUENCY__TYPE = str
+HISTOGRAM_TOP__TYPE = str
 SENS_GAMMA_MODE_EN__RAW = str
 SENSI2C_TBL_SA_BITS__TYPE = str
 DEBUG_ADDR = int
+SIMULATE_CMPRS_CMODE2__TYPE = str
 MULT_SAXI_ADV_WR__RAW = str
 LOGGER_PAGE_GPS = int
 HIST_SAXI_MODE_ADDR_MASK = int
-WRITELEV_OFFSET = int
+CMPRS_AFIMUX_SA_LEN__RAW = str
 LOGGER_CONF_MSG = int
 CMPRS_CSAT_CR__RAW = str
 CMPRS_CBIT_RUN = int
@@ -640,9 +666,10 @@ MULT_SAXI_HALF_BRAM_IN__RAW = str
 SENSI2C_TBL_SA__RAW = str
 CMPRS_CBIT_CMODE_JP4__RAW = str
 MULTICLK_BUF_AXIHP__RAW = str
-DFLT_DQM_PATTERN__RAW = str
+CLK_STATUS__TYPE = str
 GPIO_SET_STATUS__RAW = str
 SENS_JTAG_TCK = int
+CMPRS_COLOR20__TYPE = str
 DEBUG_STATUS_REG_ADDR__TYPE = str
 REFRESH_OFFSET__TYPE = str
 SENS_CTRL_ARST__RAW = str
@@ -739,7 +766,7 @@ LOGGER_PERIOD__RAW = str
 MCNTRL_SCANLINE_STATUS_CNTRL__TYPE = str
 SENS_LENS_AX_MASK = int
 AXI_RD_ADDR_BITS__RAW = str
-RTC_BITC_PREDIV = int
+AXI_WRADDR_LATENCY = int
 SENS_SS_MOD_PERIOD__TYPE = str
 MCONTR_LINTILE_SKIP_LATE__RAW = str
 SENS_JTAG_PGMEN__TYPE = str
@@ -763,7 +790,7 @@ SS_MOD_PERIOD = int
 MCONTR_CMPRS_BASE__TYPE = str
 FFCLK1_IBUF_LOW_PWR = str
 HISPI_CAPACITANCE__TYPE = str
-TEST01_SUSPEND__TYPE = str
+MCONTR_LINTILE_KEEP_OPEN__TYPE = str
 SENS_LENS_POST_SCALE = int
 LOGGER_STATUS_REG_ADDR__TYPE = str
 SS_MODE = str
@@ -784,19 +811,22 @@ MCNTRL_SCANLINE_MASK = int
 MULTICLK_DIVCLK = int
 MCNTRL_TILED_TILE_WHS__TYPE = str
 MULT_SAXI_BSLOG3__TYPE = str
+SENSOR12BITS_NGPL__RAW = str
 CLKFBOUT_MULT__RAW = str
 CMPRS_STATUS_REG_INC__RAW = str
+SIMULATE_CMPRS_CMODE1__TYPE = str
 HISTOGRAM_RADDR0__RAW = str
 HISPI_KEEP_IRST = int
 STATUS_ADDR_MASK = int
 PXD_CAPACITANCE = str
 SENS_LENS_AY = int
 CMPRS_CBIT_CMODE_MONO6__TYPE = str
+MULTICLK_BUF_XCLK__RAW = str
 HISTOGRAM_RAM_MODE__RAW = str
 SENS_LENS_AX_MASK__RAW = str
 SENSI2C_TBL_SA_BITS = int
 CMPRS_FRMT_MBCM1__TYPE = str
-SENSOR_HIST_EN_BITS__RAW = str
+CMPRS_TIMEOUT__TYPE = str
 MULT_SAXI_ADV_WR = int
 NUM_CYCLES_10__TYPE = str
 MCONTR_LINTILE_EXTRAPG__RAW = str
@@ -816,6 +846,7 @@ MCONTR_BUF4_WR_ADDR = int
 SENS_DIVCLK_DIVIDE__RAW = str
 SENSOR_BASE_INC__RAW = str
 CMPRS_CBIT_DCSUB_BITS = int
+HISTOGRAM_LEFT__RAW = str
 MCONTR_TOP_16BIT_ADDR_MASK = int
 PXD_IBUF_LOW_PWR__TYPE = str
 MCONTR_LINTILE_REPEAT__TYPE = str
@@ -836,7 +867,6 @@ MCONTR_PHY_16BIT_WBUF_DELAY = int
 DLY_LANE1_DQS_WLV_IDELAY__TYPE = str
 TILE_HEIGHT__RAW = str
 MULTICLK_PHASE_SYNC = float
-MEMBRIDGE_MODE__RAW = str
 SENSI2C_TBL_SA_BITS__RAW = str
 HISPI_MMCM3__RAW = str
 CMPRS_CBIT_RUN_STANDALONE = int
@@ -871,6 +901,7 @@ MCONTR_LINTILE_NRESET__TYPE = str
 PXD_CLK_DIV__RAW = str
 SENS_NUM_SUBCHN__RAW = str
 CMPRS_CBIT_RUN_ENABLE__RAW = str
+AXI_RDADDR_LATENCY__TYPE = str
 BUF_IPCLK_SENS3__RAW = str
 CLK_STATUS__RAW = str
 MULTICLK_BUF_AXIHP = str
@@ -880,10 +911,10 @@ SENS_CTRL_RST_MMCM = int
 HISPI_DQS_BIAS__TYPE = str
 MCONTR_CMD_WR_ADDR = int
 SENSI2C_TBL_DLY_BITS__RAW = str
-CMPRS_CSAT_CB__TYPE = str
+SENSOR12BITS_TDDO1__RAW = str
 HISPI_MMCM0__TYPE = str
 TILE_WIDTH = int
-GPIO_MASK = int
+CMPRS_CONTROL_REG = int
 DLY_LANE0_ODELAY = long
 NUM_XFER_BITS = int
 HISPI_NUMLANES__RAW = str
@@ -892,6 +923,7 @@ DLY_DQS_ODELAY__TYPE = str
 DLY_LANE0_ODELAY__RAW = str
 MCONTR_BUF3_WR_ADDR__TYPE = str
 SCANLINE_STARTX__TYPE = str
+CAMSYNC_MASTER_BIT__TYPE = str
 WRITE_BLOCK_OFFSET = int
 FRAME_FULL_WIDTH__RAW = str
 LOGGER_CONF_EN__TYPE = str
@@ -907,7 +939,9 @@ LOGGER_BIT_DURATION__TYPE = str
 HISPI_MMCM1__RAW = str
 MULT_SAXI_CNTRL_STATUS = int
 TEST_INITIAL_BURST__TYPE = str
+SENSOR12BITS_NVLO = int
 NUM_CYCLES_19__RAW = str
+SIMULATE_CMPRS_CMODE2__RAW = str
 MCNTRL_PS_MASK__RAW = str
 CMPRS_CBIT_CMODE_JPEG20__TYPE = str
 HISPI_IBUF_LOW_PWR__TYPE = str
@@ -920,6 +954,7 @@ CMPRS_TIMEOUT_BITS__TYPE = str
 SENS_GAMMA_MODE_WIDTH__RAW = str
 PHASE_CLK2X_PCLK__TYPE = str
 FFCLK1_DIFF_TERM__TYPE = str
+WRITELEV_OFFSET = int
 MCONTR_PHY_0BIT_ADDR_MASK__TYPE = str
 MULT_SAXI_ADV_RD__RAW = str
 SENS_SYNC_RADDR = int
@@ -938,7 +973,6 @@ CMDSEQMUX_STATUS = int
 SENSI2C_TBL_RNWREG__TYPE = str
 FRAME_START_ADDRESS_INC = int
 TILED_STARTY = int
-MEMBRIDGE_MODE__TYPE = str
 LOGGER_MASK = int
 MCNTRL_SCANLINE_FRAME_FULL_WIDTH = int
 WINDOW_Y0 = int
@@ -950,6 +984,7 @@ CMPRS_MONO16__TYPE = str
 READ_PATTERN_OFFSET__RAW = str
 SENSI2C_TBL_DLY__TYPE = str
 MEMBRIDGE_SIZE64 = int
+SENSOR_IMAGE_TYPE1__RAW = str
 MCONTR_PHY_0BIT_CKE_EN__TYPE = str
 CMPRS_FRMT_MBCM1_BITS = int
 HISTOGRAM_RAM_MODE__TYPE = str
@@ -957,8 +992,9 @@ AFI_LO_ADDR64 = int
 NUM_CYCLES_07__TYPE = str
 SENS_LENS_FAT0_IN = int
 CMPRS_FRMT_LMARG_BITS__TYPE = str
+SENSOR12BITS_NGPL__TYPE = str
 HISTOGRAM_RADDR1__TYPE = str
-CAMSYNC_MASTER_BIT__TYPE = str
+SIMUL_AXI_READ_WIDTH = int
 HISTOGRAM_ADDR_MASK = int
 MCONTR_BUF2_RD_ADDR__RAW = str
 MCONTR_TOP_16BIT_ADDR_MASK__RAW = str
@@ -1017,6 +1053,7 @@ MCONTR_TOP_STATUS_REG_ADDR = int
 SENSI2C_STATUS_REG_INC__RAW = str
 SDCLK_PHASE = float
 SLEW_CMDA = str
+SENSOR_IMAGE_TYPE0__RAW = str
 MCNTRL_SCANLINE_MODE__TYPE = str
 GPIO_N__RAW = str
 TEST01_NEXT_PAGE__TYPE = str
@@ -1033,12 +1070,13 @@ CAMSYNC_DELAY = int
 BUF_IPCLK2X_SENS2__TYPE = str
 MCNTRL_TEST01_CHN1_MODE__RAW = str
 MULTICLK_PHASE_AXIHP__RAW = str
+QUADRANTS_PXD_HACT_VACT = int
 FFCLK0_IOSTANDARD__RAW = str
 MULTICLK_DIV_XCLK__RAW = str
 DFLT_DQS_TRI_ON_PATTERN__TYPE = str
 MCONTR_PHY_0BIT_DLY_RST__TYPE = str
 TILED_KEEP_OPEN__RAW = str
-MULTICLK_BUF_XCLK__RAW = str
+AXI_WRADDR_LATENCY__TYPE = str
 MULT_SAXI_IRQLEN_ADDR = int
 MULTICLK_BUF_XCLK__TYPE = str
 MCONTR_TOP_0BIT_ADDR__TYPE = str
@@ -1050,9 +1088,12 @@ MCNTRL_SCANLINE_FRAME_SIZE = int
 STATUS_DEPTH = int
 NUM_CYCLES_20__RAW = str
 MCNTRL_SCANLINE_WINDOW_STARTXY__RAW = str
+MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str
 CAMSYNC_EXTERNAL_BIT__RAW = str
+HISTOGRAM_WIDTH = int
 MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str
 HISPI_IBUF_LOW_PWR__RAW = str
+MCNTRL_PS_STATUS_REG_ADDR = int
 SENSI2C_TBL_NBRD__TYPE = str
 SENSI2C_CMD_ACIVE_SDA = int
 MCONTR_PHY_0BIT_ADDR__TYPE = str
@@ -1079,7 +1120,7 @@ CMPRS_CBIT_FOCUS_BITS = int
 LOGGER_CONF_SYN__RAW = str
 CMPRS_COLOR20 = int
 SENSI2C_CMD_TABLE__RAW = str
-SENSIO_DELAYS__TYPE = str
+LAST_BUF_FRAME__RAW = str
 ADDRESS_NUMBER__TYPE = str
 WSEL__TYPE = str
 CMPRS_AFIMUX_CYCBITS__RAW = str
@@ -1137,6 +1178,7 @@ NUM_CYCLES_29__RAW = str
 GPIO_SET_STATUS__TYPE = str
 SENSIO_STATUS_REG_REL__RAW = str
 FFCLK0_CAPACITANCE__RAW = str
+SENSOR12BITS_TDDO1__TYPE = str
 CMDFRAMESEQ_ABS = int
 CMPRS_MONO8 = int
 MULT_SAXI_ADDR__RAW = str
@@ -1146,6 +1188,7 @@ MCNTRL_SCANLINE_MASK__RAW = str
 MULT_SAXI_STATUS_REG__RAW = str
 MCONTR_LINTILE_EN__RAW = str
 SENSI2C_ADDR_MASK__TYPE = str
+SENSOR12BITS_NVLO__RAW = str
 CAMSYNC_EXTERNAL_BIT__TYPE = str
 CMPRS_BASE_INC__RAW = str
 SENS_SYNC_FBITS = int
@@ -1156,6 +1199,7 @@ MEMBRIDGE_CTRL__TYPE = str
 TILED_KEEP_OPEN__TYPE = str
 CMPRS_CBIT_RUN_RST__TYPE = str
 LOGGER_CONF_GPS_BITS__RAW = str
+SENSOR12BITS_TDDO__TYPE = str
 MULTICLK_DIV_SYNC = int
 CLK_STATUS_REG_ADDR = int
 CLK_DIV_PHASE__TYPE = str
@@ -1165,6 +1209,7 @@ CLKFBOUT_USE_FINE_PS__RAW = str
 CMPRS_FRMT_LMARG__RAW = str
 CMDFRAMESEQ_IRQ_BIT__RAW = str
 LOGGER_BIT_DURATION = int
+FCLK1_PERIOD__TYPE = str
 CAMSYNC_MODE__TYPE = str
 CHNBUF_READ_LATENCY__RAW = str
 NUM_CYCLES_12__RAW = str
@@ -1182,6 +1227,7 @@ PXD_IBUF_LOW_PWR__RAW = str
 PXD_DRIVE = int
 MULT_SAXI_BSLOG2__RAW = str
 CLK_CNTRL__TYPE = str
+HISTOGRAM_WIDTH__RAW = str
 GPIO_MASK__RAW = str
 DFLT_REFRESH_ADDR__TYPE = str
 SENS_GAMMA_MODE_REPET__TYPE = str
@@ -1203,6 +1249,7 @@ SENS_SYNC_FBITS__TYPE = str
 HISPI_UNTUNED_SPLIT = str
 MCONTR_TOP_0BIT_ADDR_MASK = int
 HISPI_IBUF_DELAY_VALUE__TYPE = str
+SENSOR12BITS_NGPL = int
 CMDFRAMESEQ_REL = int
 CAMSYNC_POST_MAGIC__TYPE = str
 NUM_CYCLES_29__TYPE = str
@@ -1220,6 +1267,7 @@ MEMCLK_CAPACITANCE__TYPE = str
 MCONTR_BUF0_WR_ADDR__RAW = str
 SENS_GAMMA_MODE_WIDTH = int
 SENS_SS_MODE = str
+SENSOR12BITS_TDDO = int
 CAMSYNC_TRIG_DST = int
 DLY_LANE1_ODELAY__TYPE = str
 CMPRS_AFIMUX_WIDTH__TYPE = str
@@ -1235,6 +1283,7 @@ CMPRS_COLOR18 = int
 LOGGER_CONF_MSG__TYPE = str
 MCNTRL_TILED_MASK__RAW = str
 MULTICLK_DIV_AXIHP__RAW = str
+SENSI2C_CMD_SOFT_SDA__RAW = str
 MCNTRL_TILED_STATUS_REG_CHN2_ADDR = int
 SENSI2C_STATUS_REG_BASE = int
 MCNTRL_TILED_STATUS_CNTRL__RAW = str
@@ -1270,6 +1319,7 @@ SENS_REF_JITTER1 = float
 SENS_REF_JITTER2 = float
 MCNTRL_TILED_FRAME_SIZE__RAW = str
 MULT_SAXI_HALF_BRAM__RAW = str
+SIMUL_AXI_READ_WIDTH__TYPE = str
 DFLT_DQS_TRI_ON_PATTERN__RAW = str
 SLEW_DQ = str
 SENS_GAMMA_MODE_REPET__RAW = str
@@ -1279,6 +1329,7 @@ SLEW_DQS__TYPE = str
 SENSIO_ADDR_MASK = int
 SCANLINE_STARTY = int
 SCANLINE_STARTX = int
+SIMULATE_CMPRS_CMODE1__RAW = str
 FFCLK0_DIFF_TERM__TYPE = str
 HISPI_UNTUNED_SPLIT__TYPE = str
 LD_DLY_CMDA__TYPE = str
@@ -1290,7 +1341,9 @@ SENSI2C_IOSTANDARD__TYPE = str
 REFCLK_FREQUENCY__TYPE = str
 CLKOUT_DIV_PCLK2X__TYPE = str
 MEMBRIDGE_CTRL = int
-CMPRS_TIMEOUT__TYPE = str
+SENSOR_IMAGE_TYPE3__TYPE = str
+HISTOGRAM_LEFT = int
+MULT_SAXI_HALF_BRAM__TYPE = str
 MCONTR_PHY_STATUS_CNTRL = int
 SENSOR_GROUP_ADDR = int
 NUM_CYCLES_14 = int
@@ -1319,6 +1372,7 @@ HISTOGRAM_RADDR1 = int
 HISTOGRAM_RADDR2 = int
 HISTOGRAM_RADDR3 = int
 MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__RAW = str
+HISTOGRAM_LEFT__TYPE = str
 SENS_LENS_AY_MASK__TYPE = str
 SENS_CTRL_IGNORE_EMBED__RAW = str
 READ_BLOCK_OFFSET__TYPE = str
@@ -1330,10 +1384,12 @@ MCNTRL_TEST01_CHN2_MODE = int
 MCNTRL_TILED_WINDOW_WH__TYPE = str
 SS_MOD_PERIOD__RAW = str
 CMPRS_NUM_AFI_CHN__RAW = str
+SENSOR_IMAGE_TYPE3 = str
 MULTICLK_DIV_AXIHP__TYPE = str
 HISPI_DELAY_CLK2__TYPE = str
 MULT_SAXI_ADV_RD = int
-MCNTRL_SCANLINE_FRAME_FULL_WIDTH__RAW = str
+WSEL__RAW = str
+SENSOR_PRIORITY = int
 DLY_PHASE__TYPE = str
 MCONTR_TOP_0BIT_ADDR_MASK__TYPE = str
 MCONTR_TOP_STATUS_REG_ADDR__TYPE = str
@@ -1358,10 +1414,13 @@ WBUF_DLY_DFLT = int
 SENS_JTAG_PROG = int
 MCONTR_PHY_16BIT_WBUF_DELAY__TYPE = str
 FFCLK0_IOSTANDARD = str
+AXI_TASK_HOLD__TYPE = str
 SENS_GAMMA_ADDR_MASK__RAW = str
+SENSOR_IMAGE_TYPE3__RAW = str
 DLY_LANE1_IDELAY__TYPE = str
 SENS_LENS_BY_MASK = int
 DEBUG_MASK__RAW = str
+NUM_INTERRUPTS__RAW = str
 MCNTRL_TEST01_CHN2_MODE__TYPE = str
 MEMBRIDGE_ADDR__RAW = str
 CMPRS_COLOR_SATURATION__RAW = str
@@ -1380,27 +1439,32 @@ DLY_CMDA = long
 SENS_GAMMA_MODE_BAYER = int
 LAST_BUF_FRAME__TYPE = str
 CMPRS_HIFREQ_REG_BASE = int
+FCLK1_PERIOD__RAW = str
 MCONTR_ARBIT_ADDR = int
 MEMBRIDGE_CTRL__RAW = str
 CMPRS_CBIT_RUN_RST__RAW = str
 TABLE_QUANTIZATION_INDEX = int
 NUM_CYCLES_04__TYPE = str
-WSEL__RAW = str
+SENSOR_IMAGE_TYPE2 = str
+SENSOR_IMAGE_TYPE1 = str
+SENSOR_IMAGE_TYPE0 = str
 SENS_CTRL_IGNORE_EMBED = int
 RTC_MASK__TYPE = str
 MCNTRL_TILED_PENDING_CNTR_BITS = int
 NUM_CYCLES_00__TYPE = str
 CMPRS_MASK__RAW = str
-STATUS_SEQ_SHFT__RAW = str
+MEMBRIDGE_CTRL_IRQ__TYPE = str
 MCNTRL_TEST01_MASK__RAW = str
 MCONTR_PHY_16BIT_ADDR_MASK = int
 CAMSYNC_TRIG_DELAY1__TYPE = str
 HIGH_PERFORMANCE_MODE = str
 DQTRI_LAST__RAW = str
 MCNTRL_TEST01_CHN4_STATUS_CNTRL = int
+SIMULATE_CMPRS_CMODE3__TYPE = str
 DFLT_DQM_PATTERN = int
 HISPI_NUMLANES = int
 SENSI2C_CMD_RUN = int
+AXI_WRDATA_LATENCY__RAW = str
 CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__TYPE = str
 NUM_CYCLES_04 = int
 SENS_LENS_C__TYPE = str
@@ -1460,6 +1524,7 @@ INITIALIZE_OFFSET__TYPE = str
 SENSOR_FIFO_DELAY__TYPE = str
 LOGGER_CONF_IMU_BITS__TYPE = str
 IDELAY_VALUE__TYPE = str
+SENSOR_IMAGE_TYPE2__RAW = str
 CMPRS_CBIT_CMODE_JP4DC__TYPE = str
 MULT_SAXI_IRQLEN_ADDR__TYPE = str
 MULT_SAXI_IRQLEN_MASK__TYPE = str
@@ -1479,6 +1544,7 @@ SENSI2C_CTRL = int
 SENS_SYNC_MULT = int
 CLK_ADDR__RAW = str
 SENSIO_CTRL__RAW = str
+HISTOGRAM_WIDTH__TYPE = str
 MCNTRL_TILED_TILE_WHS = int
 NUM_CYCLES_03__RAW = str
 MULT_SAXI_HALF_BRAM = int
@@ -1486,21 +1552,22 @@ DLY_LANE1_DQS_WLV_IDELAY = long
 MULTICLK_PHASE_DLYREF = float
 HIST_SAXI_ADDR_REL = int
 CMDFRAMESEQ_ADDR_BASE = int
-CMPRS_AFIMUX_RADDR1 = int
+SENS_SS_MODE__TYPE = str
 CMPRS_AFIMUX_RADDR0 = int
 CMPRS_FRMT_MBCM1_BITS__RAW = str
 CMPRS_AFIMUX_REG_ADDR1__TYPE = str
 CMPRS_CBIT_FRAMES__TYPE = str
 MCONTR_TOP_0BIT_ADDR = int
 NUM_CYCLES_05__RAW = str
-MEMBRIDGE_MODE = int
 MCNTRL_TILED_FRAME_LAST__TYPE = str
+QUADRANTS_PXD_HACT_VACT__RAW = str
 MCONTR_CMPRS_STATUS_INC__RAW = str
 CMPRS_CBIT_CMODE_JP4DIFFHDR = int
 TABLE_CORING_INDEX__RAW = str
 SENSI2C_CMD_RESET__TYPE = str
 MCONTR_ARBIT_ADDR__TYPE = str
 CAMSYNC_TRIG_DELAY1__RAW = str
+AXI_TASK_HOLD = float
 ADDRESS_NUMBER = int
 SENS_SYNC_LATE__TYPE = str
 MCNTRL_TILED_STATUS_REG_CHN4_ADDR__TYPE = str
@@ -1549,6 +1616,8 @@ CMPRS_CBIT_BAYER_BITS = int
 PXD_SLEW__RAW = str
 MULT_SAXI_STATUS_REG = int
 CLKIN_PERIOD_SENSOR__TYPE = str
+QUADRANTS_PXD_HACT_VACT__TYPE = str
+SENSOR_PRIORITY__TYPE = str
 SENS_LENS_BY__RAW = str
 MCNTRL_PS_CMD__TYPE = str
 SENS_SYNC_MASK__RAW = str
@@ -1591,11 +1660,11 @@ GPIO_SLEW__RAW = str
 MULTICLK_PHASE_DLYREF__TYPE = str
 TEST01_START_FRAME__RAW = str
 CMDFRAMESEQ_ABS__RAW = str
-CMPRS_AFIMUX_SA_LEN__RAW = str
+FRAME_WIDTH_ROUND_BITS__TYPE = str
 BUF_IPCLK2X_SENS0__RAW = str
 MCONTR_BUF4_WR_ADDR__RAW = str
-CLK_STATUS__TYPE = str
-CMPRS_COLOR20__TYPE = str
+DFLT_DQM_PATTERN__RAW = str
+CMPRS_CSAT_CB__TYPE = str
 T_REFI__TYPE = str
 MCONTR_CMD_WR_ADDR__TYPE = str
 SENSI2C_CMD_SOFT_SCL__TYPE = str
@@ -1607,6 +1676,7 @@ MCNTRL_TEST01_MASK = int
 TEST01_NEXT_PAGE__RAW = str
 HIST_SAXI_MODE_ADDR_MASK__RAW = str
 FFCLK1_IBUF_LOW_PWR__TYPE = str
+SENSOR12BITS_NVLO__TYPE = str
 MCONTR_LINTILE_EXTRAPG__TYPE = str
 NUM_CYCLES_06__TYPE = str
 SCANLINE_STARTX__RAW = str
@@ -1623,8 +1693,9 @@ WRITELEV_OFFSET__RAW = str
 READ_PATTERN_OFFSET = int
 CLK_PHASE__TYPE = str
 SENSOR_16BIT_BIT = int
-MCNTRL_PS_STATUS_REG_ADDR = int
+SENSIO_DELAYS__TYPE = str
 SENS_CTRL_EXT_CLK__RAW = str
+WOI_HEIGHT = int
 LOGGER_PAGE_GPS__TYPE = str
 T_REFI = int
 HIST_CONFIRM_WRITE__TYPE = str
@@ -1664,6 +1735,7 @@ HIGH_PERFORMANCE_MODE__RAW = str
 DFLT_DQM_PATTERN__TYPE = str
 STATUS_ADDR__TYPE = str
 MCONTR_PHY_0BIT_CMDA_EN = int
+WOI_WIDTH = int
 CMPRS_AFIMUX_WIDTH__RAW = str
 BUF_CLK1X_PCLK2X = str
 MCNTRL_TEST01_CHN4_MODE = int
@@ -1679,6 +1751,7 @@ INITIALIZE_OFFSET__RAW = str
 CMD_DONE_BIT__RAW = str
 DEBUG_STATUS_REG_ADDR__RAW = str
 CMPRS_AFIMUX_RST__RAW = str
+SENSOR12BITS_TDDO__RAW = str
 CAMSYNC_TRIG_DST__RAW = str
 MCONTR_TOP_16BIT_REFRESH_PERIOD__TYPE = str
 CAMSYNC_TRIG_DELAY3__TYPE = str
@@ -1686,6 +1759,7 @@ FRAME_START_ADDRESS__RAW = str
 IPCLK_PHASE = float
 SENSI2C_CTRL_RADDR = int
 HIST_SAXI_MODE_ADDR_REL__RAW = str
+AXI_WRDATA_LATENCY = int
 SENS_CTRL_QUADRANTS_EN = int
 MCNTRL_SCANLINE_WINDOW_WH__RAW = str
 MULTICLK_PHASE_FB__TYPE = str
@@ -1703,11 +1777,12 @@ MEMCLK_IOSTANDARD = str
 DLY_LANE1_ODELAY__RAW = str
 SENSI2C_IBUF_LOW_PWR__RAW = str
 SENSI2C_STATUS_REG_REL = int
-MULT_SAXI_HALF_BRAM__TYPE = str
+AXI_RDADDR_LATENCY__RAW = str
 SENSOR_CTRL_ADDR_MASK = int
 NUM_CYCLES_16__TYPE = str
 MEMBRIDGE_LO_ADDR64__TYPE = str
 CMDFRAMESEQ_MASK__RAW = str
+SENSOR12BITS_TMD__TYPE = str
 SENS_CTRL_LD_DLY__TYPE = str
 MCONTR_TOP_16BIT_ADDR__TYPE = str
 PXD_SLEW = str
@@ -1727,6 +1802,7 @@ SENSIO_JTAG = int
 DLY_LD = int
 CMPRS_CBIT_FRAMES_SINGLE = int
 SENS_SYNC_LATE = int
+MEMBRIDGE_CTRL_IRQ = int
 CMDFRAMESEQ_CTRL__RAW = str
 SENSIO_DELAYS = int
 MULTICLK_BUF_SYNC = str
@@ -1766,8 +1842,10 @@ LOGGER_STATUS_MASK = int
 MULTICLK_PHASE_XCLK__TYPE = str
 DFLT_DQ_TRI_ON_PATTERN__RAW = str
 HISPI_CAPACITANCE = str
+HISTOGRAM_START_PAGE__RAW = str
 CONTROL_ADDR_MASK = int
 LOGGER_PERIOD = int
+MEMCLK_PERIOD__RAW = str
 MCONTR_BUF0_WR_ADDR = int
 MCNTRL_PS_STATUS_REG_ADDR__RAW = str
 LOGGER_STATUS_MASK__RAW = str
@@ -1790,6 +1868,7 @@ SENS_REF_JITTER2__RAW = str
 SCANLINE_EXTRA_PAGES__RAW = str
 CMDSEQMUX_STATUS__RAW = str
 MCONTR_PHY_0BIT_SDRST_ACT__RAW = str
+SENSOR_IMAGE_TYPE0__TYPE = str
 CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__RAW = str
 DIVCLK_DIVIDE_PCLK = int
 MCNTRL_PS_MASK = int
@@ -1819,6 +1898,7 @@ SENS_LENS_SCALES__TYPE = str
 SENS_LENS_COEFF__TYPE = str
 LOGGER_STATUS__RAW = str
 SENS_JTAG_TMS__RAW = str
+FRAME_WIDTH_ROUND_BITS__RAW = str
 FFCLK0_IBUF_LOW_PWR__RAW = str
 SENS_CTRL_MRST = int
 MCNTRL_SCANLINE_FRAME_LAST__TYPE = str
@@ -1826,6 +1906,7 @@ MCONTR_SENS_STATUS_BASE__RAW = str
 MCNTRL_TEST01_CHN3_MODE__TYPE = str
 MCONTR_BUF2_RD_ADDR__TYPE = str
 SENS_SYNC_RADDR__RAW = str
+SENS_HIGH_PERFORMANCE_MODE__RAW = str
 MCNTRL_TEST01_CHN2_STATUS_CNTRL = int
 CLKFBOUT_PHASE_SENSOR__TYPE = str
 SENSOR_HIST_NRST_BITS__TYPE = str
@@ -1834,12 +1915,14 @@ RTC_STATUS_REG_ADDR__TYPE = str
 SENS_JTAG_TCK__TYPE = str
 MCNTRL_TILED_FRAME_SIZE__TYPE = str
 CMPRS_AFIMUX_REG_ADDR1__RAW = str
+WOI_HEIGHT__RAW = str
 SENS_LENS_COEFF = int
 MULTICLK_PHASE_XCLK__RAW = str
 LOGGER_BIT_DURATION__RAW = str
 MCONTR_WR_MASK__TYPE = str
 SENS_LENS_C__RAW = str
 CMDFRAMESEQ_ADDR_BASE__TYPE = str
+AXI_WRDATA_LATENCY__TYPE = str
 SENS_GAMMA_HEIGHT01 = int
 RTC_SET_SEC__RAW = str
 MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__TYPE = str
@@ -1858,6 +1941,7 @@ CMPRS_INTERRUPTS = int
 SENSI2C_SLEW__RAW = str
 MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
 CMDSEQMUX_MASK = int
+MCNTRL_SCANLINE_PENDING_CNTR_BITS__RAW = str
 MEMCLK_CAPACITANCE__RAW = str
 DQTRI_FIRST = int
 DLY_LANE0_DQS_WLV_IDELAY__TYPE = str
@@ -1865,6 +1949,7 @@ CAMSYNC_TRIG_DELAY0 = int
 CAMSYNC_TRIG_DELAY1 = int
 MCNTRL_SCANLINE_STATUS_CNTRL__RAW = str
 CAMSYNC_TRIG_DELAY3 = int
+SIMUL_AXI_READ_WIDTH__RAW = str
 MCONTR_SENS_STATUS_INC = int
 CAMSYNC_TRIGGERED_BIT__TYPE = str
 SENS_GAMMA_MODE_TRIG__TYPE = str
@@ -1889,6 +1974,7 @@ TABLE_CORING_INDEX__TYPE = str
 HISTOGRAM_RADDR1__RAW = str
 SENSI2C_CMD_TAND__TYPE = str
 MCONTR_LINTILE_EXTRAPG_BITS__RAW = str
+SENS_BANDWIDTH = str
 MCNTRL_SCANLINE_MODE__RAW = str
 LOGGER_BIT_HALF_PERIOD__TYPE = str
 FRAME_START_ADDRESS_INC__RAW = str
@@ -1940,6 +2026,8 @@ SENS_PHASE_WIDTH__RAW = str
 SENS_REF_JITTER2__TYPE = str
 FFCLK0_IBUF_LOW_PWR = str
 DFLT_DQ_TRI_ON_PATTERN__TYPE = str
+FRAME_WIDTH_ROUND_BITS = int
+LD_DLY_LANE1_IDELAY__TYPE = str
 CMPRS_AFIMUX_MODE__TYPE = str
 DQTRI_FIRST__TYPE = str
 MCNTRL_SCANLINE_FRAME_SIZE__RAW = str
@@ -1953,6 +2041,7 @@ DLY_CMDA__TYPE = str
 CLKFBOUT_MULT__TYPE = str
 DEBUG_MASK = int
 MCONTR_PHY_0BIT_CMDA_EN__RAW = str
+STATUS_SEQ_SHFT__RAW = str
 IDELAY_VALUE = int
 DQSTRI_LAST__TYPE = str
 HISTOGRAM_RADDR2__TYPE = str
@@ -1968,7 +2057,7 @@ MCONTR_TOP_0BIT_REFRESH_EN__RAW = str
 SENSI2C_TBL_RAH = int
 SENSI2C_ADDR_MASK__RAW = str
 SENS_HIGH_PERFORMANCE_MODE__TYPE = str
-MCONTR_LINTILE_KEEP_OPEN__TYPE = str
+TEST01_SUSPEND__TYPE = str
 NUM_CYCLES_15__RAW = str
 DLY_DQ_IDELAY = long
 CLKFBOUT_USE_FINE_PS = int
@@ -1998,7 +2087,7 @@ DLY_DQ_ODELAY__RAW = str
 MCNTRL_TILED_PENDING_CNTR_BITS__RAW = str
 CMPRS_CORING_BITS = int
 CMDFRAMESEQ_MASK__TYPE = str
-FFCLK1_IOSTANDARD = str
+SENS_JTAG_TMS__TYPE = str
 CLK_PHASE__RAW = str
 MCONTR_PHY_0BIT_DLY_RST = int
 GPIO_MASK__TYPE = str
@@ -2021,6 +2110,7 @@ CMPRS_JP4 = int
 CAMSYNC_CHN_EN_BIT = int
 SENSIO_STATUS_REG_REL__TYPE = str
 MULTICLK_BUF_XCLK = str
+HISTOGRAM_START_PAGE__TYPE = str
 MCNTRL_SCANLINE_MODE = int
 DLY_LANE0_IDELAY = long
 MCNTRL_PS_CMD = int
@@ -2039,7 +2129,7 @@ DFLT_CHN_EN = int
 GPIO_STATUS_REG_ADDR__RAW = str
 DLY_DQS_ODELAY = long
 SENSOR_CHN_EN_BIT__RAW = str
-SENS_SS_MODE__TYPE = str
+CMPRS_AFIMUX_RADDR1 = int
 CAMSYNC_TRIG_SRC__TYPE = str
 SENSI2C_CMD_FIFO_RD = int
 LOGGER_CONF_IMU__TYPE = str
@@ -2048,6 +2138,7 @@ SENS_LENS_AY__RAW = str
 SS_EN = str
 SENSI2C_CMD_TAND__RAW = str
 WINDOW_HEIGHT__TYPE = str
+SENSOR_IMAGE_TYPE2__TYPE = str
 IBUF_LOW_PWR__TYPE = str
 CLK_DIV_PHASE = float
 MCNTRL_TEST01_CHN4_STATUS_CNTRL__RAW = str
@@ -2060,7 +2151,7 @@ NUM_CYCLES_11__RAW = str
 FFCLK1_CAPACITANCE__RAW = str
 SENSI2C_DRIVE__RAW = str
 CMPRS_CBIT_CMODE_MONO1__TYPE = str
-SENSI2C_CMD_SOFT_SDA__RAW = str
+SENS_LENS_C = int
 SENSOR_CTRL_ADDR_MASK__RAW = str
 DFLT_CHN_EN__RAW = str
 NUM_CYCLES_LOW_BIT = int
@@ -2108,6 +2199,7 @@ DFLT_WBUF_DELAY = int
 CONTROL_RBACK_ADDR_MASK__RAW = str
 AXI_WR_ADDR_BITS__TYPE = str
 RTC_SET_STATUS = int
+SENSOR_HIST_EN_BITS__RAW = str
 MULT_SAXI_ADV_WR__TYPE = str
 CMPRS_AFIMUX_STATUS_CNTRL__RAW = str
 FRAME_FULL_WIDTH = int
@@ -2159,13 +2251,14 @@ MCONTR_LINTILE_REPEAT__RAW = str
 MCONTR_TOP_16BIT_REFRESH_PERIOD = int
 CMPRS_INTERRUPTS__TYPE = str
 MCNTRL_TILED_FRAME_FULL_WIDTH__TYPE = str
+WOI_HEIGHT__TYPE = str
 STATUS_SEQ_SHFT__TYPE = str
 MCONTR_CMPRS_BASE = int
 DEBUG_SET_STATUS__TYPE = str
-MCNTRL_SCANLINE_PENDING_CNTR_BITS__RAW = str
+HISTOGRAM_START_PAGE = int
 RTC_SEC_USEC_ADDR__RAW = str
 MCNTRL_PS_ADDR = int
-SENS_BANDWIDTH = str
+HISTOGRAM_HEIGHT__RAW = str
 MEMCLK_IBUF_LOW_PWR = str
 HISPI_DELAY_CLK3__RAW = str
 CAMSYNC_TRIG_DST__TYPE = str
@@ -2186,6 +2279,7 @@ SENSI2C_REL_RADDR__RAW = str
 MCONTR_ARBIT_ADDR__RAW = str
 MCONTR_LINTILE_EN__TYPE = str
 SENSI2C_REL_RADDR__TYPE = str
+AXI_WRADDR_LATENCY__RAW = str
 GPIO_DRIVE = int
 HISPI_MSB_FIRST__RAW = str
 SENS_LENS_SCALES = int
@@ -2205,12 +2299,14 @@ HISPI_DELAY_CLK2__RAW = str
 SS_MOD_PERIOD__TYPE = str
 TILE_HEIGHT = int
 MULT_SAXI_MASK__RAW = str
+SENSOR12BITS_TMD = int
 MCONTR_CMPRS_STATUS_BASE__TYPE = str
 NUM_CYCLES_10__RAW = str
 SENS_LENS_FAT0_OUT__TYPE = str
 DEBUG_SHIFT_DATA__RAW = str
 SENSOR_16BIT_BIT__TYPE = str
 SENS_NUM_SUBCHN = int
+FRAME_HEIGHT_BITS = int
 MCONTR_BUF0_WR_ADDR__TYPE = str
 SENSOR_CHN_EN_BIT__TYPE = str
 CMPRS_COLOR18__RAW = str

py393/x393_export_c.py

@@ -334,10 +334,16 @@ class X393ExportC(object):
                                  data =      self._enc_membridge_cmd(),
                                  name =      "x393_membridge_cmd",  typ="wo",
                                  frmt_spcs = frmt_spcs)
+        """
         stypedefs += self.get_typedef32(comment =   "Cache mode for membridge",
                                  data =      self._enc_membridge_mode(),
                                  name =      "x393_membridge_mode",  typ="wo",
                                  frmt_spcs = frmt_spcs)
+        """                                 
+        stypedefs += self.get_typedef32(comment =   "Interrupt handling commands for Membridge module",
+                                 data =      self._enc_membridge_ctrl_irq(),
+                                 name =      "x393_membridge_ctrl_irq",  typ="wo",
+                                 frmt_spcs = frmt_spcs)
         stypedefs += self.get_typedef32(comment =   "Address in 64-bit words",
                                  data =      self._enc_u29(),
                                  name =      "u29",  typ="wo",
@@ -738,7 +744,7 @@ class X393ExportC(object):
             (("X393_MEMBRIDGE_START64",                  c, vrlg.MEMBRIDGE_START64 +               ba, 0, None, "u29", "wo",                               "start of transfer offset to system memory range in QWORDs (4 LSBs==0)")),
             (("X393_MEMBRIDGE_LEN64",                    c, vrlg.MEMBRIDGE_LEN64 +                 ba, 0, None, "u29", "wo",                               "Full length of transfer in QWORDs")),
             (("X393_MEMBRIDGE_WIDTH64",                  c, vrlg.MEMBRIDGE_WIDTH64 +               ba, 0, None, "u29", "wo",                               "Frame width in QWORDs (last xfer in each line may be partial)")),
-            (("X393_MEMBRIDGE_MODE",                     c, vrlg.MEMBRIDGE_MODE +                  ba, 0, None, "x393_membridge_mode", "wo",               "AXI cache mode"))]
+            (("X393_MEMBRIDGE_CTRL_IRQ",                 c, vrlg.MEMBRIDGE_CTRL_IRQ +              ba, 0, None, "x393_membridge_ctrl_irq", "wo",           "Membridge IRQ control"))]
 
         ba = vrlg.MCNTRL_PS_ADDR
         ia = 0
@@ -1777,6 +1783,8 @@ class X393ExportC(object):
         dw=[]
         dw.append(("wresp_conf",       0, 8,0,  "Number of 64-bit words confirmed through axi b channel (low bits)"))
         dw.append(("axi_arw_requested",8, 8,0,  "Number of 64-bit words to be read/written over axi queued to AR/AW channels (low bits)"))
+        dw.append(("irq_r",           16, 1,0,  "Interrupt request (before mask)"))
+        dw.append(("irq_m",           17, 1,0,  "Interrupt enable (0 - disable)"))
         dw.append(("busy",           24,  1,0,  "Membridge operation in progress"))
         dw.append(("done",           25,  1,0,  "Membridge operation finished"))
         dw.append(("seq_num",        26,  6,0,  "Sequence number"))
@@ -1828,11 +1836,18 @@ class X393ExportC(object):
         dw.append(("enable",           0, 1,0,  "enable membridge"))
         dw.append(("start_reset",      1, 2,0,  "1 - start (from current address), 3 - start from reset address"))
         return dw
+    """
     def _enc_membridge_mode(self):
         dw=[]
         dw.append(("axi_cache",        0, 4,3,  "AXI CACHE value (ignored by Zynq)"))
         dw.append(("debug_cache",      4, 1,0,  "0 - normal operation, 1 debug (replace data)"))
         return dw
+    """    
+    def _enc_membridge_ctrl_irq(self):
+        dw=[]
+        dw.append(("interrupt_cmd",    0, 2,   0, "IRQ control commands - 0: nop, 1: clear interrupt status, 2: disable interrupt, 3: enable interrupt"))
+        return dw
+    
     def _enc_u29(self):
         dw=[]
         dw.append(("addr64",           0,29,0,  "Address/length in 64-bit words (<<3 to get byte address"))

py393/x393_mcntrl_membridge.py

@@ -187,7 +187,7 @@ class X393McntrlMembridge(object):
                          start64,                       # input [28:0] start64;  # relative start address of the transfer (set to 0 when writing lo_addr64)
                          lo_addr64 =       None,        # input [28:0] lo_addr64; # low address of the system memory range, in 64-bit words 
                          size64 =          None,        # input [28:0] size64;    # size of the system memory range in 64-bit words
-                         cache = 0x3,
+#                         cache = 0x3,
                          quiet=1):
         '''
         Set up membridge parameters for data transfer
@@ -196,8 +196,6 @@ class X393McntrlMembridge(object):
         @param start64 relative start address of the transfer (normally 0)
         @param lo_addr64 low address of the system memory range, in 64-bit words 
         @param size64  size of the system memory range in 64-bit words
-        @param cache bits[3:0] - ARCHACHE, AWCACHE (default 0x3), bit[4] - debug mode, when each 64-bit word high 16 bits is replaced with:
-               bits[63:60] - transfer id (incrementing each new transfer), bits[59:58]==0, [57:56] - mchtrl page number, [45:48] FIFO count (wcount)
         @quiet - reduce output (>=1 - silent)
         '''
         if lo_addr64 is None:
@@ -212,7 +210,7 @@ class X393McntrlMembridge(object):
         self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_START64,    start64);    
         self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_LEN64,      len64);    
         self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_WIDTH64,    width64);    
-        self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_MODE,       cache);    
+#        self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_MODE,       cache);    
 
     def membridge_start(self,
                         cont=False,
@@ -249,7 +247,7 @@ class X393McntrlMembridge(object):
                       lo_addr64 =         None,                     # input [28:0] lo_addr64;        # low address of the system memory range, in 64-bit words 
                       size64 =            None,                     # input [28:0] size64;           # size of the system memory range in 64-bit words
                       cont =              False,                    # input        continue;         # 0 start from start64, 1 - continue from where it was
-                      cache =             0x3,
+#                      cache =             0x3,
                       wait_ready =        False,
                       quiet=1):
         '''
@@ -265,8 +263,6 @@ class X393McntrlMembridge(object):
         @param lo_addr64 start of the system memory buffer, in 8-bytes (byte_address >>3), 29 bits 
         @param size64 size of the transfer buffer in the system memory, in 8-bytes. Transfers will roll over to lo_addr64. 29 bits.
         @param cont True: continue from  the same address in the system memory, where the previous transfer stopped. False - start from lo_addr64+start64
-        @param cache bits[3:0] - ARCHACHE, AWCACHE (default 0x3), bit[4] - debug mode, when each 64-bit word high 16 bits is replaced with:
-               bits[63:60] - transfer id (incrementing each new transfer), bits[59:58]==0, [57:56] - mchtrl page number, [45:48] FIFO count (wcount)
         @param wait_ready poll status to see if the command finished
         @param quiet Reduce output
         '''
@@ -297,10 +293,10 @@ class X393McntrlMembridge(object):
         if quiet <2:
             print("====== test_afi_rw: write=%s, frame_start=0x%x, window_full_width=%d, window_width=%d, window_height=%d, window_left=%d, window_top=%d"%(
                                       str(write_ddr3),  frame_start_addr, window_full_width,   window_width, window_height, window_left, window_top));
-            print("len64=0x%x,  width64=0x%x, start64=0x%x, lo_addr64=0x%x, size64=0x%x, cache=0x%x"%(
+            print("len64=0x%x,  width64=0x%x, start64=0x%x, lo_addr64=0x%x, size64=0x%x"%(
                   (window_width << 1)*window_height,
                   (window_width << 1),
-                  start64, lo_addr64, size64,cache))
+                  start64, lo_addr64, size64))
         '''    
         mode=   func_encode_mode_scanline(
                     0, # extra_pages,
@@ -337,7 +333,7 @@ class X393McntrlMembridge(object):
             start64,
             lo_addr64,
             size64,
-            cache,
+#            cache,
             quiet)
         self.membridge_start (cont)         
 # just wait done (default timeout = 10 sec)

py393/x393_sens_cmprs.py

@@ -1632,7 +1632,7 @@ class X393SensCmprs(object):
     def setup_membridge_sensor(self,
                                num_sensor      = 0,
                                write_mem       = False,
-                               cache_mode      = 0x3, # 0x13 for debug mode
+#                               cache_mode      = 0x3, # 0x13 for debug mode
                                window_width    = 2592,
                                window_height   = 1944,
                                window_left     = 0,
@@ -1645,7 +1645,6 @@ class X393SensCmprs(object):
         Configure membridge to read/write to the sensor 0 area in the video memory
         @param num_sensor - sensor port number (0..3)
         @param write_mem - Write to video memory (Flase - read from)
-        @param cache_mode - lower 4 bits, axi cache mode (default 3), bit [4] - debug mode (replace data)
         @param window_width -  window width in pixels (bytes) (TODO: add 16-bit mode)
         @param window_height - window height in lines
         @param window_left -   window left margin
@@ -1692,7 +1691,6 @@ class X393SensCmprs(object):
             print ("membridge start =           0x%x"%(membridge_start))
             print ("membridge end =             0x%x"%(membridge_end))
             print ("membridge size =            %d bytes"%(membridge_end - membridge_start))
-            print ("cache/debug mode =          0x%x bytes"%(cache_mode))
             
             
         # Copied from setup_sensor    
@@ -1762,7 +1760,7 @@ class X393SensCmprs(object):
                                            start64 =   0,
                                            lo_addr64 = membridge_start // 8,
                                            size64 =    (membridge_end - membridge_start) // 8,
-                                           cache =     cache_mode,
+#                                           cache =     cache_mode,
                                            quiet = 1 - verbose)
         
         self.x393Membridge.membridge_en( # enable membridge

x393.v

@@ -549,6 +549,7 @@ module  x393 #(
    
     wire                      [3:0] cmprs_irq;         // compressor done, data confirmed written to memory)
     wire                      [3:0] mult_saxi_irq;     // interrupts from mult_saxi channels
+    wire                            membridge_irq;     // interrupt from membridge done
    
 // Compressor frame synchronization
   
@@ -1473,7 +1474,8 @@ assign axi_grst = axi_rst_pre;
         .MEMBRIDGE_START64      (MEMBRIDGE_START64),
         .MEMBRIDGE_LEN64        (MEMBRIDGE_LEN64),
         .MEMBRIDGE_WIDTH64      (MEMBRIDGE_WIDTH64),
-        .MEMBRIDGE_MODE         (MEMBRIDGE_MODE),
+//        .MEMBRIDGE_MODE         (MEMBRIDGE_MODE),
+        .MEMBRIDGE_CTRL_IRQ     (MEMBRIDGE_CTRL_IRQ),
         .MEMBRIDGE_STATUS_REG   (MEMBRIDGE_STATUS_REG),
         .FRAME_HEIGHT_BITS      (FRAME_HEIGHT_BITS),
         .FRAME_WIDTH_BITS       (FRAME_WIDTH_BITS)
@@ -1490,6 +1492,7 @@ assign axi_grst = axi_rst_pre;
         .status_ad              (status_membridge_ad[7:0]), // output[7:0] 
         .status_rq              (status_membridge_rq),      // output
         .status_start           (status_membridge_start),   // input
+        .irq                    (membridge_irq),            // output
         .frame_start_chn        (frame_start_chn1),         // output
         .next_page_chn          (next_page_chn1),           // output
         .cmd_wrmem              (cmd_wrmem_chn1),           // input
@@ -2955,7 +2958,8 @@ sata_ahci_top sata_top(
             cmprs_irq[3:0],      // [15:12] Compressor done interrupts          SPI: Numbers [91:88]
             frseq_irq[3:0],      // [11: 8] Frame sync interrupts               SPI: Numbers [87:84]
             mult_saxi_irq[3:0],  // [ 7: 4] interrupts from mult_saxi channels  SPI: Numbers [68:65]
-            3'b0,                // [ 3: 1] Reserved                            SPI: Numbers [65:63]
+            membridge_irq,       //     [3] interrupts from membridge module    SPI: Number     [65]    
+            2'b0,                // [ 2: 1] Reserved                            SPI: Numbers [64:63]
             sata_irq             // [    0] AHCI (SATA ) interrupt              SPI: Number     [62]
             }),                  // Interrupts, PL to PS [19:0], input
     .IRQP2F(),                   // Interrupts, PL to PS [28:0], output