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Commit 35cce7c8 authored by Andrey Filippov's avatar Andrey Filippov
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Added interrupts to membridge module

parent 26c2cba0
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Showing with 211 additions and 80 deletions
axi/membridge.v
View file @ 35cce7c8
......@@ -48,7 +48,8 @@ module membridge#(
parameter MEMBRIDGE_START64= 'h4, // start address relative to lo_addr
parameter MEMBRIDGE_LEN64= 'h5, // full length of transfer in 64-bit words
parameter MEMBRIDGE_WIDTH64= 'h6, // frame width in 64-bit words (partial last page in each line)
parameter MEMBRIDGE_MODE= 'h7, // bits [3:0] - *_cache, bit [4] - cache debug
// parameter MEMBRIDGE_MODE= 'h7, // bits [3:0] - *_cache, bit [4] - cache debug
parameter MEMBRIDGE_CTRL_IRQ= 'h7, // offset for IRQ control register (4 dibits): 0 - nop, 1 reset, 2 - disable, 3 - enable
parameter MEMBRIDGE_STATUS_REG= 'h3b,
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height bits
parameter FRAME_WIDTH_BITS= 13
......@@ -70,6 +71,7 @@ module membridge#(
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address)
output irq, // Masked interrupt request (level, resettable)
// mcntrl_linear_rw.v interface
output frame_start_chn, // input
output next_page_chn, // input
......@@ -182,14 +184,15 @@ module membridge#(
wire set_size64_w;
wire set_start64_w;
wire set_len64_w;
wire set_mode_w;
wire set_irq_w;
wire set_width64_w;
reg [4:0] mode_reg_mclk;
reg [4:0] mode_reg;
// reg [4:0] mode_reg_mclk;
// reg [4:0] mode_reg;
wire cache_debug;
assign cache_debug=mode_reg[4];
assign afi_awcache = mode_reg[3:0]; // 4'h3;
assign afi_arcache = mode_reg[3:0]; // 4'h3;
// Disabling cache modes and debug - cache modes are not supported in Zynq
assign cache_debug= 0; // mode_reg[4];
assign afi_awcache = 4'h3; // mode_reg[3:0]; // 4'h3;
assign afi_arcache = 4'h3; // mode_reg[3:0]; // 4'h3;
assign set_ctrl_w = cmd_we && (cmd_a== MEMBRIDGE_CTRL);
assign set_lo_addr64_w = cmd_we && (cmd_a== MEMBRIDGE_LO_ADDR64);
assign set_size64_w = cmd_we && (cmd_a== MEMBRIDGE_SIZE64);
......@@ -197,7 +200,7 @@ module membridge#(
assign set_len64_w = cmd_we && (cmd_a== MEMBRIDGE_LEN64);
assign set_width64_w = cmd_we && (cmd_a== MEMBRIDGE_WIDTH64);
assign set_status_w = cmd_we && (cmd_a== MEMBRIDGE_STATUS_CNTRL);
assign set_mode_w = cmd_we && (cmd_a== MEMBRIDGE_MODE);
assign set_irq_w = cmd_we && (cmd_a== MEMBRIDGE_CTRL_IRQ);
reg [28:0] lo_addr64_mclk;
reg [28:0] size64_mclk;
reg [28:0] start64_mclk;
......@@ -223,7 +226,12 @@ module membridge#(
wire debug_w_ready;
assign debug_aw_ready = (!debug_aw_allowed[6] && (|debug_aw_allowed[5:0])) || debug_disable; // > 0
assign debug_w_ready = (!debug_w_allowed[8] && (|debug_w_allowed [7:0]) &&((|debug_w_allowed [7:1]) || !(|debug_bufrd_rd))) || debug_disable; // > 0
`endif
`endif
reg irq_r = 0;
reg irq_m = 0;
wire done_mclk; // pre_done && !done @ posedge mclk
assign irq = irq_r && irq_m;
//cmd_wrmem
always @ (posedge mclk) begin
if (set_lo_addr64_w) lo_addr64_mclk <= {cmd_data[28:4],4'b0}; // align to 16-bursts
......@@ -244,8 +252,8 @@ module membridge#(
if (mrst) start_mclk <= 0;
else start_mclk <= set_ctrl_w & cmd_data[1];
if (mrst) mode_reg_mclk <= 5'h03;
else if (set_mode_w) mode_reg_mclk <= cmd_data[4:0];
// if (mrst) mode_reg_mclk <= 5'h03;
// else if (set_mode_w) mode_reg_mclk <= cmd_data[4:0];
`ifdef MEMBRIDGE_DEBUG_READ
if (mrst) debug_aw_mclk <= 0;
......@@ -259,9 +267,19 @@ module membridge#(
`endif
end
// IRQ-related
always @ (posedge mclk) begin
if (mrst) irq_m <= 0;
else if (set_irq_w && cmd_data[1]) irq_m <= cmd_data[0];
if (mrst) irq_r <= 0;
else if (done_mclk) irq_r <= 1;
else if (set_irq_w && (cmd_data[1:0] == 1)) irq_r <= 0;
end
// syncronize mclk ->hclk
reg [28:0] lo_addr64;
......@@ -310,7 +328,7 @@ module membridge#(
size64 <= size64_mclk;
start64 <= start64_mclk;
len64 <= len64_mclk;
mode_reg <= mode_reg_mclk;
// mode_reg <= mode_reg_mclk;
last_in_line64 <= width64_minus1_mclk;
wr_mode <= cmd_wrmem;
rdwr_reset_addr <= rdwr_reset_addr_mclk;
......@@ -348,6 +366,9 @@ module membridge#(
pulse_cross_clock frame_done_i (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(frame_done_chn), .out_pulse(frame_done),.busy());
pulse_cross_clock reset_page_wr_i (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(xfer_reset_page_wr), .out_pulse(reset_page_wr),.busy());
//hclk -> mclk
pulse_cross_clock done_mclk_i (.rst(hrst), .src_clk(hclk), .dst_clk(mclk), .in_pulse(pre_done &&!done), .out_pulse(done_mclk),.busy());
`ifdef MEMBRIDGE_DEBUG_READ
// mclk -> hclk, debug-only
pulse_cross_clock debug_aw_i (.rst(hrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(debug_aw_mclk), .out_pulse(debug_aw),.busy());
......@@ -744,9 +765,9 @@ module membridge#(
status_generate #(
.STATUS_REG_ADDR (MEMBRIDGE_STATUS_REG),
`ifdef MEMBRIDGE_DEBUG_READ
.PAYLOAD_BITS (18) // 2) // With debug
.PAYLOAD_BITS (20) // 2) // With debug
`else
.PAYLOAD_BITS (18) //2)
.PAYLOAD_BITS (20) //2)
`endif
) status_generate_i (
.rst (1'b0), // rst), // input
......@@ -755,9 +776,9 @@ module membridge#(
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
`ifdef MEMBRIDGE_DEBUG_READ
.status ({debug_aw_allowed, debug_w_allowed, done, busy}), // input[25:0]
.status ({irq_m, irq_r, debug_aw_allowed[7:0], debug_w_allowed[7:0], done, busy}), // input[25:0]
`else
.status ({axi_arw_requested, wresp_conf, done, busy}), // input[25:0]
.status ({irq_m, irq_r, axi_arw_requested[7:0], wresp_conf[7:0], done, busy}), // input[25:0]
`endif
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
......
axi/mult_saxi_wr.v
View file @ 35cce7c8
......@@ -47,7 +47,7 @@ module mult_saxi_wr #(
parameter MULT_SAXI_CNTRL_ADDR = 'h73c, // ..'h73e
parameter MULT_SAXI_CNTRL_MODE = 'h0, // 'h73c offset for mode register
parameter MULT_SAXI_CNTRL_STATUS = 'h1, // 'h73d offset for status control register
parameter MULT_SAXI_CNTRL_IRQ = 'h2, // 'h73e offset for IRQ contgrol register (4 dibits): 0 - nop, 1 reset, 2 - disable, 3 - enable
parameter MULT_SAXI_CNTRL_IRQ = 'h2, // 'h73e offset for IRQ control register (4 dibits): 0 - nop, 1 reset, 2 - disable, 3 - enable
parameter MULT_SAXI_POINTERS_REG = 'h34, //..'h37 uses 4 consecutive locations
parameter MULT_SAXI_STATUS_REG = 'h3c, //status and IRQ requests and masks
parameter MULT_SAXI_HALF_BRAM = 1, // 0 - use full 36Kb BRAM for the buffer, 1 - use just half
......
includes/tasks_tests_memory.vh
View file @ 35cce7c8
......@@ -142,7 +142,7 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
input [28:0] size64; // size of the system memory range in 64-bit words
input continue; // 0 start from start64, 1 - continue from where it was
input disable_need;
input [4:0] cache_mode; // 'h3 - normal, 'h13 - debug
input [4:0] cache_mode; // 'h3 - normal, 'h13 - debug - disabled
input rpt;
......@@ -193,8 +193,8 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
(window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0}, // width64,
start64,
lo_addr64,
size64,
cache_mode);
size64);
// cache_mode);
membridge_start (continue);
`ifdef MEMBRIDGE_DEBUG_READ
// debugging
......
includes/x393_parameters.vh
View file @ 35cce7c8
......@@ -328,7 +328,8 @@
parameter MEMBRIDGE_START64= 'h4, // start address relative to lo_addr
parameter MEMBRIDGE_LEN64= 'h5, // full length of transfer in 64-bit words
parameter MEMBRIDGE_WIDTH64= 'h6, // frame width in 64-bit words (partial last page in each line)
parameter MEMBRIDGE_MODE= 'h7, // AXI cache mode (default == 3). +0x10 - debug cache (replace data with counters)
// parameter MEMBRIDGE_MODE= 'h7, // AXI cache mode (default == 3). +0x10 - debug cache (replace data with counters)
parameter MEMBRIDGE_CTRL_IRQ= 'h7, // offset for IRQ control register (4 dibits): 0 - nop, 1 reset, 2 - disable, 3 - enable
parameter MEMBRIDGE_STATUS_REG= 'h3b,
parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
......@@ -833,7 +834,7 @@
parameter MULT_SAXI_CNTRL_ADDR = 'h73c, // ..'h73e
parameter MULT_SAXI_CNTRL_MODE = 'h0, // 'h73c offset for mode register
parameter MULT_SAXI_CNTRL_STATUS = 'h1, // 'h73d offset for status control register
parameter MULT_SAXI_CNTRL_IRQ = 'h2, // 'h73e offset for IRQ contgrol register (4 dibits): 0 - nop, 1 reset, 2 - disable, 3 - enable
parameter MULT_SAXI_CNTRL_IRQ = 'h2, // 'h73e offset for IRQ control register (4 dibits): 0 - nop, 1 reset, 2 - disable, 3 - enable
parameter MULT_SAXI_POINTERS_REG = 'h34, //..'h37 uses 4 consecutive locations
parameter MULT_SAXI_STATUS_REG = 'h3c, //status and IRQ requests and masks
parameter MULT_SAXI_HALF_BRAM = 1, // 0 - use full 36Kb BRAM for the buffer, 1 - use just half
......
includes/x393_tasks_afi.vh
View file @ 35cce7c8
......@@ -42,14 +42,14 @@
input [28:0] start64; // relative start address of the transfer (set to 0 when writing lo_addr64)
input [28:0] lo_addr64; // low address of the system memory range, in 64-bit words
input [28:0] size64; // size of the system memory range in 64-bit words
input [4:0] mode;
// input [4:0] mode;
begin
write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_LO_ADDR64, {3'b0,lo_addr64});
write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_SIZE64, {3'b0,size64});
write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_START64, {3'b0,start64});
write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_LEN64, {3'b0,len64});
write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_WIDTH64, {3'b0,width64});
write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_MODE, {27'b0,mode});
// write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL_IRQ, {27'b0,mode});
end
endtask
......
py393/cargs
View file @ 35cce7c8
-d TARGET_MODE=1
-f ../system_defines.vh
-f ../includes/x393_parameters.vh ../includes/x393_cur_params_target.vh ../includes/x393_localparams.vh
-f ../includes/x393_parameters.vh ../includes/x393_cur_params_target.vh ../includes/x393_localparams.vh ../includes/x393_simulation_parameters.vh
-l ../includes/x393_cur_params_target_gen.vh
-p PICKLE="../includes/x393_mcntrl.pickle"
-c export_all
\ No newline at end of file
py393/vrlg.py
View file @ 35cce7c8
This diff is collapsed.
py393/x393_export_c.py
View file @ 35cce7c8
......@@ -334,10 +334,16 @@ class X393ExportC(object):
data = self._enc_membridge_cmd(),
name = "x393_membridge_cmd", typ="wo",
frmt_spcs = frmt_spcs)
"""
stypedefs += self.get_typedef32(comment = "Cache mode for membridge",
data = self._enc_membridge_mode(),
name = "x393_membridge_mode", typ="wo",
frmt_spcs = frmt_spcs)
"""
stypedefs += self.get_typedef32(comment = "Interrupt handling commands for Membridge module",
data = self._enc_membridge_ctrl_irq(),
name = "x393_membridge_ctrl_irq", typ="wo",
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Address in 64-bit words",
data = self._enc_u29(),
name = "u29", typ="wo",
......@@ -738,7 +744,7 @@ class X393ExportC(object):
(("X393_MEMBRIDGE_START64", c, vrlg.MEMBRIDGE_START64 + ba, 0, None, "u29", "wo", "start of transfer offset to system memory range in QWORDs (4 LSBs==0)")),
(("X393_MEMBRIDGE_LEN64", c, vrlg.MEMBRIDGE_LEN64 + ba, 0, None, "u29", "wo", "Full length of transfer in QWORDs")),
(("X393_MEMBRIDGE_WIDTH64", c, vrlg.MEMBRIDGE_WIDTH64 + ba, 0, None, "u29", "wo", "Frame width in QWORDs (last xfer in each line may be partial)")),
(("X393_MEMBRIDGE_MODE", c, vrlg.MEMBRIDGE_MODE + ba, 0, None, "x393_membridge_mode", "wo", "AXI cache mode"))]
(("X393_MEMBRIDGE_CTRL_IRQ", c, vrlg.MEMBRIDGE_CTRL_IRQ + ba, 0, None, "x393_membridge_ctrl_irq", "wo", "Membridge IRQ control"))]
ba = vrlg.MCNTRL_PS_ADDR
ia = 0
......@@ -1777,6 +1783,8 @@ class X393ExportC(object):
dw=[]
dw.append(("wresp_conf", 0, 8,0, "Number of 64-bit words confirmed through axi b channel (low bits)"))
dw.append(("axi_arw_requested",8, 8,0, "Number of 64-bit words to be read/written over axi queued to AR/AW channels (low bits)"))
dw.append(("irq_r", 16, 1,0, "Interrupt request (before mask)"))
dw.append(("irq_m", 17, 1,0, "Interrupt enable (0 - disable)"))
dw.append(("busy", 24, 1,0, "Membridge operation in progress"))
dw.append(("done", 25, 1,0, "Membridge operation finished"))
dw.append(("seq_num", 26, 6,0, "Sequence number"))
......@@ -1828,11 +1836,18 @@ class X393ExportC(object):
dw.append(("enable", 0, 1,0, "enable membridge"))
dw.append(("start_reset", 1, 2,0, "1 - start (from current address), 3 - start from reset address"))
return dw
"""
def _enc_membridge_mode(self):
dw=[]
dw.append(("axi_cache", 0, 4,3, "AXI CACHE value (ignored by Zynq)"))
dw.append(("debug_cache", 4, 1,0, "0 - normal operation, 1 debug (replace data)"))
return dw
"""
def _enc_membridge_ctrl_irq(self):
dw=[]
dw.append(("interrupt_cmd", 0, 2, 0, "IRQ control commands - 0: nop, 1: clear interrupt status, 2: disable interrupt, 3: enable interrupt"))
return dw
def _enc_u29(self):
dw=[]
dw.append(("addr64", 0,29,0, "Address/length in 64-bit words (<<3 to get byte address"))
......
py393/x393_mcntrl_membridge.py
View file @ 35cce7c8
......@@ -187,7 +187,7 @@ class X393McntrlMembridge(object):
start64, # input [28:0] start64; # relative start address of the transfer (set to 0 when writing lo_addr64)
lo_addr64 = None, # input [28:0] lo_addr64; # low address of the system memory range, in 64-bit words
size64 = None, # input [28:0] size64; # size of the system memory range in 64-bit words
cache = 0x3,
# cache = 0x3,
quiet=1):
'''
Set up membridge parameters for data transfer
......@@ -196,8 +196,6 @@ class X393McntrlMembridge(object):
@param start64 relative start address of the transfer (normally 0)
@param lo_addr64 low address of the system memory range, in 64-bit words
@param size64 size of the system memory range in 64-bit words
@param cache bits[3:0] - ARCHACHE, AWCACHE (default 0x3), bit[4] - debug mode, when each 64-bit word high 16 bits is replaced with:
bits[63:60] - transfer id (incrementing each new transfer), bits[59:58]==0, [57:56] - mchtrl page number, [45:48] FIFO count (wcount)
@quiet - reduce output (>=1 - silent)
'''
if lo_addr64 is None:
......@@ -212,7 +210,7 @@ class X393McntrlMembridge(object):
self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_START64, start64);
self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_LEN64, len64);
self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_WIDTH64, width64);
self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_MODE, cache);
# self.x393_axi_tasks.write_control_register(vrlg.MEMBRIDGE_ADDR + vrlg.MEMBRIDGE_MODE, cache);
def membridge_start(self,
cont=False,
......@@ -249,7 +247,7 @@ class X393McntrlMembridge(object):
lo_addr64 = None, # input [28:0] lo_addr64; # low address of the system memory range, in 64-bit words
size64 = None, # input [28:0] size64; # size of the system memory range in 64-bit words
cont = False, # input continue; # 0 start from start64, 1 - continue from where it was
cache = 0x3,
# cache = 0x3,
wait_ready = False,
quiet=1):
'''
......@@ -265,8 +263,6 @@ class X393McntrlMembridge(object):
@param lo_addr64 start of the system memory buffer, in 8-bytes (byte_address >>3), 29 bits
@param size64 size of the transfer buffer in the system memory, in 8-bytes. Transfers will roll over to lo_addr64. 29 bits.
@param cont True: continue from the same address in the system memory, where the previous transfer stopped. False - start from lo_addr64+start64
@param cache bits[3:0] - ARCHACHE, AWCACHE (default 0x3), bit[4] - debug mode, when each 64-bit word high 16 bits is replaced with:
bits[63:60] - transfer id (incrementing each new transfer), bits[59:58]==0, [57:56] - mchtrl page number, [45:48] FIFO count (wcount)
@param wait_ready poll status to see if the command finished
@param quiet Reduce output
'''
......@@ -297,10 +293,10 @@ class X393McntrlMembridge(object):
if quiet <2:
print("====== test_afi_rw: write=%s, frame_start=0x%x, window_full_width=%d, window_width=%d, window_height=%d, window_left=%d, window_top=%d"%(
str(write_ddr3), frame_start_addr, window_full_width, window_width, window_height, window_left, window_top));
print("len64=0x%x, width64=0x%x, start64=0x%x, lo_addr64=0x%x, size64=0x%x, cache=0x%x"%(
print("len64=0x%x, width64=0x%x, start64=0x%x, lo_addr64=0x%x, size64=0x%x"%(
(window_width << 1)*window_height,
(window_width << 1),
start64, lo_addr64, size64,cache))
start64, lo_addr64, size64))
'''
mode= func_encode_mode_scanline(
0, # extra_pages,
......@@ -337,7 +333,7 @@ class X393McntrlMembridge(object):
start64,
lo_addr64,
size64,
cache,
# cache,
quiet)
self.membridge_start (cont)
# just wait done (default timeout = 10 sec)
......
py393/x393_sens_cmprs.py
View file @ 35cce7c8
......@@ -1632,7 +1632,7 @@ class X393SensCmprs(object):
def setup_membridge_sensor(self,
num_sensor = 0,
write_mem = False,
cache_mode = 0x3, # 0x13 for debug mode
# cache_mode = 0x3, # 0x13 for debug mode
window_width = 2592,
window_height = 1944,
window_left = 0,
......@@ -1645,7 +1645,6 @@ class X393SensCmprs(object):
Configure membridge to read/write to the sensor 0 area in the video memory
@param num_sensor - sensor port number (0..3)
@param write_mem - Write to video memory (Flase - read from)
@param cache_mode - lower 4 bits, axi cache mode (default 3), bit [4] - debug mode (replace data)
@param window_width - window width in pixels (bytes) (TODO: add 16-bit mode)
@param window_height - window height in lines
@param window_left - window left margin
......@@ -1692,7 +1691,6 @@ class X393SensCmprs(object):
print ("membridge start = 0x%x"%(membridge_start))
print ("membridge end = 0x%x"%(membridge_end))
print ("membridge size = %d bytes"%(membridge_end - membridge_start))
print ("cache/debug mode = 0x%x bytes"%(cache_mode))
# Copied from setup_sensor
......@@ -1762,7 +1760,7 @@ class X393SensCmprs(object):
start64 = 0,
lo_addr64 = membridge_start // 8,
size64 = (membridge_end - membridge_start) // 8,
cache = cache_mode,
# cache = cache_mode,
quiet = 1 - verbose)
self.x393Membridge.membridge_en( # enable membridge
......
x393.v
View file @ 35cce7c8
......@@ -549,6 +549,7 @@ module x393 #(
wire [3:0] cmprs_irq; // compressor done, data confirmed written to memory)
wire [3:0] mult_saxi_irq; // interrupts from mult_saxi channels
wire membridge_irq; // interrupt from membridge done
// Compressor frame synchronization
......@@ -1473,7 +1474,8 @@ assign axi_grst = axi_rst_pre;
.MEMBRIDGE_START64 (MEMBRIDGE_START64),
.MEMBRIDGE_LEN64 (MEMBRIDGE_LEN64),
.MEMBRIDGE_WIDTH64 (MEMBRIDGE_WIDTH64),
.MEMBRIDGE_MODE (MEMBRIDGE_MODE),
// .MEMBRIDGE_MODE (MEMBRIDGE_MODE),
.MEMBRIDGE_CTRL_IRQ (MEMBRIDGE_CTRL_IRQ),
.MEMBRIDGE_STATUS_REG (MEMBRIDGE_STATUS_REG),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS)
......@@ -1490,6 +1492,7 @@ assign axi_grst = axi_rst_pre;
.status_ad (status_membridge_ad[7:0]), // output[7:0]
.status_rq (status_membridge_rq), // output
.status_start (status_membridge_start), // input
.irq (membridge_irq), // output
.frame_start_chn (frame_start_chn1), // output
.next_page_chn (next_page_chn1), // output
.cmd_wrmem (cmd_wrmem_chn1), // input
......@@ -2955,7 +2958,8 @@ sata_ahci_top sata_top(
cmprs_irq[3:0], // [15:12] Compressor done interrupts SPI: Numbers [91:88]
frseq_irq[3:0], // [11: 8] Frame sync interrupts SPI: Numbers [87:84]
mult_saxi_irq[3:0], // [ 7: 4] interrupts from mult_saxi channels SPI: Numbers [68:65]
3'b0, // [ 3: 1] Reserved SPI: Numbers [65:63]
membridge_irq, // [3] interrupts from membridge module SPI: Number [65]
2'b0, // [ 2: 1] Reserved SPI: Numbers [64:63]
sata_irq // [ 0] AHCI (SATA ) interrupt SPI: Number [62]
}), // Interrupts, PL to PS [19:0], input
.IRQP2F(), // Interrupts, PL to PS [28:0], output
......
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