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Commit 31e4c348 authored by Andrey Filippov's avatar Andrey Filippov
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more simulation with HiSPi sensors

parent 8dd16a59
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.project
View file @ 31e4c348
...@@ -62,7 +62,7 @@ ...@@ -62,7 +62,7 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151107161322372.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151107204814914.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
...@@ -97,7 +97,7 @@ ...@@ -97,7 +97,7 @@
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151107161322372.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151107204814914.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......
.settings/com.elphel.vdt.FPGA_project.prefs
View file @ 31e4c348
FPGA_project_0_SimulationTopFile=x393_testbench02.tf FPGA_project_0_SimulationTopFile=x393_testbench03.tf
FPGA_project_1_SimulationTopModule=x393_testbench02 FPGA_project_1_SimulationTopModule=x393_testbench03
FPGA_project_2_ImplementationTopFile=x393.v FPGA_project_2_ImplementationTopFile=x393.v
FPGA_project_4_part=xc7z030fbg484-1 FPGA_project_4_part=xc7z030fbg484-1
FPGA_project_5_part=xc7z030fbg484-1 FPGA_project_5_part=xc7z030fbg484-1
......
includes/tasks_tests_memory.vh
View file @ 31e4c348
...@@ -137,8 +137,10 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused ...@@ -137,8 +137,10 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
reg single; reg single;
reg reset_frame; reg reset_frame;
reg disable_need; reg disable_need;
reg skip_too_late;
begin begin
// disable_need = 1'b0; skip_too_late = 1'b0;
disable_need = 1'b0;
repetitive = 1'b1; repetitive = 1'b1;
single = 1'b0; single = 1'b0;
reset_frame = 1'b0; reset_frame = 1'b0;
...@@ -149,6 +151,7 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused ...@@ -149,6 +151,7 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
(window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0}, (window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0},
start64, lo_addr64, size64, $time); start64, lo_addr64, size64, $time);
mode= func_encode_mode_scanline( mode= func_encode_mode_scanline(
skip_too_late,
disable_need, disable_need,
repetitive, repetitive,
single, single,
...@@ -219,12 +222,14 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused ...@@ -219,12 +222,14 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
reg repetitive; reg repetitive;
reg single; reg single;
reg reset_frame; reg reset_frame;
reg disable_need; reg disable_need;
reg skip_too_late;
begin begin
disable_need = 1'b0; disable_need = 1'b0;
repetitive = 1'b1; repetitive = 1'b1;
single = 1'b0; single = 1'b0;
reset_frame = 1'b0; reset_frame = 1'b0;
skip_too_late = 1'b0;
pages_per_row= (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1); pages_per_row= (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);
$display("====== test_scanline_write: channel=%d, extra_pages=%d, wait_done=%d @%t", $display("====== test_scanline_write: channel=%d, extra_pages=%d, wait_done=%d @%t",
channel, extra_pages, wait_done, $time); channel, extra_pages, wait_done, $time);
...@@ -250,6 +255,7 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused ...@@ -250,6 +255,7 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
end end
endcase endcase
mode= func_encode_mode_scanline( mode= func_encode_mode_scanline(
skip_too_late,
disable_need, disable_need,
repetitive, repetitive,
single, single,
...@@ -360,8 +366,9 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused ...@@ -360,8 +366,9 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused
reg single; reg single;
reg reset_frame; reg reset_frame;
reg disable_need; reg disable_need;
reg skip_too_late;
begin begin
skip_too_late = 1'b0;
disable_need = 1'b0; disable_need = 1'b0;
repetitive = 1'b1; repetitive = 1'b1;
single = 1'b0; single = 1'b0;
...@@ -391,6 +398,7 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused ...@@ -391,6 +398,7 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused
end end
endcase endcase
mode= func_encode_mode_scanline( mode= func_encode_mode_scanline(
skip_too_late,
disable_need, disable_need,
repetitive, repetitive,
single, single,
...@@ -471,13 +479,14 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused ...@@ -471,13 +479,14 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
reg repetitive; reg repetitive;
reg single; reg single;
reg reset_frame; reg reset_frame;
reg disable_need; reg disable_need;
reg skip_too_late;
begin begin
disable_need = 1'b0; disable_need = 1'b0;
repetitive = 1'b1; repetitive = 1'b1;
single = 1'b0; single = 1'b0;
reset_frame = 1'b0; reset_frame = 1'b0;
skip_too_late = 1'b0;
tiles_per_row= (window_width/tile_width)+ ((window_width % tile_width==0)?0:1); tiles_per_row= (window_width/tile_width)+ ((window_width % tile_width==0)?0:1);
tile_rows_per_window= ((window_height-1)/tile_vstep) + 1; tile_rows_per_window= ((window_height-1)/tile_vstep) + 1;
tile_size= tile_width*tile_height; tile_size= tile_width*tile_height;
...@@ -505,6 +514,7 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused ...@@ -505,6 +514,7 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
end end
endcase endcase
mode= func_encode_mode_tiled( mode= func_encode_mode_tiled(
skip_too_late,
disable_need, disable_need,
repetitive, repetitive,
single, single,
...@@ -603,8 +613,10 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused ...@@ -603,8 +613,10 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused
reg repetitive; reg repetitive;
reg single; reg single;
reg reset_frame; reg reset_frame;
reg disable_need; reg disable_need;
reg skip_too_late;
begin begin
skip_too_late = 1'b0;
disable_need = 1'b0; disable_need = 1'b0;
repetitive = 1'b1; repetitive = 1'b1;
single = 1'b0; single = 1'b0;
...@@ -637,6 +649,7 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused ...@@ -637,6 +649,7 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused
end end
endcase endcase
mode= func_encode_mode_tiled( mode= func_encode_mode_tiled(
skip_too_late,
disable_need, disable_need,
repetitive, repetitive,
single, single,
......
includes/x393_simulation_parameters.vh
View file @ 31e4c348
...@@ -46,9 +46,15 @@ ...@@ -46,9 +46,15 @@
parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks) parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks)
//parameter tMD = 14; // //parameter tMD = 14; //
//parameter tDDO = 10; // some confusion here - let's assume that it is from DCLK to Data out //parameter tDDO = 10; // some confusion here - let's assume that it is from DCLK to Data out
`ifdef HISPI
parameter SENSOR12BITS_TMD = 1, //
parameter SENSOR12BITS_TDDO = 1, // some confusion here - let's assume that it is from DCLK to Data out
parameter SENSOR12BITS_TDDO1 = 2, //
`else
parameter SENSOR12BITS_TMD = 4, // parameter SENSOR12BITS_TMD = 4, //
parameter SENSOR12BITS_TDDO = 2, // some confusion here - let's assume that it is from DCLK to Data out parameter SENSOR12BITS_TDDO = 2, // some confusion here - let's assume that it is from DCLK to Data out
parameter SENSOR12BITS_TDDO1 = 5, // parameter SENSOR12BITS_TDDO1 = 5, //
`endif
// parameter SENSOR12BITS_TRIGDLY = 8, // delay between trigger input and start of output (VACT) in lines // parameter SENSOR12BITS_TRIGDLY = 8, // delay between trigger input and start of output (VACT) in lines
// parameter SENSOR12BITS_RAMP = 1, // 1 - ramp, 0 - random (now - sensor.dat) // parameter SENSOR12BITS_RAMP = 1, // 1 - ramp, 0 - random (now - sensor.dat)
// parameter SENSOR12BITS_NEW_BAYER = 0, // 0 - "old" tiles (16x16, 1 - new - (18x18) // parameter SENSOR12BITS_NEW_BAYER = 0, // 0 - "old" tiles (16x16, 1 - new - (18x18)
...@@ -61,7 +67,7 @@ ...@@ -61,7 +67,7 @@
parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page) parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)
parameter WOI_WIDTH= 64, parameter WOI_WIDTH= 64,
parameter QUADRANTS_PXD_HACT_VACT = 6'h01 // 2 bits each: data-0, hact - 1, vact - 2 parameter QUADRANTS_PXD_HACT_VACT = 6'h01, // 2 bits each: data-0, hact - 1, vact - 2
// 90-degree shifts for data [1:0], hact [3:2] and vact [5:4] // 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
parameter SENSOR_PRIORITY = 1000
\ No newline at end of file
x393_testbench02.tf
View file @ 31e4c348
...@@ -2247,7 +2247,8 @@ task write_block_scanline_chn; // SuppressThisWarning VEditor : may be unused ...@@ -2247,7 +2247,8 @@ task write_block_scanline_chn; // SuppressThisWarning VEditor : may be unused
end end
endtask endtask
// x393_mcntrl (no class) // x393_mcntrl (no class)
function [11:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not used function [12:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not used
input skip_too_late;
input disable_need; input disable_need;
input repetitive; input repetitive;
input single; input single;
...@@ -2260,7 +2261,7 @@ function [11:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not us ...@@ -2260,7 +2261,7 @@ function [11:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not us
input enable; // enable requests from this channel ( 0 will let current to finish, but not raise want/need) input enable; // enable requests from this channel ( 0 will let current to finish, but not raise want/need)
input chn_reset; // immediately reset al;l the internal circuitry input chn_reset; // immediately reset al;l the internal circuitry
reg [11:0] rslt; reg [12:0] rslt;
begin begin
rslt = 0; rslt = 0;
rslt[MCONTR_LINTILE_EN] = ~chn_reset; rslt[MCONTR_LINTILE_EN] = ~chn_reset;
...@@ -2273,12 +2274,15 @@ function [11:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not us ...@@ -2273,12 +2274,15 @@ function [11:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not us
rslt[MCONTR_LINTILE_SINGLE] = single; rslt[MCONTR_LINTILE_SINGLE] = single;
rslt[MCONTR_LINTILE_REPEAT] = repetitive; rslt[MCONTR_LINTILE_REPEAT] = repetitive;
rslt[MCONTR_LINTILE_DIS_NEED] = disable_need; rslt[MCONTR_LINTILE_DIS_NEED] = disable_need;
rslt[MCONTR_LINTILE_SKIP_LATE] = skip_too_late;
// func_encode_mode_tiled={byte32,keep_open,extra_pages,write_mem,enable,~chn_reset}; // func_encode_mode_tiled={byte32,keep_open,extra_pages,write_mem,enable,~chn_reset};
func_encode_mode_tiled = rslt; func_encode_mode_tiled = rslt;
end end
endfunction endfunction
// x393_mcntrl (no class) // x393_mcntrl (no class)
function [11:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not used function [12:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not used
input skip_too_late;
input disable_need; input disable_need;
input repetitive; input repetitive;
input single; input single;
...@@ -2289,7 +2293,7 @@ function [11:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not ...@@ -2289,7 +2293,7 @@ function [11:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not
input enable; // enable requests from this channel ( 0 will let current to finish, but not raise want/need) input enable; // enable requests from this channel ( 0 will let current to finish, but not raise want/need)
input chn_reset; // immediately reset al;l the internal circuitry input chn_reset; // immediately reset al;l the internal circuitry
reg [11:0] rslt; reg [12:0] rslt;
begin begin
rslt = 0; rslt = 0;
rslt[MCONTR_LINTILE_EN] = ~chn_reset; rslt[MCONTR_LINTILE_EN] = ~chn_reset;
...@@ -2300,6 +2304,7 @@ function [11:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not ...@@ -2300,6 +2304,7 @@ function [11:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not
rslt[MCONTR_LINTILE_SINGLE] = single; rslt[MCONTR_LINTILE_SINGLE] = single;
rslt[MCONTR_LINTILE_REPEAT] = repetitive; rslt[MCONTR_LINTILE_REPEAT] = repetitive;
rslt[MCONTR_LINTILE_DIS_NEED] = disable_need; rslt[MCONTR_LINTILE_DIS_NEED] = disable_need;
rslt[MCONTR_LINTILE_SKIP_LATE] = skip_too_late;
// func_encode_mode_scanline={extra_pages,write_mem,enable,~chn_reset}; // func_encode_mode_scanline={extra_pages,write_mem,enable,~chn_reset};
func_encode_mode_scanline = rslt; func_encode_mode_scanline = rslt;
end end
......
x393_testbench03.sav
View file @ 31e4c348
[*] [*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Wed Oct 28 16:58:42 2015 [*] Sun Nov 8 07:30:39 2015
[*] [*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151028094057171.fst" [dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151107210810890.fst"
[dumpfile_mtime] "Wed Oct 28 16:18:25 2015" [dumpfile_mtime] "Sun Nov 8 04:40:36 2015"
[dumpfile_size] 255725225 [dumpfile_size] 202201184
[savefile] "/home/andrey/git/x393/x393_testbench03.sav" [savefile] "/home/andrey/git/x393/x393_testbench03.sav"
[timestart] 174980000 [timestart] 0
[size] 1823 1173 [size] 1823 1180
[pos] 1920 0 [pos] 1920 0
*-13.073349 175004500 108390000 148070000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-25.279701 81782497 108390000 148070000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03. [treeopen] x393_testbench03.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i. [treeopen] x393_testbench03.par12_hispi_psp4l0_i.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0]. [treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].
...@@ -63,7 +63,7 @@ ...@@ -63,7 +63,7 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3]. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
[sst_width] 294 [sst_width] 445
[signals_width] 348 [signals_width] 348
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 514 [sst_vpaned_height] 514
...@@ -773,7 +773,7 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se ...@@ -773,7 +773,7 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
- -
@1000200 @1000200
-sens_sync_chn0 -sens_sync_chn0
@800200 @c00200
-mcntr_linear_rw_sensor0 -mcntr_linear_rw_sensor0
@28 @28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.cmd_we x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.cmd_we
...@@ -903,8 +903,9 @@ x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i ...@@ -903,8 +903,9 @@ x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i
-group_end -group_end
@200 @200
- -
@1000200 @1401200
-mcntr_linear_rw_sensor0 -mcntr_linear_rw_sensor0
@1000200
-sensor_channel_0 -sensor_channel_0
@800200 @800200
-DDR3 -DDR3
...@@ -973,7 +974,7 @@ x393_testbench03.simul_sensor12bits_2_i.stopped ...@@ -973,7 +974,7 @@ x393_testbench03.simul_sensor12bits_2_i.stopped
x393_testbench03.simul_sensor12bits_2_i.stoppedd x393_testbench03.simul_sensor12bits_2_i.stoppedd
@1401200 @1401200
-simul_sensor_0 -simul_sensor_0
@c00200 @800200
-PX1 -PX1
@28 @28
x393_testbench03.PX1_MCLK_PRE x393_testbench03.PX1_MCLK_PRE
...@@ -1007,9 +1008,31 @@ x393_testbench03.PX1_MRST ...@@ -1007,9 +1008,31 @@ x393_testbench03.PX1_MRST
x393_testbench03.PX1_OFST x393_testbench03.PX1_OFST
x393_testbench03.PX1_SHUTTER x393_testbench03.PX1_SHUTTER
x393_testbench03.PX1_VACT x393_testbench03.PX1_VACT
@1401200 @1000200
-PX1 -PX1
@800200 @800200
-SENSOR0
@28
x393_testbench03.simul_sensor12bits_i.MCLK
@22
x393_testbench03.simul_sensor12bits_i.row_index[5:0]
x393_testbench03.simul_sensor12bits_i.row[11:0]
x393_testbench03.simul_sensor12bits_i.col_index[5:0]
x393_testbench03.simul_sensor12bits_i.col[11:0]
x393_testbench03.simul_sensor12bits_i.cold[11:0]
@28
x393_testbench03.simul_sensor12bits_i.c
@22
x393_testbench03.simul_sensor12bits_i.state[3:0]
@28
x393_testbench03.simul_sensor12bits_i.stoppedd
@23
x393_testbench03.simul_sensor12bits_i.cntrd[15:0]
@200
-
@1000200
-SENSOR0
@800200
-par_hispi_sel -par_hispi_sel
@28 @28
x393_testbench03.par12_hispi_psp4l0_i.pclk x393_testbench03.par12_hispi_psp4l0_i.pclk
...@@ -2107,7 +2130,7 @@ x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huff ...@@ -2107,7 +2130,7 @@ x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huff
-new_compressor -new_compressor
@22 @22
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_rdata0[63:0] x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_rdata0[63:0]
@29 @28
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_ren0 x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_ren0
@200 @200
- -
......
x393_testbench03.tf
View file @ 31e4c348
...@@ -120,8 +120,8 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb ...@@ -120,8 +120,8 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb
`else `else
parameter HBLANK= 12; // 52; // 12; /// 52; //********************* parameter HBLANK= 12; // 52; // 12; /// 52; //*********************
parameter BLANK_ROWS_BEFORE= 1; //8; ///2+2 - a little faster than compressor parameter BLANK_ROWS_BEFORE= 1; //8; ///2+2 - a little faster than compressor
parameter BLANK_ROWS_AFTER= 1; //8; parameter BLANK_ROWS_AFTER= 1; //8;
`endif `endif
parameter WOI_HEIGHT= 32; parameter WOI_HEIGHT= 32;
parameter TRIG_LINES= 8; parameter TRIG_LINES= 8;
...@@ -359,7 +359,7 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb ...@@ -359,7 +359,7 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb
assign PX1_ARST = sns1_dn[7]; assign PX1_ARST = sns1_dn[7];
assign sns1_clkn = PX1_D[0]; // inout CNVSYNC/TDI assign sns1_clkn = PX1_D[0]; // inout CNVSYNC/TDI
assign sns1_clkp = PX1_D[1]; // CNVCLK/TDO assign sns1_clkp = PX1_D[1]; // CNVCLK/TDO
assign PX1_ARO = sns1_ctl; // from FPGA to sensor assign PX1_ARO = sns1_ctl; // from FPGA to sensor
assign PX2_MRST = sns2_dp[7]; // from FPGA to sensor assign PX2_MRST = sns2_dp[7]; // from FPGA to sensor
assign PX2_MCLK_PRE = sns2_dp[0]; // from FPGA to sensor assign PX2_MCLK_PRE = sns2_dp[0]; // from FPGA to sensor
...@@ -1260,7 +1260,7 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -1260,7 +1260,7 @@ assign #10 gpio_pins[9] = gpio_pins[8];
setup_sensor_membridge (0, // for sensor 0 setup_sensor_membridge (0, // for sensor 0
1) ; // disable_need 1) ; // disable_need
`endif `endif
`ifdef DEBUG_RING `ifdef DEBUG_RING
TEST_TITLE = "READING DEBUG DATA"; TEST_TITLE = "READING DEBUG DATA";
$display("===================== TEST_%s =========================",TEST_TITLE); $display("===================== TEST_%s =========================",TEST_TITLE);
...@@ -1346,6 +1346,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP; ...@@ -1346,6 +1346,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
//TODO: See how to show problems in include files opened in the editor (test all top *.v files that have it) //TODO: See how to show problems in include files opened in the editor (test all top *.v files that have it)
// Top module under test // Top module under test
x393 #( x393 #(
// TODO: Are these parameters needed? They are included in x393 from the save x393_parameters.vh
.MCONTR_WR_MASK (MCONTR_WR_MASK), .MCONTR_WR_MASK (MCONTR_WR_MASK),
.MCONTR_RD_MASK (MCONTR_RD_MASK), .MCONTR_RD_MASK (MCONTR_RD_MASK),
.MCONTR_CMD_WR_ADDR (MCONTR_CMD_WR_ADDR), .MCONTR_CMD_WR_ADDR (MCONTR_CMD_WR_ADDR),
...@@ -1505,8 +1506,15 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP; ...@@ -1505,8 +1506,15 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR), .MCNTRL_TEST01_STATUS_REG_CHN3_ADDR (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR) .MCNTRL_TEST01_STATUS_REG_CHN4_ADDR (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR)
) x393_i ( ) x393_i (
`ifdef HISPI
.sns1_dp (sns1_dp[3:0]), // inout[3:0]
.sns1_dn (sns1_dn[3:0]), // inout[3:0]
.sns1_dp74 (sns1_dp[7:4]), // inout[3:0]
.sns1_dn74 (sns1_dn[7:4]), // inout[3:0]
`else
.sns1_dp (sns1_dp), // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK} .sns1_dp (sns1_dp), // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK}
.sns1_dn (sns1_dn), // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF} .sns1_dn (sns1_dn), // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF}
`endif
.sns1_clkp (sns1_clkp), // inout CNVCLK/TDO .sns1_clkp (sns1_clkp), // inout CNVCLK/TDO
.sns1_clkn (sns1_clkn), // inout CNVSYNC/TDI .sns1_clkn (sns1_clkn), // inout CNVSYNC/TDI
.sns1_scl (sns1_scl), // inout PX_SCL .sns1_scl (sns1_scl), // inout PX_SCL
...@@ -1514,8 +1522,15 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP; ...@@ -1514,8 +1522,15 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.sns1_ctl (sns1_ctl), // inout PX_ARO/TCK .sns1_ctl (sns1_ctl), // inout PX_ARO/TCK
.sns1_pg (sns1_pg), // inout SENSPGM .sns1_pg (sns1_pg), // inout SENSPGM
.sns2_dp (sns2_dp), // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK} `ifdef HISPI
.sns2_dn (sns2_dn), // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF} .sns2_dp (sns2_dp[3:0]), // inout[3:0]
.sns2_dn (sns2_dn[3:0]), // inout[3:0]
.sns2_dp74 (sns2_dp[7:4]), // inout[3:0]
.sns2_dn74 (sns2_dn[7:4]), // inout[3:0]
`else
.sns2_dp (sns1_dp), // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK}
.sns2_dn (sns1_dn), // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF}
`endif
.sns2_clkp (sns2_clkp), // inout CNVCLK/TDO .sns2_clkp (sns2_clkp), // inout CNVCLK/TDO
.sns2_clkn (sns2_clkn), // inout CNVSYNC/TDI .sns2_clkn (sns2_clkn), // inout CNVSYNC/TDI
.sns2_scl (sns2_scl), // inout PX_SCL .sns2_scl (sns2_scl), // inout PX_SCL
...@@ -1523,8 +1538,15 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP; ...@@ -1523,8 +1538,15 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.sns2_ctl (sns2_ctl), // inout PX_ARO/TCK .sns2_ctl (sns2_ctl), // inout PX_ARO/TCK
.sns2_pg (sns2_pg), // inout SENSPGM .sns2_pg (sns2_pg), // inout SENSPGM
`ifdef HISPI
.sns3_dp (sns3_dp[3:0]), // inout[3:0]
.sns3_dn (sns3_dn[3:0]), // inout[3:0]
.sns3_dp74 (sns3_dp[7:4]), // inout[3:0]
.sns3_dn74 (sns3_dn[7:4]), // inout[3:0]
`else
.sns3_dp (sns3_dp), // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK} .sns3_dp (sns3_dp), // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK}
.sns3_dn (sns3_dn), // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF} .sns3_dn (sns3_dn), // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF}
`endif
.sns3_clkp (sns3_clkp), // inout CNVCLK/TDO .sns3_clkp (sns3_clkp), // inout CNVCLK/TDO
.sns3_clkn (sns3_clkn), // inout CNVSYNC/TDI .sns3_clkn (sns3_clkn), // inout CNVSYNC/TDI
.sns3_scl (sns3_scl), // inout PX_SCL .sns3_scl (sns3_scl), // inout PX_SCL
...@@ -1532,8 +1554,15 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP; ...@@ -1532,8 +1554,15 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.sns3_ctl (sns3_ctl), // inout PX_ARO/TCK .sns3_ctl (sns3_ctl), // inout PX_ARO/TCK
.sns3_pg (sns3_pg), // inout SENSPGM .sns3_pg (sns3_pg), // inout SENSPGM
`ifdef HISPI
.sns4_dp (sns4_dp[3:0]), // inout[3:0]
.sns4_dn (sns4_dn[3:0]), // inout[3:0]
.sns4_dp74 (sns4_dp[7:4]), // inout[3:0]
.sns4_dn74 (sns4_dn[7:4]), // inout[3:0]
`else
.sns4_dp (sns4_dp), // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK} .sns4_dp (sns4_dp), // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK}
.sns4_dn (sns4_dn), // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF} .sns4_dn (sns4_dn), // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF}
`endif
.sns4_clkp (sns4_clkp), // inout CNVCLK/TDO .sns4_clkp (sns4_clkp), // inout CNVCLK/TDO
.sns4_clkn (sns4_clkn), // inout CNVSYNC/TDI .sns4_clkn (sns4_clkn), // inout CNVSYNC/TDI
.sns4_scl (sns4_scl), // inout PX_SCL .sns4_scl (sns4_scl), // inout PX_SCL
...@@ -1564,7 +1593,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP; ...@@ -1564,7 +1593,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.ffclk0p (ffclk0p), // input .ffclk0p (ffclk0p), // input
.ffclk0n (ffclk0n), // input .ffclk0n (ffclk0n), // input
.ffclk1p (ffclk1p), // input .ffclk1p (ffclk1p), // input
.ffclk1n (ffclk1n) // input .ffclk1n (ffclk1n) // input
); );
// just to simplify extra delays in tri-state memory bus - provide output enable // just to simplify extra delays in tri-state memory bus - provide output enable
wire WRAP_MCLK=x393_i.mclk; wire WRAP_MCLK=x393_i.mclk;
...@@ -2260,7 +2289,7 @@ simul_axi_hp_wr #( ...@@ -2260,7 +2289,7 @@ simul_axi_hp_wr #(
.tDDO1 (SENSOR12BITS_TDDO1), .tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY), .trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP), .ramp (0), //SENSOR12BITS_RAMP),
.new_bayer (1) //SENSOR12BITS_NEW_BAYER) .new_bayer (0) // was 1 SENSOR12BITS_NEW_BAYER)
) simul_sensor12bits_i ( ) simul_sensor12bits_i (
.MCLK (PX1_MCLK), // input .MCLK (PX1_MCLK), // input
.MRST (PX1_MRST), // input .MRST (PX1_MRST), // input
...@@ -2299,7 +2328,7 @@ simul_axi_hp_wr #( ...@@ -2299,7 +2328,7 @@ simul_axi_hp_wr #(
.tDDO1 (SENSOR12BITS_TDDO1), .tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY), .trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP), .ramp (0), //SENSOR12BITS_RAMP),
.new_bayer (1) //SENSOR12BITS_NEW_BAYER) .new_bayer (0) //SENSOR12BITS_NEW_BAYER) was 1
) simul_sensor12bits_2_i ( ) simul_sensor12bits_2_i (
.MCLK (PX2_MCLK), // input .MCLK (PX2_MCLK), // input
.MRST (PX2_MRST), // input .MRST (PX2_MRST), // input
...@@ -2336,8 +2365,8 @@ simul_axi_hp_wr #( ...@@ -2336,8 +2365,8 @@ simul_axi_hp_wr #(
.tDDO (SENSOR12BITS_TDDO), .tDDO (SENSOR12BITS_TDDO),
.tDDO1 (SENSOR12BITS_TDDO1), .tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY), .trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP), .ramp (0), // SENSOR12BITS_RAMP),
.new_bayer (1) //SENSOR12BITS_NEW_BAYER) .new_bayer (0) // was 1SENSOR12BITS_NEW_BAYER)
) simul_sensor12bits_3_i ( ) simul_sensor12bits_3_i (
.MCLK (PX3_MCLK), // input .MCLK (PX3_MCLK), // input
.MRST (PX3_MRST), // input .MRST (PX3_MRST), // input
...@@ -2374,8 +2403,8 @@ simul_axi_hp_wr #( ...@@ -2374,8 +2403,8 @@ simul_axi_hp_wr #(
.tDDO (SENSOR12BITS_TDDO), .tDDO (SENSOR12BITS_TDDO),
.tDDO1 (SENSOR12BITS_TDDO1), .tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY), .trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP), .ramp (0),// SENSOR12BITS_RAMP),
.new_bayer (1) //SENSOR12BITS_NEW_BAYER) .new_bayer (0) // was 1SENSOR12BITS_NEW_BAYER)
) simul_sensor12bits_4_i ( ) simul_sensor12bits_4_i (
.MCLK (PX4_MCLK), // input .MCLK (PX4_MCLK), // input
.MRST (PX4_MRST), // input .MRST (PX4_MRST), // input
...@@ -2661,8 +2690,8 @@ task setup_sensor_channel; ...@@ -2661,8 +2690,8 @@ task setup_sensor_channel;
setup_compressor_channel( setup_compressor_channel(
num_sensor, // sensor channel number (0..3) num_sensor, // sensor channel number (0..3)
// 0, // qbank; // [6:3] quantization table page - 100% quality 0, // qbank; // [6:3] quantization table page - 100% quality
1, // qbank; // [6:3] quantization table page - 85%? quality // 1, // qbank; // [6:3] quantization table page - 85%? quality
1, // dc_sub; // [8:7] subtract DC 1, // dc_sub; // [8:7] subtract DC
CMPRS_CBIT_CMODE_JPEG18, //input [31:0] cmode; // [13:9] color mode: CMPRS_CBIT_CMODE_JPEG18, //input [31:0] cmode; // [13:9] color mode:
// parameter CMPRS_CBIT_CMODE_JPEG18 = 4'h0, // color 4:2:0 // parameter CMPRS_CBIT_CMODE_JPEG18 = 4'h0, // color 4:2:0
...@@ -2679,7 +2708,7 @@ task setup_sensor_channel; ...@@ -2679,7 +2708,7 @@ task setup_sensor_channel;
// parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented) // parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
// parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks // parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks
1, // input [31:0] multi_frame; // [15:14] 0 - single-frame buffer, 1 - multiframe video memory buffer 1, // input [31:0] multi_frame; // [15:14] 0 - single-frame buffer, 1 - multiframe video memory buffer
0, // input [31:0] bayer; // [20:18] // Bayer shift 3, // 0, // input [31:0] bayer; // [20:18] // Bayer shift
0, // input [31:0] focus_mode; // [23:21] Set focus mode 0, // input [31:0] focus_mode; // [23:21] Set focus mode
3, // num_macro_cols_m1; // number of macroblock colums minus 1 3, // num_macro_cols_m1; // number of macroblock colums minus 1
1, // num_macro_rows_m1; // number of macroblock rows minus 1 1, // num_macro_rows_m1; // number of macroblock rows minus 1
...@@ -2752,10 +2781,10 @@ task setup_sensor_channel; ...@@ -2752,10 +2781,10 @@ task setup_sensor_channel;
num_sensor, num_sensor,
0, // num_sub_sensor 0, // num_sub_sensor
// add mode "DIRECT", "ASAP", "RELATIVE", "ABSOLUTE" and frame number // add mode "DIRECT", "ASAP", "RELATIVE", "ABSOLUTE" and frame number
19'h20000, // 0, // input [18:0] AX; 19'h0, // 19'h20000, // 0, // input [18:0] AX;
19'h20000, // 0, // input [18:0] AY; 19'h0, // 19'h20000, // 0, // input [18:0] AY;
21'h180000, //0, // input [20:0] BX; 21'h0, // 21'h180000, //0, // input [20:0] BX;
21'h180000, //0, // input [20:0] BY; 21'h0, // 21'h180000, //0, // input [20:0] BY;
'h8000, // input [18:0] C; 'h8000, // input [18:0] C;
32768, // input [16:0] scales0; 32768, // input [16:0] scales0;
32768, // input [16:0] scales1; 32768, // input [16:0] scales1;
......
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