Tested compressor version w/o 2x clock, fixed errors found

.gitignore

@@ -12,7 +12,7 @@ x393.prj
 *.old
 *.pyc
 *.pickle
-py393/dbg
+py393/dbg*
 
 includes/x393_cur_params_sim.vh
 includes/x393_cur_params_target_*.vh

.project

@@ -62,42 +62,42 @@
 		<link>
 			<name>vivado_logs/VivadoBitstream.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151028193641990.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151031114347621.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOpt.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151028193641990.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151031114347621.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPhys.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151028193641990.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151031114347621.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPower.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151028193641990.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151031114347621.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoPlace.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151028193641990.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151031114347621.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoRoute.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151028193641990.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151031114347621.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151028193155597.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151031113658557.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151028193641990.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151031114347621.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

.settings/com.elphel.vdt.FPGA_project.prefs

-FPGA_project_0_SimulationTopFile=x393_testbench03.tf
-FPGA_project_1_SimulationTopModule=x393_testbench03
+FPGA_project_0_SimulationTopFile=x393_testbench02.tf
+FPGA_project_1_SimulationTopModule=x393_testbench02
 FPGA_project_2_ImplementationTopFile=x393.v
 FPGA_project_4_part=xc7z030fbg484-1
 FPGA_project_5_part=xc7z030fbg484-1

compressor_jp/bit_stuffer_escape.v

@@ -40,7 +40,7 @@ module  bit_stuffer_escape(
     wire  [31:0] fifo_pre_out;
     // mask output for flushing
     wire  [31:0] fifo_out = fifo_pre_out & {{8{fifo_nempty[3]}},{8{fifo_nempty[2]}},{8{fifo_nempty[1]}},{8{fifo_nempty[0]}}};
-    reg    [2:0] flush_pend;
+    reg    [3:0] flush_pend;
     
     reg    [3:0] bytes_in_mask_w;
     always @* case (bytes_in)
@@ -185,17 +185,17 @@ module  bit_stuffer_escape(
         default: fifo_re_mask_w <= 'bx; // impossible num_zeros_w 
     endcase
 
-    assign fifo_re = flush_pend[1]? fifo_nempty : (rdy_w ? fifo_re_mask_w : 4'b0); // when flushing read whatever is left
+    assign fifo_re = flush_pend[2]? fifo_nempty : (rdy_w ? fifo_re_mask_w : 4'b0); // when flushing read whatever is left
 
     always @(posedge xclk) begin
-        if      (rst)   cry_ff <= 0;
-        else if (rdy_w) cry_ff <=cry_ff_w;
+        if (rst || flush_pend[2])   cry_ff <= 0;
+        else if (rdy_w)             cry_ff <= cry_ff_w;
         
-        if (rst) fifo_byte_pntr <= 0;
+        if (rst || flush_pend[2]) fifo_byte_pntr <= 0; // flush reads all the remaining data from FIFO, byte pointer should be reset too
         else if (rdy_w)           fifo_byte_pntr <= fifo_byte_pntr - num_zeros_w;
         
-        dv <= rdy_w || (flush_pend[1] && (cry_ff || (|fifo_nempty)));
-        if (rdy_w || (flush_pend[1] && (cry_ff || (|fifo_nempty)))) begin
+        dv <= rdy_w || (flush_pend[2] && (cry_ff || (|fifo_nempty)));
+        if (rdy_w || (flush_pend[2] && (cry_ff || (|fifo_nempty)))) begin
             case (sel3_w)
                 1'b0 :    d_out[31:24] <= fifo_out_barrel_w[31:24];
                 1'b1 :    d_out[31:24] <= 8'b0; 
@@ -228,14 +228,14 @@ module  bit_stuffer_escape(
         if (rst) flush_pend[1] <= 0;
         else     flush_pend[1] <= flush_pend[0] &&!flush_pend[1] && !rdy_w;
         
-        if (rst) flush_pend[2] <= 0;
-        else     flush_pend[2] <= flush_pend[1];
+        if (rst) flush_pend[3:2] <= 0;
+        else     flush_pend[3:2] <= {flush_pend[2:1]};
         
         if (rst) flush_out <=  0;
-        else     flush_out <= flush_pend[2]; 
+        else     flush_out <= flush_pend[3]; 
         
         if (rst) bytes_out <= 'bx;
-        else if ( rdy_w || flush_pend[1]) casex(bytes_rdy_w[3:0])
+        else if ( rdy_w || flush_pend[2]) casex(bytes_rdy_w[3:0])
             4'b10xx :  bytes_out <= 1;
             4'b110x :  bytes_out <= 2;
             4'b1110 :  bytes_out <= 3;

compressor_jp/huffman_snglclk.v

@@ -110,7 +110,7 @@ module huffman_snglclk    (
     
     always @(posedge xclk) begin
         if (rst) fifo_re_r <= 0;
-        else     fifo_re_r <= fifo_rdy && !(fifo_re && gotRLL) && !(|rll[5:4]);
+        else     fifo_re_r <= fifo_rdy && !(fifo_re && gotRLL && (|fifo_out[5:4])) && !(|rll[5:4]);
     
         if (rst) gotAC_r <= 0;
         else     gotAC_r <= {gotAC_r[1:0], gotAC && fifo_re};

fpga_version.vh

-    parameter FPGA_VERSION =          32'h03930054; // 'old' sensor/converter with debug
+    parameter FPGA_VERSION =          32'h03930059; // 'new' (no pclk2x, no xclk2x  clocks) sensor/converter w/o debug - ???
+//    parameter FPGA_VERSION =          32'h03930058; // 'new' (no pclk2x, no xclk2x  clocks) sensor/converter w/o debug - broken end of frame
+//    parameter FPGA_VERSION =          32'h03930057; // 'new' (no pclk2x, yes xclk2x  clocks) sensor/converter w/o debug - OK
+//    parameter FPGA_VERSION =          32'h03930056; // 'new' (no 2x clocks) sensor/converter w/o debug - broken
+//    parameter FPGA_VERSION =          32'h03930055; // 'old' sensor/converter w/o debug, fixed bug with irst - OK
+//    parameter FPGA_VERSION =          32'h03930054; // 'old' sensor/converter with debug
 //    parameter FPGA_VERSION =          32'h03930053; // trying if(reset ) reg <- 'bx    
\ No newline at end of file

includes/tasks_tests_memory.vh

@@ -149,7 +149,6 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
                   (window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0},
                   start64, lo_addr64, size64, $time);
         mode=   func_encode_mode_scanline(
-                    1'b0, // skip_too_late
                     disable_need,
                     repetitive,
                     single,
@@ -251,7 +250,6 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
             end
         endcase
         mode=   func_encode_mode_scanline(
-                    1'b0, // skip_too_late
                     disable_need,
                     repetitive,
                     single,
@@ -393,7 +391,6 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused
             end
         endcase
         mode=   func_encode_mode_scanline(
-                    1'b0, // skip_too_late
                     disable_need,
                     repetitive,
                     single,
@@ -508,7 +505,6 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
             end
         endcase
         mode=   func_encode_mode_tiled(
-                    1'b0, // skip_too_late
                     disable_need,
                     repetitive,
                     single,
@@ -641,7 +637,6 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused
             end
         endcase
         mode=   func_encode_mode_tiled(
-                    1'b0, // skip_too_late
                     disable_need,
                     repetitive,
                     single,

includes/x393_simulation_parameters.vh

@@ -38,15 +38,6 @@
 //    parameter SENSOR12BITS_NROWA   =     1,   // number of "blank rows" from last hact to end of vact
 //    parameter nAV   =      24,   //240;   // clocks from ARO to VACT (actually from en_dclkd)
 //    parameter SENSOR12BITS_NBPF =       20,   //16; // bpf length
-`ifdef HISPI
-    parameter SENSOR12BITS_NGPL =        2,   // bpf to hact
-    parameter SENSOR12BITS_NVLO =        1,   // VACT=0 in video mode (clocks)
-    //parameter tMD   =   14;    //
-    //parameter tDDO   =   10;   //   some confusion here - let's assume that it is from DCLK to Data out
-    parameter SENSOR12BITS_TMD =         1.2,   //
-    parameter SENSOR12BITS_TDDO =        0.8,   //   some confusion here - let's assume that it is from DCLK to Data out
-    parameter SENSOR12BITS_TDDO1 =       1.6,   //
-`else
     parameter SENSOR12BITS_NGPL =        8,   // bpf to hact
     parameter SENSOR12BITS_NVLO =        1,   // VACT=0 in video mode (clocks)
     //parameter tMD   =   14;    //
@@ -54,20 +45,19 @@
     parameter SENSOR12BITS_TMD =         4,   //
     parameter SENSOR12BITS_TDDO =        2,   //   some confusion here - let's assume that it is from DCLK to Data out
     parameter SENSOR12BITS_TDDO1 =       5,   //
-`endif    
 //    parameter SENSOR12BITS_TRIGDLY =     8,   // delay between trigger input and start of output (VACT) in lines
 //    parameter SENSOR12BITS_RAMP =        1,   // 1 - ramp, 0 - random (now - sensor.dat)
 //    parameter SENSOR12BITS_NEW_BAYER =   0,   // 0 - "old" tiles (16x16, 1 - new - (18x18)   
 
     parameter HISTOGRAM_LEFT =           0,   // 2;   // left   
     parameter HISTOGRAM_TOP =            8,   // 2,   // top
-    parameter HISTOGRAM_WIDTH =         22,  // 6,  // width
+    parameter HISTOGRAM_WIDTH =          6,   // width
     parameter HISTOGRAM_HEIGHT =         6,   // height
     parameter HISTOGRAM_START_PAGE =    20'h12345,
     parameter FRAME_WIDTH_ROUND_BITS =   9,  // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)
     
     parameter WOI_WIDTH=                 64,
-    parameter QUADRANTS_PXD_HACT_VACT =  6'h01, // 2 bits each: data-0, hact - 1, vact - 2 
+    parameter QUADRANTS_PXD_HACT_VACT =  6'h01 // 2 bits each: data-0, hact - 1, vact - 2 
                                                // 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
-    parameter SENSOR_PRIORITY = 0 // 1000 // 1000 - works OK, testing recover from too early Frame Sync       // 5 usec for 200MHz mclk
+    
     
\ No newline at end of file

py393/x393_cmprs.py

@@ -295,7 +295,7 @@ class X393Cmprs(object):
         @param byte32 -           32-byte columns
         @param tile_width         tile width,
         @param extra_pages        extra pages needed (1)
-        @param disable_need       disable need (preference to sesnor channels - they can not wait
+        @param disable_need       disable need (preference to sensor channels - they can not wait
         """
         tile_vstep = 16
         tile_height= 18

py393/x393_cmprs_afi.py

@@ -102,7 +102,8 @@ class X393CmprsAfi(object):
                           channel,
                           cirbuf_start = 0x27a00000,
                           circbuf_len =  0x1000000,
-                          verbose = 1):
+                          verbose = 1,
+                          num_lines_print = 20):
         """
         Returns image metadata (start, length,timestamp) or null
         @param port_afi - AFI port (0/1), currently only 0
@@ -140,13 +141,13 @@ class X393CmprsAfi(object):
         if img_start < 0:
             img_start += circbuf_len
         if verbose >0:
-            for a in range ( img_start,  img_start + 0x10, 4):
+            for a in range ( img_start,  img_start + (0x10 * num_lines_print), 4):
                 d = self.x393_mem.read_mem(cirbuf_start + a)
                 if (a % 16) == 0:
                     print ("\n%08x: "%(a),end ="" )
                 print("%02x %02x %02x %02x "%(d & 0xff, (d >> 8) & 0xff, (d >> 16) & 0xff, (d >> 24) & 0xff), end = "")
             print("\n...",end="")
-            for a0 in range ( last_image_chunk - 0x10,  last_image_chunk + 0x20, 4):
+            for a0 in range ( last_image_chunk - (0x10 * num_lines_print),  last_image_chunk + 0x20, 4):
                 a = a0
                 if (a < 0):
                     a -=circbuf_len

py393/x393_jpeg.py

@@ -820,6 +820,8 @@ ff d9
 """        
 """
 Camera compressors testing sequence
+cd /usr/local/verilog/; test_mcntrl.py @hargs
+#or (for debug)
 cd /usr/local/verilog/; test_mcntrl.py @hargs -x -v
 
 Next 2 lines needed to use jpeg functionality if the program was started w/o setup_all_sensors True None 0xf
@@ -830,7 +832,7 @@ specify_window
 measure_all "*DI"
 # Run 'measure_all' again (but w/o arguments) to perform full calibration (~10 minutes) and save results.
 # Needed after new bitstream
-# setup_all_sensors , 3-rd argument - bitmask of sesnors to initialize
+# setup_all_sensors , 3-rd argument - bitmask of sensors to initialize
 setup_all_sensors True None 0xf
 
 #reset all compressors - NOT NEEDED
@@ -849,7 +851,7 @@ compressor_control  all  None  None  None None None  3
 
 #Gamma 0.57
 program_gamma all 0 0.57 0.04
-
+program_gamma all 0 1.0 0.04
 #colors - outdoor
 write_sensor_i2c  all 1 0 0x9035000a
 write_sensor_i2c  all 1 0 0x902c000e
@@ -875,6 +877,20 @@ write_sensor_i2c  all 1 0 0x90090500
 #exposure 0x797 (default)
 write_sensor_i2c  all 1 0 0x90090797
 
+#color pattern:
+#turn off black shift (normally 0xa8)
+write_sensor_i2c  all 1 0 0x90490000
+ 
+write_sensor_i2c  all 1 0 0x90a00001
+write_sensor_i2c  all 1 0 0x90a00009
+write_sensor_i2c  all 1 0 0x90a00019
+#running 1:
+write_sensor_i2c  all 1 0 0x90a00029
+...
+write_sensor_i2c  all 1 0 0x90a00041
+
+#color pattern off: 
+write_sensor_i2c  all 1 0 0x90a00000
 
 #Get rid of the corrupted last pixel column
 #longer line (default 0xa1f)
@@ -886,7 +902,7 @@ axi_write_single_w 0x686 0x079800a3
 axi_write_single_w 0x6a6 0x079800a3
 axi_write_single_w 0x6b6 0x079800a3
 
-#run copmpressors once (#1 - stop gracefully, 0 - reset, 2 - single, 3 - repetitive with sync to sensors)
+#run compressors once (#1 - stop gracefully, 0 - reset, 2 - single, 3 - repetitive with sync to sensors)
 compressor_control all 2
 
 jpeg_write  "img.jpeg" all
@@ -898,6 +914,14 @@ compressor_control all 2
 jpeg_write  "img.jpeg" all 85
 
 -----
+#turn off black shift (normally 0xa8)
+write_sensor_i2c  all 1 0 0x90490000
+program_gamma all 0 1.0 0.00                                       
+membridge_start                                                      
+mem_dump 0x2ba00000 0x100                                            
+mem_save "/usr/local/verilog/sensor_dump_01" 0x2ba00000 0x2300000
+#scp -p root@192.168.0.8:/mnt/mmc/local/verilog/sensor_dump_01 /home/andrey/git/x393/py393/dbg1
+
 
 setup_membridge_sensor  <write_mem=False>  <cache_mode=3>  <window_width=2592>  <window_height=1944>  <window_left=0>  <window_top=0>  <membridge_start=731906048>  <membridge_end=768606208>  <verbose=1> 
 setup_membridge_sensor  0  3  2608  1936 
@@ -905,7 +929,6 @@ setup_membridge_sensor  <num_sensor=0>  <write_mem=False>  <cache_mode=3>  <wind
 setup_membridge_sensor  0 0  3  2608  1936 
 setup_membridge_sensor  1 0  3  2608  1936 
 
-
 # Trying quadrants @param quadrants -  90-degree shifts for data [1:0], hact [3:2] and vact [5:4] (6'h01), None - no change
 # set_sensor_io_ctl  <num_sensor>  <mrst=None>  <arst=None>  <aro=None>  <mmcm_rst=None>  <clk_sel=None>  <set_delays=False>  <quadrants=None> 
 

py393/x393_sens_cmprs.py

@@ -470,7 +470,7 @@ class X393SensCmprs(object):
 
         if verbose >0 :
             print ("===================== GAMMA_CTL =========================")
-        self.x393Sensor.set_sensor_gamma_ctl (# doing last to enable sesnor data when everything else is set up
+        self.x393Sensor.set_sensor_gamma_ctl (# doing last to enable sensor data when everything else is set up
             num_sensor = num_sensor, # input   [1:0] num_sensor; # sensor channel number (0..3)
             bayer =      0,
             table_page = 0,

py393/x393_sensor.py

@@ -892,14 +892,19 @@ class X393Sensor(object):
                       ):
         """
         @brief Calculate gamma table (as array of 257 unsigned short values)
-        @param gamma - gamma value (1.0 - linear)
+        @param gamma - gamma value (1.0 - linear), 0 - linear as a special case
         @param black - black level, 1.0 corresponds to 256 for 8bit values
         @return array of 257 int elements (for a single color), right-shifted to match original 0..0x3ff range
         """
+        gtable = []
+        if gamma <= 0: # special case
+            for i in range (257):
+                ig = min(i*256, 0xffff)
+                gtable.append(ig >> rshift)
+        else:    
             black256 =  max(0.0, min(255, black * 256.0))
             k=  1.0 / (256.0 - black256)
             gamma =max(0.13, min(gamma, 10.0))
-        gtable = []
             for i in range (257):
                 x=k * (i - black256)
                 x = max(x, 0.0)

sensor/sens_parallel12.v

@@ -141,7 +141,9 @@ module  sens_parallel12 #(
     reg         set_ctrl_r;
     reg         set_status_r;
     reg   [1:0] set_width_r; // to make double-cycle subtract
-    wire        set_width_ipclk; //re-clocked to pclk
+    wire        set_width_ipclk_w; //re-clocked to ipclk
+    reg         set_width_ipclk_r; // copy from mclk domain when reset is off
+    wire        set_width_ipclk = set_width_ipclk_w || set_width_ipclk_r; //re-clocked to ipclk
     reg         set_jtag_r;
     
     reg [LINE_WIDTH_BITS-1:0] line_width_m1;       // regenerated HACT duration;
@@ -224,6 +226,7 @@ module  sens_parallel12 #(
     always @ (posedge ipclk) begin
 //        irst_r <= {irst_r[1:0], prst};
         irst_r <= {irst_r[1:0], prsts}; // extended reset that includes sensor reset and rst_mmcm
+        set_width_ipclk_r <= irst_r[2] && !irst_r[1];
     end
 
     always @(posedge pclk or posedge async_prst_with_sens_mrst) begin
@@ -373,7 +376,7 @@ module  sens_parallel12 #(
         .src_clk     (mclk),              // input
         .dst_clk     (ipclk),             // input
         .in_pulse    (set_width_r[1]),    // input
-        .out_pulse   (set_width_ipclk),      // output
+        .out_pulse   (set_width_ipclk_w), // output
         .busy() // output
     );
     

simulation_modules/simul_sensor12bits.v

@@ -143,7 +143,8 @@ initial begin
    $display ("    -- new_bayer = %d ",new_bayer);
 
 //  reg   [15:0]   sensor_data[0:4095]; // up to 64 x 64 pixels
-    $readmemh("input_data/sensor.dat",sensor_data);
+//    $readmemh("input_data/sensor.dat",sensor_data);
+    $readmemh("input_data/sensor_run1.dat",sensor_data);
    c=0;
 //   {ibpf,ihact,ivact}=0;
    stopped=1;

system_defines.vh

@@ -6,9 +6,9 @@
   // if HISPI is not defined, parallel sensor interface is used for all channels
 //  `define HISPI
   
-  `define USE_PCLK2X
-  `define USE_XCLK2X
-  `define DEBUG_RING 1
+//  `define USE_PCLK2X
+//  `define USE_XCLK2X
+//  `define DEBUG_RING 1
   
   `define MEMBRIDGE_DEBUG_WRITE 1
 // Enviroment-dependent options

timing/camsync393.v

@@ -570,7 +570,7 @@ module camsync393       #(
         end
 // Why was it local_got_pclk? Also, it is a multi-bit vector
 //        rcv_done_rq <= start_en && ((ts_external_pclk && local_got_pclk) || (rcv_done_rq && rcv_run));
-// TODO: think of disabling receiving sync if sesnor is not ready yet (not done with a previous frame)
+// TODO: think of disabling receiving sync if sensor is not ready yet (not done with a previous frame)
         rcv_done_rq <= start_en && ((ts_external_pclk && (rcv_run && !rcv_run_d)) || (rcv_done_rq && rcv_run));
         //
         rcv_done_rq_d <= rcv_done_rq;

x393.v

@@ -440,7 +440,7 @@ module  x393 #(
     wire   [3:0] cmprs_page_ready;          // input
     wire   [3:0] cmprs_next_page;           // output
 
-// per-channel master (sesnor)/slave (compressor) synchronization (compressor wait until sesnor provided data)
+// per-channel master (sensor)/slave (compressor) synchronization (compressor wait until sensor provided data)
     wire                     [3:0] cmprs_frame_start_dst; // output - trigger receive (tiledc) memory channel (it will take care of single/repetitive
                                                           // these output either follows vsync_late (reclocks it) or generated in non-bonded mode
                                                           // (compress from memory)

x393_no_pclk2x_timing.xdc

+#################################################################################
+# Filename: x393_timing.xdc
+# Date:2014-02-25  
+# Author: Andrey Filippov
+# Description: DDR3 controller test with axi constraints
+#
+# Copyright (c) 2015 Elphel, Inc.
+# x393_timing.xdc is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+#  x393_timing.xdc is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/> .
+#################################################################################
+
+create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
+#x393_i/mcntrl393_i/memcntrl16/mcontr_sequencer
+
+#Clock        Period    Waveform           Attributes  Sources
+#axi_aclk     10.00000  {0.00000 5.00000}  P           {bufg_axi_aclk_i/O}
+#clk_fb       10.00000  {0.00000 5.00000}  P,G         {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT}
+#sdclk_pre    2.50000   {0.00000 1.25000}  P,G         {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0}
+#clk_pre      2.50000   {0.00000 1.25000}  P,G         {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1}
+#clk_div_pre  5.00000   {0.00000 2.50000}  P,G         {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2}
+#mclk_pre     5.00000   {1.25000 3.75000}  P,G         {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3}
+#clkfb_ref    10.00000  {0.00000 5.00000}  P,G         {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKFBOUT}
+#clk_ref_pre  3.33333   {0.00000 1.66667}  P,G         {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKOUT0}
+
+#Each list contains 2 elements - warning later in DRC
+#create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre]
+#create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre]
+#create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre]
+#create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
+#create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre]
+
+#Not available initially
+#create_generated_clock -name ddr3_sdclk [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/sdclk_pre]
+#create_generated_clock -name ddr3_clk [get_netsddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/clk_pre]
+#create_generated_clock -name ddr3_clk_div [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/clk_div_pre]
+#create_generated_clock -name ddr3_mclk [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/mclk_pre]
+#create_generated_clock -name ddr3_clk_ref [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/clk_ref_pre]
+
+# try use first from list - seems that 2 are created from the same name 
+# ddrc_sequencer_i/phy_cmd_i/phy_top_i/sdclk_pre
+# ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/sdclk_pre
+# lindex is not supported in xdc
+#create_generated_clock -name ddr3_sdclk [lindex [get_nets -hierarchical sdclk_pre] 0 ]
+#create_generated_clock -name ddr3_clk [lindex [get_nets -hierarchical clk_pre] 0 ]
+#create_generated_clock -name ddr3_clk_div [lindex [get_nets -hierarchical clk_div_pre] 0 ]
+#create_generated_clock -name ddr3_mclk [lindex [get_nets -hierarchical mclk_pre] 0 ]
+#create_generated_clock -name ddr3_clk_ref [lindex [get_nets -hierarchical clk_ref_pre] 0 ]
+
+##create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
+##create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
+##create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
+##create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
+##create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre -filter {NAME !~ */pll_base_i*} ]
+
+### Version used with eddr3
+###create_generated_clock -name ddr3_sdclk [get_nets */sdclk_pre ]
+###create_generated_clock -name ddr3_clk [get_nets */clk_pre ]
+###create_generated_clock -name ddr3_clk_div [get_nets */clk_div_pre ]
+###create_generated_clock -name ddr3_mclk [get_nets */mclk_pre ]
+###create_generated_clock -name ddr3_clk_ref [get_nets */clk_ref_pre]
+
+create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ]
+create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ]
+create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ]
+create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
+create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
+create_generated_clock -name axihp_clk [get_nets clocks393_i/dual_clock_axihp_i/clk1x_pre ]
+
+create_generated_clock -name xclk      [get_nets clocks393_i/dual_clock_xclk_i/clk1x_pre ]
+#create_generated_clock -name xclk2x    [get_nets clocks393_i/dual_clock_xclk_i/clk2x_pre ]
+
+#clock for inter - camera synchronization and event logger
+create_generated_clock -name sclk      [get_nets clocks393_i/dual_clock_sync_clk_i/clk1x_pre ]
+
+create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}]
+#Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated 
+create_generated_clock -name pclk      [get_nets clocks393_i/dual_clock_pclk_i/clk1x_pre ]
+#create_generated_clock -name pclk2x    [get_nets clocks393_i/dual_clock_pclk_i/clk2x_pre ]
+
+#Sensor-synchronous clocks
+create_generated_clock -name iclk0    [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
+create_generated_clock -name iclk2x0  [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
+
+create_generated_clock -name iclk1    [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
+create_generated_clock -name iclk2x1  [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
+
+create_generated_clock -name iclk2    [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
+create_generated_clock -name iclk2x2  [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
+
+create_generated_clock -name iclk3    [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
+create_generated_clock -name iclk2x3  [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
+
+
+
+# do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
+set_clock_groups -name ps_async_clock                 -asynchronous -group {axi_aclk}
+# do not check timing between clk_axihp_pre and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
+set_clock_groups -name ps_async_clock_axihp          -asynchronous -group {axihp_clk}
+set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk xclk2x}
+#set_clock_groups -name sensor_clocks_pclk_pclk2x     -asynchronous -group {pclk pclk2x}
+#set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk }
+set_clock_groups -name sensor_clocks_pclk_pclk2x     -asynchronous -group {pclk}
+
+set_clock_groups -name sync_logger_clocks_sclk       -asynchronous -group {sclk }
+
+set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous -group {iclk0 iclk2x0}
+set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1}
+set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2}
+set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3}
+
+set_clock_groups -name external_clock_ffclk0 -asynchronous -group {ffclk0}
\ No newline at end of file

x393_nox2_timing.xdc

+#################################################################################
+# Filename: x393_timing.xdc
+# Date:2014-02-25  
+# Author: Andrey Filippov
+# Description: DDR3 controller test with axi constraints
+#
+# Copyright (c) 2015 Elphel, Inc.
+# x393_timing.xdc is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+#  x393_timing.xdc is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/> .
+#################################################################################
+
+create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
+#x393_i/mcntrl393_i/memcntrl16/mcontr_sequencer
+
+#Clock        Period    Waveform           Attributes  Sources
+#axi_aclk     10.00000  {0.00000 5.00000}  P           {bufg_axi_aclk_i/O}
+#clk_fb       10.00000  {0.00000 5.00000}  P,G         {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT}
+#sdclk_pre    2.50000   {0.00000 1.25000}  P,G         {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0}
+#clk_pre      2.50000   {0.00000 1.25000}  P,G         {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1}
+#clk_div_pre  5.00000   {0.00000 2.50000}  P,G         {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2}
+#mclk_pre     5.00000   {1.25000 3.75000}  P,G         {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3}
+#clkfb_ref    10.00000  {0.00000 5.00000}  P,G         {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKFBOUT}
+#clk_ref_pre  3.33333   {0.00000 1.66667}  P,G         {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKOUT0}
+
+#Each list contains 2 elements - warning later in DRC
+#create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre]
+#create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre]
+#create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre]
+#create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
+#create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre]
+
+#Not available initially
+#create_generated_clock -name ddr3_sdclk [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/sdclk_pre]
+#create_generated_clock -name ddr3_clk [get_netsddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/clk_pre]
+#create_generated_clock -name ddr3_clk_div [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/clk_div_pre]
+#create_generated_clock -name ddr3_mclk [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/mclk_pre]
+#create_generated_clock -name ddr3_clk_ref [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/clk_ref_pre]
+
+# try use first from list - seems that 2 are created from the same name 
+# ddrc_sequencer_i/phy_cmd_i/phy_top_i/sdclk_pre
+# ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/sdclk_pre
+# lindex is not supported in xdc
+#create_generated_clock -name ddr3_sdclk [lindex [get_nets -hierarchical sdclk_pre] 0 ]
+#create_generated_clock -name ddr3_clk [lindex [get_nets -hierarchical clk_pre] 0 ]
+#create_generated_clock -name ddr3_clk_div [lindex [get_nets -hierarchical clk_div_pre] 0 ]
+#create_generated_clock -name ddr3_mclk [lindex [get_nets -hierarchical mclk_pre] 0 ]
+#create_generated_clock -name ddr3_clk_ref [lindex [get_nets -hierarchical clk_ref_pre] 0 ]
+
+##create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
+##create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
+##create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
+##create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
+##create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre -filter {NAME !~ */pll_base_i*} ]
+
+### Version used with eddr3
+###create_generated_clock -name ddr3_sdclk [get_nets */sdclk_pre ]
+###create_generated_clock -name ddr3_clk [get_nets */clk_pre ]
+###create_generated_clock -name ddr3_clk_div [get_nets */clk_div_pre ]
+###create_generated_clock -name ddr3_mclk [get_nets */mclk_pre ]
+###create_generated_clock -name ddr3_clk_ref [get_nets */clk_ref_pre]
+
+create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ]
+create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ]
+create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ]
+create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
+create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
+create_generated_clock -name axihp_clk [get_nets clocks393_i/dual_clock_axihp_i/clk1x_pre ]
+
+create_generated_clock -name xclk      [get_nets clocks393_i/dual_clock_xclk_i/clk1x_pre ]
+#create_generated_clock -name xclk2x    [get_nets clocks393_i/dual_clock_xclk_i/clk2x_pre ]
+
+#clock for inter - camera synchronization and event logger
+create_generated_clock -name sclk      [get_nets clocks393_i/dual_clock_sync_clk_i/clk1x_pre ]
+
+create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}]
+#Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated 
+create_generated_clock -name pclk      [get_nets clocks393_i/dual_clock_pclk_i/clk1x_pre ]
+#create_generated_clock -name pclk2x    [get_nets clocks393_i/dual_clock_pclk_i/clk2x_pre ]
+
+#Sensor-synchronous clocks
+create_generated_clock -name iclk0    [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
+create_generated_clock -name iclk2x0  [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
+
+create_generated_clock -name iclk1    [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
+create_generated_clock -name iclk2x1  [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
+
+create_generated_clock -name iclk2    [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
+create_generated_clock -name iclk2x2  [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
+
+create_generated_clock -name iclk3    [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
+create_generated_clock -name iclk2x3  [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
+
+
+
+# do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
+set_clock_groups -name ps_async_clock                 -asynchronous -group {axi_aclk}
+# do not check timing between clk_axihp_pre and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
+set_clock_groups -name ps_async_clock_axihp          -asynchronous -group {axihp_clk}
+#set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk xclk2x}
+#set_clock_groups -name sensor_clocks_pclk_pclk2x     -asynchronous -group {pclk pclk2x}
+set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk }
+set_clock_groups -name sensor_clocks_pclk_pclk2x     -asynchronous -group {pclk}
+
+set_clock_groups -name sync_logger_clocks_sclk       -asynchronous -group {sclk }
+
+set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous -group {iclk0 iclk2x0}
+set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1}
+set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2}
+set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3}
+
+set_clock_groups -name external_clock_ffclk0 -asynchronous -group {ffclk0}
\ No newline at end of file

x393_testbench03.tf

@@ -2652,7 +2652,7 @@ task setup_sensor_channel;
     // Enable arbitration of sensor-to-memory controller
     enable_memcntrl_en_dis(4'h8 + {2'b0,num_sensor}, 1);
 //            write_contol_register(MCONTR_TOP_16BIT_ADDR +  MCONTR_TOP_16BIT_CHN_EN, {16'b0,ENABLED_CHANNELS});
-    // Set sesnor channel priority - 5 usec bonus to compressor/other channels
+    // Set sensor channel priority - 5 usec bonus to compressor/other channels
     configure_channel_priority(4'h8 + {2'b0,num_sensor}, SENSOR_PRIORITY);    // lowest priority channel 1
     
     compressor_run (num_sensor, 0); // reset compressor
@@ -2817,7 +2817,7 @@ task setup_sensor_channel;
     
     TEST_TITLE = "GAMMA_CTL";
     $display("===================== TEST_%s =========================",TEST_TITLE);
-        set_sensor_gamma_ctl (// doing last to enable sesnor data when everything else is set up
+        set_sensor_gamma_ctl (// doing last to enable sensor data when everything else is set up
             num_sensor, // input   [1:0] num_sensor; // sensor channel number (0..3)
             2'h0, // 2'h3,       // input   [1:0] bayer;      // bayer shift (0..3)
             0,          // input         table_page; // table page (only used if SENS_GAMMA_BUFFER)
@@ -3906,7 +3906,7 @@ task set_camsync_mode;
     input       en;             // 1 - enable, 0 - reset module
     input [1:0] en_snd;         // <2 - NOP, 2 - disable, 3 - enable sending timestamp with sync pulse
     input [1:0] en_ts_external; // <2 - NOP, 2 - local timestamp in the frame header, 3 - use external timestamp
-    input [1:0] triggered_mode; // <2 - NOP, 2 - async sesnor mode, 3 - triggered sensor mode
+    input [1:0] triggered_mode; // <2 - NOP, 2 - async sensor mode, 3 - triggered sensor mode
     input [2:0] master_chn;     // <4 - NOP, 4..7 - set master channel
     input [4:0] chn_en;         // <16 - NOP, [3:0] - bit mask of enabled sensor channels
     reg    [31:0] data;