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Commit 30fae557 authored by Andrey Filippov's avatar Andrey Filippov
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Tested compressor version w/o 2x clock, fixed errors found

parent 62cf2722
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.gitignore
View file @ 30fae557
......@@ -12,7 +12,7 @@ x393.prj
*.old
*.pyc
*.pickle
py393/dbg
py393/dbg*
includes/x393_cur_params_sim.vh
includes/x393_cur_params_target_*.vh
......
.project
View file @ 30fae557
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151028193641990.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151031114347621.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151028193641990.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151031114347621.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151028193641990.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151031114347621.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151028193641990.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151031114347621.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151028193641990.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151031114347621.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151028193641990.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151031114347621.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151028193155597.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151031113658557.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151028193641990.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151031114347621.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......
.settings/com.elphel.vdt.FPGA_project.prefs
View file @ 30fae557
FPGA_project_0_SimulationTopFile=x393_testbench03.tf
FPGA_project_1_SimulationTopModule=x393_testbench03
FPGA_project_0_SimulationTopFile=x393_testbench02.tf
FPGA_project_1_SimulationTopModule=x393_testbench02
FPGA_project_2_ImplementationTopFile=x393.v
FPGA_project_4_part=xc7z030fbg484-1
FPGA_project_5_part=xc7z030fbg484-1
......
compressor_jp/bit_stuffer_escape.v
View file @ 30fae557
......@@ -40,7 +40,7 @@ module bit_stuffer_escape(
wire [31:0] fifo_pre_out;
// mask output for flushing
wire [31:0] fifo_out = fifo_pre_out & {{8{fifo_nempty[3]}},{8{fifo_nempty[2]}},{8{fifo_nempty[1]}},{8{fifo_nempty[0]}}};
reg [2:0] flush_pend;
reg [3:0] flush_pend;
reg [3:0] bytes_in_mask_w;
always @* case (bytes_in)
......@@ -185,17 +185,17 @@ module bit_stuffer_escape(
default: fifo_re_mask_w <= 'bx; // impossible num_zeros_w
endcase
assign fifo_re = flush_pend[1]? fifo_nempty : (rdy_w ? fifo_re_mask_w : 4'b0); // when flushing read whatever is left
assign fifo_re = flush_pend[2]? fifo_nempty : (rdy_w ? fifo_re_mask_w : 4'b0); // when flushing read whatever is left
always @(posedge xclk) begin
if (rst) cry_ff <= 0;
else if (rdy_w) cry_ff <=cry_ff_w;
if (rst || flush_pend[2]) cry_ff <= 0;
else if (rdy_w) cry_ff <= cry_ff_w;
if (rst) fifo_byte_pntr <= 0;
if (rst || flush_pend[2]) fifo_byte_pntr <= 0; // flush reads all the remaining data from FIFO, byte pointer should be reset too
else if (rdy_w) fifo_byte_pntr <= fifo_byte_pntr - num_zeros_w;
dv <= rdy_w || (flush_pend[1] && (cry_ff || (|fifo_nempty)));
if (rdy_w || (flush_pend[1] && (cry_ff || (|fifo_nempty)))) begin
dv <= rdy_w || (flush_pend[2] && (cry_ff || (|fifo_nempty)));
if (rdy_w || (flush_pend[2] && (cry_ff || (|fifo_nempty)))) begin
case (sel3_w)
1'b0 : d_out[31:24] <= fifo_out_barrel_w[31:24];
1'b1 : d_out[31:24] <= 8'b0;
......@@ -228,14 +228,14 @@ module bit_stuffer_escape(
if (rst) flush_pend[1] <= 0;
else flush_pend[1] <= flush_pend[0] &&!flush_pend[1] && !rdy_w;
if (rst) flush_pend[2] <= 0;
else flush_pend[2] <= flush_pend[1];
if (rst) flush_pend[3:2] <= 0;
else flush_pend[3:2] <= {flush_pend[2:1]};
if (rst) flush_out <= 0;
else flush_out <= flush_pend[2];
else flush_out <= flush_pend[3];
if (rst) bytes_out <= 'bx;
else if ( rdy_w || flush_pend[1]) casex(bytes_rdy_w[3:0])
else if ( rdy_w || flush_pend[2]) casex(bytes_rdy_w[3:0])
4'b10xx : bytes_out <= 1;
4'b110x : bytes_out <= 2;
4'b1110 : bytes_out <= 3;
......
compressor_jp/huffman_snglclk.v
View file @ 30fae557
......@@ -110,7 +110,7 @@ module huffman_snglclk (
always @(posedge xclk) begin
if (rst) fifo_re_r <= 0;
else fifo_re_r <= fifo_rdy && !(fifo_re && gotRLL) && !(|rll[5:4]);
else fifo_re_r <= fifo_rdy && !(fifo_re && gotRLL && (|fifo_out[5:4])) && !(|rll[5:4]);
if (rst) gotAC_r <= 0;
else gotAC_r <= {gotAC_r[1:0], gotAC && fifo_re};
......
fpga_version.vh
View file @ 30fae557
parameter FPGA_VERSION = 32'h03930054; // 'old' sensor/converter with debug
parameter FPGA_VERSION = 32'h03930059; // 'new' (no pclk2x, no xclk2x clocks) sensor/converter w/o debug - ???
// parameter FPGA_VERSION = 32'h03930058; // 'new' (no pclk2x, no xclk2x clocks) sensor/converter w/o debug - broken end of frame
// parameter FPGA_VERSION = 32'h03930057; // 'new' (no pclk2x, yes xclk2x clocks) sensor/converter w/o debug - OK
// parameter FPGA_VERSION = 32'h03930056; // 'new' (no 2x clocks) sensor/converter w/o debug - broken
// parameter FPGA_VERSION = 32'h03930055; // 'old' sensor/converter w/o debug, fixed bug with irst - OK
// parameter FPGA_VERSION = 32'h03930054; // 'old' sensor/converter with debug
// parameter FPGA_VERSION = 32'h03930053; // trying if(reset ) reg <- 'bx
\ No newline at end of file
includes/tasks_tests_memory.vh
View file @ 30fae557
......@@ -149,7 +149,6 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
(window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0},
start64, lo_addr64, size64, $time);
mode= func_encode_mode_scanline(
1'b0, // skip_too_late
disable_need,
repetitive,
single,
......@@ -251,7 +250,6 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_scanline(
1'b0, // skip_too_late
disable_need,
repetitive,
single,
......@@ -393,7 +391,6 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_scanline(
1'b0, // skip_too_late
disable_need,
repetitive,
single,
......@@ -508,7 +505,6 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_tiled(
1'b0, // skip_too_late
disable_need,
repetitive,
single,
......@@ -641,7 +637,6 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_tiled(
1'b0, // skip_too_late
disable_need,
repetitive,
single,
......
includes/x393_simulation_parameters.vh
View file @ 30fae557
......@@ -38,15 +38,6 @@
// parameter SENSOR12BITS_NROWA = 1, // number of "blank rows" from last hact to end of vact
// parameter nAV = 24, //240; // clocks from ARO to VACT (actually from en_dclkd)
// parameter SENSOR12BITS_NBPF = 20, //16; // bpf length
`ifdef HISPI
parameter SENSOR12BITS_NGPL = 2, // bpf to hact
parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks)
//parameter tMD = 14; //
//parameter tDDO = 10; // some confusion here - let's assume that it is from DCLK to Data out
parameter SENSOR12BITS_TMD = 1.2, //
parameter SENSOR12BITS_TDDO = 0.8, // some confusion here - let's assume that it is from DCLK to Data out
parameter SENSOR12BITS_TDDO1 = 1.6, //
`else
parameter SENSOR12BITS_NGPL = 8, // bpf to hact
parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks)
//parameter tMD = 14; //
......@@ -54,20 +45,19 @@
parameter SENSOR12BITS_TMD = 4, //
parameter SENSOR12BITS_TDDO = 2, // some confusion here - let's assume that it is from DCLK to Data out
parameter SENSOR12BITS_TDDO1 = 5, //
`endif
// parameter SENSOR12BITS_TRIGDLY = 8, // delay between trigger input and start of output (VACT) in lines
// parameter SENSOR12BITS_RAMP = 1, // 1 - ramp, 0 - random (now - sensor.dat)
// parameter SENSOR12BITS_NEW_BAYER = 0, // 0 - "old" tiles (16x16, 1 - new - (18x18)
parameter HISTOGRAM_LEFT = 0, // 2; // left
parameter HISTOGRAM_TOP = 8, // 2, // top
parameter HISTOGRAM_WIDTH = 22, // 6, // width
parameter HISTOGRAM_WIDTH = 6, // width
parameter HISTOGRAM_HEIGHT = 6, // height
parameter HISTOGRAM_START_PAGE = 20'h12345,
parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)
parameter WOI_WIDTH= 64,
parameter QUADRANTS_PXD_HACT_VACT = 6'h01, // 2 bits each: data-0, hact - 1, vact - 2
parameter QUADRANTS_PXD_HACT_VACT = 6'h01 // 2 bits each: data-0, hact - 1, vact - 2
// 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
parameter SENSOR_PRIORITY = 0 // 1000 // 1000 - works OK, testing recover from too early Frame Sync // 5 usec for 200MHz mclk
\ No newline at end of file
input_data/sensor_run1.dat 0 → 100644
View file @ 30fae557
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001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
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001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
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001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
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001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008 010 020 040 080 100 200 400 800 001 002 004 008
py393/dbg/x393_mcntrl.pickle
View file @ 30fae557
This source diff could not be displayed because it is too large. You can view the blob instead.
py393/x393_cmprs.py
View file @ 30fae557
......@@ -295,7 +295,7 @@ class X393Cmprs(object):
@param byte32 - 32-byte columns
@param tile_width tile width,
@param extra_pages extra pages needed (1)
@param disable_need disable need (preference to sesnor channels - they can not wait
@param disable_need disable need (preference to sensor channels - they can not wait
"""
tile_vstep = 16
tile_height= 18
......
py393/x393_cmprs_afi.py
View file @ 30fae557
......@@ -102,7 +102,8 @@ class X393CmprsAfi(object):
channel,
cirbuf_start = 0x27a00000,
circbuf_len = 0x1000000,
verbose = 1):
verbose = 1,
num_lines_print = 20):
"""
Returns image metadata (start, length,timestamp) or null
@param port_afi - AFI port (0/1), currently only 0
......@@ -140,13 +141,13 @@ class X393CmprsAfi(object):
if img_start < 0:
img_start += circbuf_len
if verbose >0:
for a in range ( img_start, img_start + 0x10, 4):
for a in range ( img_start, img_start + (0x10 * num_lines_print), 4):
d = self.x393_mem.read_mem(cirbuf_start + a)
if (a % 16) == 0:
print ("\n%08x: "%(a),end ="" )
print("%02x %02x %02x %02x "%(d & 0xff, (d >> 8) & 0xff, (d >> 16) & 0xff, (d >> 24) & 0xff), end = "")
print("\n...",end="")
for a0 in range ( last_image_chunk - 0x10, last_image_chunk + 0x20, 4):
for a0 in range ( last_image_chunk - (0x10 * num_lines_print), last_image_chunk + 0x20, 4):
a = a0
if (a < 0):
a -=circbuf_len
......
py393/x393_jpeg.py
View file @ 30fae557
......@@ -820,6 +820,8 @@ ff d9
"""
"""
Camera compressors testing sequence
cd /usr/local/verilog/; test_mcntrl.py @hargs
#or (for debug)
cd /usr/local/verilog/; test_mcntrl.py @hargs -x -v
Next 2 lines needed to use jpeg functionality if the program was started w/o setup_all_sensors True None 0xf
......@@ -830,7 +832,7 @@ specify_window
measure_all "*DI"
# Run 'measure_all' again (but w/o arguments) to perform full calibration (~10 minutes) and save results.
# Needed after new bitstream
# setup_all_sensors , 3-rd argument - bitmask of sesnors to initialize
# setup_all_sensors , 3-rd argument - bitmask of sensors to initialize
setup_all_sensors True None 0xf
#reset all compressors - NOT NEEDED
......@@ -849,7 +851,7 @@ compressor_control all None None None None None 3
#Gamma 0.57
program_gamma all 0 0.57 0.04
program_gamma all 0 1.0 0.04
#colors - outdoor
write_sensor_i2c all 1 0 0x9035000a
write_sensor_i2c all 1 0 0x902c000e
......@@ -875,6 +877,20 @@ write_sensor_i2c all 1 0 0x90090500
#exposure 0x797 (default)
write_sensor_i2c all 1 0 0x90090797
#color pattern:
#turn off black shift (normally 0xa8)
write_sensor_i2c all 1 0 0x90490000
write_sensor_i2c all 1 0 0x90a00001
write_sensor_i2c all 1 0 0x90a00009
write_sensor_i2c all 1 0 0x90a00019
#running 1:
write_sensor_i2c all 1 0 0x90a00029
...
write_sensor_i2c all 1 0 0x90a00041
#color pattern off:
write_sensor_i2c all 1 0 0x90a00000
#Get rid of the corrupted last pixel column
#longer line (default 0xa1f)
......@@ -886,7 +902,7 @@ axi_write_single_w 0x686 0x079800a3
axi_write_single_w 0x6a6 0x079800a3
axi_write_single_w 0x6b6 0x079800a3
#run copmpressors once (#1 - stop gracefully, 0 - reset, 2 - single, 3 - repetitive with sync to sensors)
#run compressors once (#1 - stop gracefully, 0 - reset, 2 - single, 3 - repetitive with sync to sensors)
compressor_control all 2
jpeg_write "img.jpeg" all
......@@ -898,6 +914,14 @@ compressor_control all 2
jpeg_write "img.jpeg" all 85
-----
#turn off black shift (normally 0xa8)
write_sensor_i2c all 1 0 0x90490000
program_gamma all 0 1.0 0.00
membridge_start
mem_dump 0x2ba00000 0x100
mem_save "/usr/local/verilog/sensor_dump_01" 0x2ba00000 0x2300000
#scp -p root@192.168.0.8:/mnt/mmc/local/verilog/sensor_dump_01 /home/andrey/git/x393/py393/dbg1
setup_membridge_sensor <write_mem=False> <cache_mode=3> <window_width=2592> <window_height=1944> <window_left=0> <window_top=0> <membridge_start=731906048> <membridge_end=768606208> <verbose=1>
setup_membridge_sensor 0 3 2608 1936
......@@ -905,7 +929,6 @@ setup_membridge_sensor <num_sensor=0> <write_mem=False> <cache_mode=3> <wind
setup_membridge_sensor 0 0 3 2608 1936
setup_membridge_sensor 1 0 3 2608 1936
# Trying quadrants @param quadrants - 90-degree shifts for data [1:0], hact [3:2] and vact [5:4] (6'h01), None - no change
# set_sensor_io_ctl <num_sensor> <mrst=None> <arst=None> <aro=None> <mmcm_rst=None> <clk_sel=None> <set_delays=False> <quadrants=None>
......
py393/x393_sens_cmprs.py
View file @ 30fae557
......@@ -470,7 +470,7 @@ class X393SensCmprs(object):
if verbose >0 :
print ("===================== GAMMA_CTL =========================")
self.x393Sensor.set_sensor_gamma_ctl (# doing last to enable sesnor data when everything else is set up
self.x393Sensor.set_sensor_gamma_ctl (# doing last to enable sensor data when everything else is set up
num_sensor = num_sensor, # input [1:0] num_sensor; # sensor channel number (0..3)
bayer = 0,
table_page = 0,
......
py393/x393_sensor.py
View file @ 30fae557
......@@ -892,14 +892,19 @@ class X393Sensor(object):
):
"""
@brief Calculate gamma table (as array of 257 unsigned short values)
@param gamma - gamma value (1.0 - linear)
@param gamma - gamma value (1.0 - linear), 0 - linear as a special case
@param black - black level, 1.0 corresponds to 256 for 8bit values
@return array of 257 int elements (for a single color), right-shifted to match original 0..0x3ff range
"""
gtable = []
if gamma <= 0: # special case
for i in range (257):
ig = min(i*256, 0xffff)
gtable.append(ig >> rshift)
else:
black256 = max(0.0, min(255, black * 256.0))
k= 1.0 / (256.0 - black256)
gamma =max(0.13, min(gamma, 10.0))
gtable = []
for i in range (257):
x=k * (i - black256)
x = max(x, 0.0)
......
sensor/sens_parallel12.v
View file @ 30fae557
......@@ -141,7 +141,9 @@ module sens_parallel12 #(
reg set_ctrl_r;
reg set_status_r;
reg [1:0] set_width_r; // to make double-cycle subtract
wire set_width_ipclk; //re-clocked to pclk
wire set_width_ipclk_w; //re-clocked to ipclk
reg set_width_ipclk_r; // copy from mclk domain when reset is off
wire set_width_ipclk = set_width_ipclk_w || set_width_ipclk_r; //re-clocked to ipclk
reg set_jtag_r;
reg [LINE_WIDTH_BITS-1:0] line_width_m1; // regenerated HACT duration;
......@@ -224,6 +226,7 @@ module sens_parallel12 #(
always @ (posedge ipclk) begin
// irst_r <= {irst_r[1:0], prst};
irst_r <= {irst_r[1:0], prsts}; // extended reset that includes sensor reset and rst_mmcm
set_width_ipclk_r <= irst_r[2] && !irst_r[1];
end
always @(posedge pclk or posedge async_prst_with_sens_mrst) begin
......@@ -373,7 +376,7 @@ module sens_parallel12 #(
.src_clk (mclk), // input
.dst_clk (ipclk), // input
.in_pulse (set_width_r[1]), // input
.out_pulse (set_width_ipclk), // output
.out_pulse (set_width_ipclk_w), // output
.busy() // output
);
......
simulation_modules/simul_sensor12bits.v
View file @ 30fae557
......@@ -143,7 +143,8 @@ initial begin
$display (" -- new_bayer = %d ",new_bayer);
// reg [15:0] sensor_data[0:4095]; // up to 64 x 64 pixels
$readmemh("input_data/sensor.dat",sensor_data);
// $readmemh("input_data/sensor.dat",sensor_data);
$readmemh("input_data/sensor_run1.dat",sensor_data);
c=0;
// {ibpf,ihact,ivact}=0;
stopped=1;
......
system_defines.vh
View file @ 30fae557
......@@ -6,9 +6,9 @@
// if HISPI is not defined, parallel sensor interface is used for all channels
// `define HISPI
`define USE_PCLK2X
`define USE_XCLK2X
`define DEBUG_RING 1
// `define USE_PCLK2X
// `define USE_XCLK2X
// `define DEBUG_RING 1
`define MEMBRIDGE_DEBUG_WRITE 1
// Enviroment-dependent options
......
timing/camsync393.v
View file @ 30fae557
......@@ -570,7 +570,7 @@ module camsync393 #(
end
// Why was it local_got_pclk? Also, it is a multi-bit vector
// rcv_done_rq <= start_en && ((ts_external_pclk && local_got_pclk) || (rcv_done_rq && rcv_run));
// TODO: think of disabling receiving sync if sesnor is not ready yet (not done with a previous frame)
// TODO: think of disabling receiving sync if sensor is not ready yet (not done with a previous frame)
rcv_done_rq <= start_en && ((ts_external_pclk && (rcv_run && !rcv_run_d)) || (rcv_done_rq && rcv_run));
//
rcv_done_rq_d <= rcv_done_rq;
......
x393.v
View file @ 30fae557
......@@ -440,7 +440,7 @@ module x393 #(
wire [3:0] cmprs_page_ready; // input
wire [3:0] cmprs_next_page; // output
// per-channel master (sesnor)/slave (compressor) synchronization (compressor wait until sesnor provided data)
// per-channel master (sensor)/slave (compressor) synchronization (compressor wait until sensor provided data)
wire [3:0] cmprs_frame_start_dst; // output - trigger receive (tiledc) memory channel (it will take care of single/repetitive
// these output either follows vsync_late (reclocks it) or generated in non-bonded mode
// (compress from memory)
......
x393_no_pclk2x_timing.xdc 0 → 100644
View file @ 30fae557
#################################################################################
# Filename: x393_timing.xdc
# Date:2014-02-25
# Author: Andrey Filippov
# Description: DDR3 controller test with axi constraints
#
# Copyright (c) 2015 Elphel, Inc.
# x393_timing.xdc is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# x393_timing.xdc is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#################################################################################
create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
#x393_i/mcntrl393_i/memcntrl16/mcontr_sequencer
#Clock Period Waveform Attributes Sources
#axi_aclk 10.00000 {0.00000 5.00000} P {bufg_axi_aclk_i/O}
#clk_fb 10.00000 {0.00000 5.00000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT}
#sdclk_pre 2.50000 {0.00000 1.25000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0}
#clk_pre 2.50000 {0.00000 1.25000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1}
#clk_div_pre 5.00000 {0.00000 2.50000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2}
#mclk_pre 5.00000 {1.25000 3.75000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3}
#clkfb_ref 10.00000 {0.00000 5.00000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKFBOUT}
#clk_ref_pre 3.33333 {0.00000 1.66667} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKOUT0}
#Each list contains 2 elements - warning later in DRC
#create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre]
#create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre]
#create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre]
#create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
#create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre]
#Not available initially
#create_generated_clock -name ddr3_sdclk [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/sdclk_pre]
#create_generated_clock -name ddr3_clk [get_netsddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/clk_pre]
#create_generated_clock -name ddr3_clk_div [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/clk_div_pre]
#create_generated_clock -name ddr3_mclk [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/mclk_pre]
#create_generated_clock -name ddr3_clk_ref [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/clk_ref_pre]
# try use first from list - seems that 2 are created from the same name
# ddrc_sequencer_i/phy_cmd_i/phy_top_i/sdclk_pre
# ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/sdclk_pre
# lindex is not supported in xdc
#create_generated_clock -name ddr3_sdclk [lindex [get_nets -hierarchical sdclk_pre] 0 ]
#create_generated_clock -name ddr3_clk [lindex [get_nets -hierarchical clk_pre] 0 ]
#create_generated_clock -name ddr3_clk_div [lindex [get_nets -hierarchical clk_div_pre] 0 ]
#create_generated_clock -name ddr3_mclk [lindex [get_nets -hierarchical mclk_pre] 0 ]
#create_generated_clock -name ddr3_clk_ref [lindex [get_nets -hierarchical clk_ref_pre] 0 ]
##create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre -filter {NAME !~ */pll_base_i*} ]
### Version used with eddr3
###create_generated_clock -name ddr3_sdclk [get_nets */sdclk_pre ]
###create_generated_clock -name ddr3_clk [get_nets */clk_pre ]
###create_generated_clock -name ddr3_clk_div [get_nets */clk_div_pre ]
###create_generated_clock -name ddr3_mclk [get_nets */mclk_pre ]
###create_generated_clock -name ddr3_clk_ref [get_nets */clk_ref_pre]
create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ]
create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ]
create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ]
create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
create_generated_clock -name axihp_clk [get_nets clocks393_i/dual_clock_axihp_i/clk1x_pre ]
create_generated_clock -name xclk [get_nets clocks393_i/dual_clock_xclk_i/clk1x_pre ]
#create_generated_clock -name xclk2x [get_nets clocks393_i/dual_clock_xclk_i/clk2x_pre ]
#clock for inter - camera synchronization and event logger
create_generated_clock -name sclk [get_nets clocks393_i/dual_clock_sync_clk_i/clk1x_pre ]
create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}]
#Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated
create_generated_clock -name pclk [get_nets clocks393_i/dual_clock_pclk_i/clk1x_pre ]
#create_generated_clock -name pclk2x [get_nets clocks393_i/dual_clock_pclk_i/clk2x_pre ]
#Sensor-synchronous clocks
create_generated_clock -name iclk0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
create_generated_clock -name iclk1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
create_generated_clock -name iclk2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
create_generated_clock -name iclk3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
# do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
# do not check timing between clk_axihp_pre and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock_axihp -asynchronous -group {axihp_clk}
set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk xclk2x}
#set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk pclk2x}
#set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk }
set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk}
set_clock_groups -name sync_logger_clocks_sclk -asynchronous -group {sclk }
set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous -group {iclk0 iclk2x0}
set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1}
set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2}
set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3}
set_clock_groups -name external_clock_ffclk0 -asynchronous -group {ffclk0}
\ No newline at end of file
x393_nox2_timing.xdc 0 → 100644
View file @ 30fae557
#################################################################################
# Filename: x393_timing.xdc
# Date:2014-02-25
# Author: Andrey Filippov
# Description: DDR3 controller test with axi constraints
#
# Copyright (c) 2015 Elphel, Inc.
# x393_timing.xdc is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# x393_timing.xdc is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#################################################################################
create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
#x393_i/mcntrl393_i/memcntrl16/mcontr_sequencer
#Clock Period Waveform Attributes Sources
#axi_aclk 10.00000 {0.00000 5.00000} P {bufg_axi_aclk_i/O}
#clk_fb 10.00000 {0.00000 5.00000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT}
#sdclk_pre 2.50000 {0.00000 1.25000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0}
#clk_pre 2.50000 {0.00000 1.25000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1}
#clk_div_pre 5.00000 {0.00000 2.50000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2}
#mclk_pre 5.00000 {1.25000 3.75000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3}
#clkfb_ref 10.00000 {0.00000 5.00000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKFBOUT}
#clk_ref_pre 3.33333 {0.00000 1.66667} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKOUT0}
#Each list contains 2 elements - warning later in DRC
#create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre]
#create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre]
#create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre]
#create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
#create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre]
#Not available initially
#create_generated_clock -name ddr3_sdclk [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/sdclk_pre]
#create_generated_clock -name ddr3_clk [get_netsddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/clk_pre]
#create_generated_clock -name ddr3_clk_div [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/clk_div_pre]
#create_generated_clock -name ddr3_mclk [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/mclk_pre]
#create_generated_clock -name ddr3_clk_ref [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/clk_ref_pre]
# try use first from list - seems that 2 are created from the same name
# ddrc_sequencer_i/phy_cmd_i/phy_top_i/sdclk_pre
# ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/sdclk_pre
# lindex is not supported in xdc
#create_generated_clock -name ddr3_sdclk [lindex [get_nets -hierarchical sdclk_pre] 0 ]
#create_generated_clock -name ddr3_clk [lindex [get_nets -hierarchical clk_pre] 0 ]
#create_generated_clock -name ddr3_clk_div [lindex [get_nets -hierarchical clk_div_pre] 0 ]
#create_generated_clock -name ddr3_mclk [lindex [get_nets -hierarchical mclk_pre] 0 ]
#create_generated_clock -name ddr3_clk_ref [lindex [get_nets -hierarchical clk_ref_pre] 0 ]
##create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre -filter {NAME !~ */pll_base_i*} ]
### Version used with eddr3
###create_generated_clock -name ddr3_sdclk [get_nets */sdclk_pre ]
###create_generated_clock -name ddr3_clk [get_nets */clk_pre ]
###create_generated_clock -name ddr3_clk_div [get_nets */clk_div_pre ]
###create_generated_clock -name ddr3_mclk [get_nets */mclk_pre ]
###create_generated_clock -name ddr3_clk_ref [get_nets */clk_ref_pre]
create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ]
create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ]
create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ]
create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
create_generated_clock -name axihp_clk [get_nets clocks393_i/dual_clock_axihp_i/clk1x_pre ]
create_generated_clock -name xclk [get_nets clocks393_i/dual_clock_xclk_i/clk1x_pre ]
#create_generated_clock -name xclk2x [get_nets clocks393_i/dual_clock_xclk_i/clk2x_pre ]
#clock for inter - camera synchronization and event logger
create_generated_clock -name sclk [get_nets clocks393_i/dual_clock_sync_clk_i/clk1x_pre ]
create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}]
#Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated
create_generated_clock -name pclk [get_nets clocks393_i/dual_clock_pclk_i/clk1x_pre ]
#create_generated_clock -name pclk2x [get_nets clocks393_i/dual_clock_pclk_i/clk2x_pre ]
#Sensor-synchronous clocks
create_generated_clock -name iclk0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
create_generated_clock -name iclk1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
create_generated_clock -name iclk2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
create_generated_clock -name iclk3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk_pre ]
create_generated_clock -name iclk2x3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_parallel12_i/ipclk2x_pre ]
# do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
# do not check timing between clk_axihp_pre and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock_axihp -asynchronous -group {axihp_clk}
#set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk xclk2x}
#set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk pclk2x}
set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk }
set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk}
set_clock_groups -name sync_logger_clocks_sclk -asynchronous -group {sclk }
set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous -group {iclk0 iclk2x0}
set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1}
set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2}
set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3}
set_clock_groups -name external_clock_ffclk0 -asynchronous -group {ffclk0}
\ No newline at end of file
x393_testbench02.sav
View file @ 30fae557
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Mon Oct 26 23:54:57 2015
[*] Sat Oct 31 16:28:08 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench02-20151012200650115.fst"
[dumpfile_mtime] "Tue Oct 13 02:42:50 2015"
[dumpfile_size] 166114960
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench02-20151031011310189.fst"
[dumpfile_mtime] "Sat Oct 31 07:46:14 2015"
[dumpfile_size] 143173820
[savefile] "/home/andrey/git/x393/x393_testbench02.sav"
[timestart] 136579500
[timestart] 100180000
[size] 1823 1180
[pos] 1922 0
*-15.149160 136632388 102872500 116192500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-22.866709 102806800 111045900 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench02.
[treeopen] x393_testbench02.compressor_control.
[treeopen] x393_testbench02.simul_axi_hp1_wr_i.
[treeopen] x393_testbench02.simul_axi_hp1_wr_i.waddr_i.
[treeopen] x393_testbench02.simul_saxi_gp0_wr_i.
[treeopen] x393_testbench02.simul_saxi_gp0_wr_i.waddr_i.
[treeopen] x393_testbench02.simul_sensor12bits_i.
[treeopen] x393_testbench02.x393_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.
......@@ -24,12 +26,16 @@
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_buf_average_i.i_CrCb_buff.genblk9.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_cmd_decode_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_macroblock_buf_iface_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_out_fifo_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_pixel_buf_iface_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.csconvert_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_escape_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_escape_i.byte_fifo_block[0].
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.quantizer393_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.table_ad_transmit_i.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.table_ad_transmit_i.i_end_burst.
[treeopen] x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.table_ad_transmit_i.i_end_burst.bit_block[0].
......@@ -50,7 +56,6 @@
[treeopen] x393_testbench02.x393_i.mcntrl393_i.
[treeopen] x393_testbench02.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.
[treeopen] x393_testbench02.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.
[treeopen] x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.
[treeopen] x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
[treeopen] x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.
[treeopen] x393_testbench02.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.
......@@ -64,8 +69,7 @@
[treeopen] x393_testbench02.x393_i.sensors393_i.histogram_saxi_i.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk7.sens_histogram_i.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.pxd_block[2].
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_fifo_i.hact_dly_16_i.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_fifo_i.hact_dly_16_i.bit_block[0].
......@@ -85,9 +89,7 @@
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.sens_histogram_i.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk7.
[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk7.sens_histogram_i.
[treeopen] x393_testbench02.x393_i.sync_resets_i.level_cross_clocks_mrst_i.
[treeopen] x393_testbench02.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].
[treeopen] x393_testbench02.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.
......@@ -95,31 +97,14 @@
[treeopen] x393_testbench02.x393_i.timing393_i.
[treeopen] x393_testbench02.x393_i.timing393_i.camsync393_i.
[treeopen] x393_testbench02.x393_i.timing393_i.rtc393_i.
[sst_width] 382
[signals_width] 318
[sst_width] 335
[signals_width] 351
[sst_expanded] 1
[sst_vpaned_height] 611
@820
x393_testbench02.TEST_TITLE[639:0]
@800200
-memcntrl_debug
@29
x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.sequence_done
@22
x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_addr[9:0]
@28
x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.pause
x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ren1
@22
x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_addr[9:0]
@28
x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_we
x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_sel
x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
@200
-
@1000200
-memcntrl_debug
@c00200
-debug_ring
@200
......@@ -205,7 +190,7 @@ x393_testbench02.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_busy[2:0]
-
@1401200
-debug_ring
@c00200
@800200
-PX1
@28
x393_testbench02.simul_sensor12bits_i.MRST
......@@ -237,7 +222,7 @@ x393_testbench02.simul_sensor12bits_i.ARO
x393_testbench02.simul_sensor12bits_i.DCLK
@28
x393_testbench02.simul_sensor12bits_i.OFST
@1401200
@1000200
-PX1
@c00200
-PX2
......@@ -286,8 +271,15 @@ x393_testbench02.simul_sensor12bits_4_i.DCLK
-PX4
@c00200
-sensor_channel
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.prst
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.prsts
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.irst
@200
-parallel12
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.irst
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.ipclk
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.data_r[31:0]
@800028
......@@ -295,6 +287,7 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
@28
(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.set_width_r[1:0]
(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.set_width_r[1:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.set_width_ipclk
@1001200
-group_end
@c00022
......@@ -556,10 +549,8 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
-group_end
@1401200
-sensor_channel
@800200
-sim_clk_tests
@1000200
-sim_clk_tests
@200
-
@c00200
-sensor_channel_2
@28
......@@ -682,10 +673,6 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.comp
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.component_color
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.component_color
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.component_color
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.flush
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.flush
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.flush
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.flush
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.fifo_ren
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.fifo_ren
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.fifo_ren
......@@ -756,7 +743,7 @@ x393_testbench02.x393_i.membridge_i.chn1wr_buf_i.rpage_in[1:0]
x393_testbench02.x393_i.membridge_i.chn1wr_buf_i.rpage_set
@1401200
-membridge_buf_wr
@c00200
@800200
-membridge_buf_rd
@22
x393_testbench02.x393_i.membridge_i.chn1rd_buf_i.data_in[63:0]
......@@ -778,7 +765,7 @@ x393_testbench02.x393_i.membridge_i.chn1rd_buf_i.wclk
x393_testbench02.x393_i.membridge_i.chn1rd_buf_i.we
x393_testbench02.x393_i.membridge_i.chn1rd_buf_i.wpage_in[1:0]
x393_testbench02.x393_i.membridge_i.chn1rd_buf_i.wpage_set
@1401200
@1000200
-membridge_buf_rd
@c00200
-linear_rw_1_sel
......@@ -1011,7 +998,6 @@ x393_testbench02.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.lsw13_zero
x393_testbench02.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mclk
@22
x393_testbench02.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mem_page_left[7:0]
x393_testbench02.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mode_reg[11:0]
@28
x393_testbench02.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.mrst
x393_testbench02.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.msw_zero
......@@ -1254,6 +1240,21 @@ x393_testbench02.x393_i.membridge_i.status_generate_i.wd[7:0]
-membridge
@800200
-compressor0
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.yc_nodc[9:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct_start
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.dct_out[12:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.pre_first_out
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.tm_out[15:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.i_dct_stage2.endv
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xdct393_i.dv
@200
-
@c00200
-func_compressor_control
@22
......@@ -1268,8 +1269,6 @@ x393_testbench02.func_compressor_control.run_mode[31:0]
x393_testbench02.func_compressor_control.tmp[31:0]
@1401200
-func_compressor_control
@200
-
@800200
-compressor_control
@22
......@@ -1314,7 +1313,7 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmpr
-
@1000200
-cmprs_frame_sync
@800200
@c00200
-quantizer
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.quantizer393_i.ds
......@@ -1335,7 +1334,7 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.quan
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.quantizer393_i.i_coring_table.raddr[11:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.quantizer393_i.tdco[3:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.quantizer393_i.qdo[12:0]
@1000200
@1401200
-quantizer
@200
-
......@@ -1343,29 +1342,9 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.quan
-huffman
@800200
-huff_fifo
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.en
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.synci
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.ds
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.ds1
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.sync_we
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.dav
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.wa[9:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.diff_a[9:0]
@c00022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.re[3:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.re[3:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.re[3:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.re[3:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.re[3:0]
@c00028
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.nempty_r[2:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.nempty_r[2:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.nempty_r[2:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.nempty_r[2:0]
@c00200
-x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.re
-x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_huff_fifo.nempty_r
@1401200
-group_end
-group_end
......@@ -1375,127 +1354,127 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_hu
-huff_fifo
@c00200
-varlen_encode
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.clk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.codel0[1:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.codel1[1:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.codel2[1:0]
@1401200
-varlen_encode
@c00200
-x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o
@1401200
-group_end
@200
-
@c00200
-x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps
@1401200
-group_end
@200
-
-
@c00200
-x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta
@1401200
-group_end
-huffman
@800200
-huffman_snglclk
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.codel[3:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.di[15:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.cycles[2:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.ds
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.d1[11:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.d[11:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.dl[4:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.do27[26:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.en
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.dv
@800200
-merge
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.in_valid
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.l[3:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.l_late[3:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.q0[10:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.q[10:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.huff_code[15:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.huff_code_len[3:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.literal[10:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.literal_len[3:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.out_bits[26:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.out_len[4:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.start
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.this0
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.this1
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.this2
@1401200
-varlen_encode
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.out_valid
@1000200
-merge
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.xclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.xclk2x
@c00022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(6)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(7)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(8)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(9)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(10)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(11)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(12)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(13)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(14)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(15)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
@1401200
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_re_r
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_rdy
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotDC
@800028
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotDC_r[2:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotDC_r[2:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotDC_r[2:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotDC_r[2:0]
@1001200
-group_end
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_or_full
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.gotLastBlock
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.last_block
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.test_lbw
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.rdy
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.stuffer_was_rdy
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.will_read
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.want_read
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_or_full
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.eob
@200
-
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotAC
@800028
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotAC_r[2:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.en2x
@c00022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotAC_r[2:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotAC_r[2:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotAC_r[2:0]
@1001200
-group_end
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
@1401200
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotRLL
@c00023
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.rll[5:0]
@29
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.rll[5:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.rll[5:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.rll[5:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.rll[5:0]
(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.rll[5:0]
(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.rll[5:0]
@1401201
-group_end
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.read_next
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotEOB
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotLastBlock
@200
-
-huffman_fifo
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.tser_a_not_d
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.tser_we
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.tdi[15:0]
@200
-
@c00022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(6)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(7)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(8)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(9)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(10)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(11)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(12)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(13)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(14)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(15)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(16)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(17)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(18)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(19)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(20)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(21)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
(22)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ta[22:0]
@1401200
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.xclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.gotLastWord
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_same_clock_i.we
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_same_clock_i.re
@800022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
(6)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
(7)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
(8)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
(9)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active_r[9:0]
@1001200
-group_end
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.twe
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.tdi[15:0]
@1401200
-huffman
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.active
@800022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_same_clock_i.fill[3:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_same_clock_i.fill[3:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_same_clock_i.fill[3:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_same_clock_i.fill[3:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.fifo_same_clock_i.fill[3:0]
@1001200
-group_end
@1000200
-huffman_snglclk
@200
-
@c00200
-table_ad_transmit
@200
......@@ -1535,7 +1514,7 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.tabl
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.table_ad_transmit_i.we_r
@1401200
-table_ad_transmit
@800200
@c00200
-encoder_DCAC
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.encoderDCAC393_i.lasti
......@@ -1592,120 +1571,12 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.enco
-group_end
@200
-
@1000200
@1401200
-encoder_DCAC
@c00200
-stuffer
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.stb_start
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_rstb
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_dout[7:0]
@800022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
(6)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
@1001200
-group_end
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.last_block
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.dl[3:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.d[15:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.stb
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.stb_start
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.abort
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.q[15:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.qv
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.flush
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.flush_now
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.flushing
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.etrax_dma[3:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.inc_imgsz32
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.imgsz32[19:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.start_time_out
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.start_sizeout
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.size_count[23:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.time_out
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.time_size_out
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.size_out[2:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.size_out_over
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.flush_end
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.trailer
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.flush_end_delayed
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.done
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.running
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.flushing
@200
-
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_pre_stb
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_data[7:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.clk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.stb_start
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.trailer
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_rstb
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_dout[7:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.trailer
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.was_trailer
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.flush_end
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.flush_end_delayed
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.will_flush
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.flush
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.force_flush
@c00028
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.abort_r[2:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.abort_r[2:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.abort_r[2:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.abort_r[2:0]
@1401200
-group_end
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.abort
@800022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
(4)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
(5)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
(6)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.ts_cycles[6:0]
@1001200
-group_end
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.vsync_late
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.sec_r[31:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.usec_r[19:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.start_time_out
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.time_out
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.time_size_out
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.start_sizeout
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.size_count[23:0]
@200
-other_module
@28
......@@ -1715,42 +1586,12 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmpr
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.aborted_frame
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.reading_frame_r
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.cmprs_run
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.qv
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.etrax_dma[3:0]
@800200
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_dv
@c00200
-timestamp_fifo
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.aclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.advance
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.advance_r[1:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.arst
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.din[7:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.dout[7:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.pre_stb
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.rclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.rcv
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.rpntr[3:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.rrst
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.rstb
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.sclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.snd
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.snd_d
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.srst
@c00022
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.wpntr[3:0]
@28
(0)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.wpntr[3:0]
(1)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.wpntr[3:0]
(2)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.wpntr[3:0]
(3)x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.wpntr[3:0]
-x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.timestamp_fifo_i.wpntr
@1401200
-group_end
@1000200
-timestamp_fifo
@200
-other
......@@ -1762,8 +1603,6 @@ x393_testbench02.x393_i.timing393_i.ts_stb[3:0]
-
@1401200
-stuffer
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_do[15:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.page_ready_chn
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.next_page_chn
......@@ -1774,22 +1613,32 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmpr
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_cmd_decode_i.cmprs_run_mclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.sigle_frame_buf
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.suspend
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.flush
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.flush_hclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_done
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_done_mclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_running_mclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.fifo_flush
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_rdy
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_en
@800200
-huffman_stuffer_meta
@200
-caller module
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.etrax_dma[3:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_do[31:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_word_number
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.flushing
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.gotLastBlock
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.gotLastWord
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_en
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_dv
@200
-
@800200
-escape
@200
-
@1000200
-escape
-huffman_stuffer_meta
@c00200
-compressor0_other
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.bayer_phase[1:0]
@22
......@@ -1844,7 +1693,6 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.enc_
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.enc_dv
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.eof_written
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.eof_written_mclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.eof_written_xclk2xn
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.fifo_count[7:0]
@28
......@@ -1861,7 +1709,6 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.firs
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.first_block_dct
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.first_block_quant
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.first_mb
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.flush
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.flush_hclk
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.focus_do[12:0]
......@@ -1885,11 +1732,6 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.hfc_
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.hifreq[31:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.hrst
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huff_dl[3:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huff_do[15:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huff_dv
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.ignore_color
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.jp4_dc_improved
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.last_mb
......@@ -1954,14 +1796,10 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stat
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.status_data[2:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.status_rq
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.status_start
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_do[15:0]
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_done
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_done_mclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_dv
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_en
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_rdy
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_running
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_running_mclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.subtract_dc
......@@ -1982,10 +1820,8 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.tser
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.tser_qe
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.vsync_late
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xclk
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xclk2x
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xfer_reset_page_rd
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xrst
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.xrst2xn
@22
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.yaddrw[7:0]
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.yc_avr[8:0]
......@@ -1993,10 +1829,10 @@ x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.yc_n
@28
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.yc_pre_first_out
x393_testbench02.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.ywe
@1401200
-compressor0_other
@1000200
-compressor0
@200
-
@c00200
-sim_cmprs_output
@22
......@@ -2977,60 +2813,16 @@ x393_testbench02.simul_saxi_gp0_wr_i.sim_wr_valid
@200
-hist-out OK
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.en_mclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_out
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.rq
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.grant
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rq_r
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_grant
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_raddr[9:0]
@800022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@28
(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@800200
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re
@1001200
-group_end
@c00022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
@28
(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(4)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(5)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(6)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(7)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(8)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(9)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(10)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(11)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(12)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(13)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(14)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(15)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(16)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(17)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(18)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(19)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(20)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(21)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(22)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(23)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(24)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(25)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(26)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(27)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(28)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(29)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(30)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
(31)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
@c00200
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do
@1401200
-group_end
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_dv
@c00022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.burst0[2:0]
@28
......@@ -3611,124 +3403,29 @@ x393_testbench02.x393_i.sensors393_i.histogram_saxi_i.wr_attr
-histogram_saxi
@c00200
-histogram01
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_out
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_out_d
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_en
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vert_woi
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr_zero_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_xfer_busy
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_xfer_done_mclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_xfer_done
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_bank_mclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_done
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_bank_pclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.monochrome
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.monochrome_pclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pre_first_line
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact
@800022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact_d[1:0]
@28
(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact_d[1:0]
(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact_d[1:0]
@800200
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact_d
@1001200
-group_end
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_en_pclk2x
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.wait_readout
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.en
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pclk2x
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.line_start_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.sof
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_di[7:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pre_first_line
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.top_margin
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.left_margin
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.left[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.top[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.width_m1[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.height_m1[15:0]
@c00022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
@28
(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(4)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(5)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(6)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(7)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(8)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(9)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(10)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(11)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(12)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(13)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(14)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
(15)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
@c00200
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr
@1401200
-group_end
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr_zero_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.top_margin
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vert_woi
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hor_woi
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_done
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.frame_active
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hcntr[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hcntr_zero_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.left_margin
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_we
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rwen
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rwaddr[9:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.to_inc[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.same_addr1
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.same_addr2
@200
-
@c00022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
@28
(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
@c00200
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi
@1401200
-group_end
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pxd_wa[3:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pxd_wa_woi[3:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pxd_ra[3:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pulse_cross_clock_hlstart_start_i.in_pulse
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hlstart
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pxd_2x[7:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hor_woi_2x
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pclk_sync
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rq
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_grant
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_rq[3:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_request
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_grant
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.en
@800022
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@28
(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@800200
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re
@1001200
-group_end
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_raddr[9:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_out
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_dv
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rq_r
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_out
@200
-
@c00200
......@@ -3792,87 +3489,6 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
-hist_mux
@200
-
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.bayer_2x[1:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.cmd_ad[7:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.cmd_stb
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.en
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.en_mclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.en_new
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.frame_active
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact_d[1:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hcntr[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hcntr_zero_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.height_m1[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_addr[9:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_addr_d2[9:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_addr_d[9:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_bank_mclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_bank_pclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_di[7:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_done
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_done_mclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_dv
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_en
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_en_pclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_en_pclk2x
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_grant
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_new[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_out
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_out_d
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_raddr[9:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_regen[1:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rq
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rq_r
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rst
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rst_pclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rwaddr[9:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rwen
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_we
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_xfer_busy
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_xfer_done
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_xfer_done_mclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hlstart
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hor_woi
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hor_woi_2x
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.inc_r[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.left[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.left_margin
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.line_start_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.lt_mclk[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.mclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.mrst
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pclk2x
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pclk_sync
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pio_addr[1:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pio_data[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pio_stb
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pre_first_line
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.prst
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pxd_2x[7:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pxd_ra[3:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pxd_ra_start[3:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pxd_wa[3:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pxd_wa_woi[3:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.set_left_top_pclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.set_left_top_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.set_width_height_pclk
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.set_width_height_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.sof
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.to_inc[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.top[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.top_margin
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vcntr_zero_w
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.vert_woi
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.wait_readout
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.wh_mclk[31:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.width_m1[15:0]
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
@1401200
-histogram01
@c00200
......@@ -3983,7 +3599,7 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.se
-chn3
@200
-
@800200
@c00200
-sens_i2c_selected
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.mclk
......@@ -4032,12 +3648,12 @@ x393_testbench02.set_sensor_i2c_command.tmp[31:0]
-task_set_sensor_i2c_cmd
@200
-
@1000200
@1401200
-sens_i2c_selected
@800200
-sens_i2c
-i2c_prot_sel
@c00200
-i2c_prot_sel
-chn1
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.i2c_start
......@@ -4213,7 +3829,7 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.send_rd
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sel_sr_in[1:0]
@1000200
@1401200
-i2c_prot_sel
@c00200
-sensor_i2c_prot
......@@ -4303,8 +3919,9 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.unused
@1401200
-sensor_i2c_prot
@800200
@c00200
-scl_sda_selected
@800200
-chn1
@22
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.i2c_dly[7:0]
......@@ -4390,9 +4007,9 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_start_restart[3:0]
@1001200
-group_end
@1000200
@1401200
-scl_sda_selected
@800200
@c00200
-scl_sda
@200
-
......@@ -4449,7 +4066,7 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.sr[8:0]
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.start_w
@1000200
@1401200
-scl_sda
@28
x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.active_cmd
......
x393_testbench02.tf
View file @ 30fae557
......@@ -195,11 +195,6 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb
wire PX4_HACT; // output
wire PX4_VACT; // output
wire PX1_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused
wire PX2_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused
wire PX3_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused
wire PX4_MCLK_PRE; // input to pixel clock mult/divisor // SuppressThisWarning VEditor - may be unused
// Sensor signals - as on FPGA pads
wire [ 7:0] sns1_dp; // inout[7:0] {PX_MRST, PXD8, PXD6, PXD4, PXD2, PXD0, PX_HACT, PX_DCLK}
wire [ 7:0] sns1_dn; // inout[7:0] {PX_ARST, PXD9, PXD7, PXD5, PXD3, PXD1, PX_VACT, PX_BPF}
......@@ -237,114 +232,10 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb
wire sns4_ctl; // inout PX_ARO/TCK
wire sns4_pg; // inout SENSPGM
// Keep signals defined even if HISPI is not, to preserve non-existing signals in .sav files of gtkwave
`ifdef HISPI
localparam PIX_CLK_DIV = 1; // scale clock from FPGA to sensor pixel clock
localparam PIX_CLK_MULT = 11; // scale clock from FPGA to sensor pixel clock
`else
localparam PIX_CLK_DIV = 1; // scale clock from FPGA to sensor pixel clock
localparam PIX_CLK_MULT = 1; // scale clock from FPGA to sensor pixel clock
`endif
`ifdef HISPI
localparam HISPI_CLK_DIV = 3; // from pixel clock to serial output pixel rate TODO: Set real ones, adjsut sensor clock too
localparam HISPI_CLK_MULT = 10; // from pixel clock to serial output pixel rate TODO: Set real ones, adjsut sensor clock too
localparam HISPI_EMBED_LINES = 2; // first lines will be marked as "embedded" (non-image data)
// localparam HISPI_MSB_FIRST = 0; // 0 - serialize LSB first, 1 - MSB first
localparam HISPI_FIFO_LOGDEPTH = 12; // 49-bit wide FIFO address bits (>log (line_length + 2)
`endif
//`ifdef HISPI
wire [3:0] PX1_LANE_P; // SuppressThisWarning VEditor - may be unused
wire [3:0] PX1_LANE_N; // SuppressThisWarning VEditor - may be unused
wire PX1_CLK_P; // SuppressThisWarning VEditor - may be unused
wire PX1_CLK_N; // SuppressThisWarning VEditor - may be unused
wire [3:0] PX1_GP; // Sensor input // SuppressThisWarning VEditor - may be unused
wire PX1_FLASH = 1'bx; // Sensor output - not yet defined // SuppressThisWarning VEditor - may be unused
wire PX1_SHUTTER = 1'bx; // Sensor output - not yet defined // SuppressThisWarning VEditor - may be unused
wire [3:0] PX2_LANE_P; // SuppressThisWarning VEditor - may be unused
wire [3:0] PX2_LANE_N; // SuppressThisWarning VEditor - may be unused
wire PX2_CLK_P; // SuppressThisWarning VEditor - may be unused
wire PX2_CLK_N; // SuppressThisWarning VEditor - may be unused
wire [3:0] PX2_GP; // Sensor input // SuppressThisWarning VEditor - may be unused
wire PX2_FLASH = 1'bx; // Sensor output - not yet defined // SuppressThisWarning VEditor - may be unused
wire PX2_SHUTTER = 1'bx; // Sensor output - not yet defined // SuppressThisWarning VEditor - may be unused
wire [3:0] PX3_LANE_P; // SuppressThisWarning VEditor - may be unused
wire [3:0] PX3_LANE_N; // SuppressThisWarning VEditor - may be unused
wire PX3_CLK_P; // SuppressThisWarning VEditor - may be unused
wire PX3_CLK_N; // SuppressThisWarning VEditor - may be unused
wire [3:0] PX3_GP; // Sensor input // SuppressThisWarning VEditor - may be unused
wire PX3_FLASH = 1'bx; // Sensor output - not yet defined // SuppressThisWarning VEditor - may be unused
wire PX3_SHUTTER = 1'bx; // Sensor output - not yet defined // SuppressThisWarning VEditor - may be unused
wire [3:0] PX4_LANE_P; // SuppressThisWarning VEditor - may be unused
wire [3:0] PX4_LANE_N; // SuppressThisWarning VEditor - may be unused
wire PX4_CLK_P; // SuppressThisWarning VEditor - may be unused
wire PX4_CLK_N; // SuppressThisWarning VEditor - may be unused
wire [3:0] PX4_GP; // Sensor input // SuppressThisWarning VEditor - may be unused
wire PX4_FLASH = 1'bx; // Sensor output - not yet defined // SuppressThisWarning VEditor - may be unused
wire PX4_SHUTTER = 1'bx; // Sensor output - not yet defined // SuppressThisWarning VEditor - may be unused
//`endif
`ifdef HISPI
assign sns1_dp[3:0] = PX1_LANE_P;
assign sns1_dn[3:0] = PX1_LANE_N;
assign sns1_clkp = PX1_CLK_P;
assign sns1_clkn = PX1_CLK_N;
// non-HiSPi signals
assign sns1_dp[4] = PX1_FLASH;
assign sns1_dn[4] = PX1_SHUTTER;
assign PX1_GP[3:0] = {sns1_dn[7],sns1_dn[6], sns1_dn[5], sns1_dp[5]};
assign PX1_MCLK_PRE = sns1_dp[6]; // from FPGA to sensor
assign PX1_MRST = sns1_dp[7]; // from FPGA to sensor
assign PX1_ARST = sns1_dn[7]; // same as GP[3]
assign PX1_ARO = sns1_dn[5]; // same as GP[1]
assign sns2_dp[3:0] = PX2_LANE_P;
assign sns2_dn[3:0] = PX2_LANE_N;
assign sns2_clkp = PX2_CLK_P;
assign sns2_clkn = PX2_CLK_N;
// non-HiSPi signals
assign sns2_dp[4] = PX1_FLASH;
assign sns2_dn[4] = PX2_SHUTTER;
assign PX2_GP[3:0] = {sns2_dn[7],sns2_dn[6], sns2_dn[5], sns2_dp[5]};
assign PX2_MCLK_PRE = sns2_dp[6]; // from FPGA to sensor
assign PX2_MRST = sns2_dp[7]; // from FPGA to sensor
assign PX2_ARST = sns2_dn[7]; // same as GP[3]
assign PX2_ARO = sns2_dn[5]; // same as GP[1]
assign sns3_dp[3:0] = PX3_LANE_P;
assign sns3_dn[3:0] = PX3_LANE_N;
assign sns3_clkp = PX3_CLK_P;
assign sns3_clkn = PX3_CLK_N;
// non-HiSPi signals
assign sns3_dp[4] = PX3_FLASH;
assign sns3_dn[4] = PX3_SHUTTER;
assign PX3_GP[3:0] = {sns3_dn[7],sns3_dn[6], sns3_dn[5], sns3_dp[5]};
assign PX3_MCLK_PRE = sns3_dp[6]; // from FPGA to sensor
assign PX3_MRST = sns3_dp[7]; // from FPGA to sensor
assign PX3_ARST = sns3_dn[7]; // same as GP[3]
assign PX3_ARO = sns3_dn[5]; // same as GP[1]
assign sns4_dp[3:0] = PX4_LANE_P;
assign sns4_dn[3:0] = PX4_LANE_N;
assign sns4_clkp = PX4_CLK_P;
assign sns4_clkn = PX4_CLK_N;
// non-HiSPi signals
assign sns4_dp[4] = PX4_FLASH;
assign sns4_dn[4] = PX4_SHUTTER;
assign PX4_GP[3:0] = {sns4_dn[7],sns4_dn[6], sns4_dn[5], sns4_dp[5]};
assign PX4_MCLK_PRE = sns4_dp[6]; // from FPGA to sensor
assign PX4_MRST = sns4_dp[7]; // from FPGA to sensor
assign PX4_ARST = sns4_dn[7]; // same as GP[3]
assign PX4_ARO = sns4_dn[5]; // same as GP[1]
`else
//connect parallel12 sensor to sensor port 1
//connect sensor to sensor port 1
assign sns1_dp[6:1] = {PX1_D[10], PX1_D[8], PX1_D[6], PX1_D[4], PX1_D[2], PX1_HACT};
assign PX1_MRST = sns1_dp[7]; // from FPGA to sensor
assign PX1_MCLK_PRE = sns1_dp[0]; // from FPGA to sensor
assign PX1_MCLK = sns1_dp[0]; // from FPGA to sensor
assign sns1_dn[6:0] = {PX1_D[11], PX1_D[9], PX1_D[7], PX1_D[5], PX1_D[3], PX1_VACT, PX1_DCLK};
assign PX1_ARST = sns1_dn[7];
assign sns1_clkn = PX1_D[0]; // inout CNVSYNC/TDI
......@@ -352,17 +243,17 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb
assign PX1_ARO = sns1_ctl; // from FPGA to sensor
assign PX2_MRST = sns2_dp[7]; // from FPGA to sensor
assign PX2_MCLK_PRE = sns2_dp[0]; // from FPGA to sensor
assign PX2_MCLK = sns2_dp[0]; // from FPGA to sensor
assign PX2_ARST = sns2_dn[7];
assign PX2_ARO = sns2_ctl; // from FPGA to sensor
assign PX3_MRST = sns3_dp[7]; // from FPGA to sensor
assign PX3_MCLK_PRE = sns3_dp[0]; // from FPGA to sensor
assign PX3_MCLK = sns3_dp[0]; // from FPGA to sensor
assign PX3_ARST = sns3_dn[7];
assign PX3_ARO = sns3_ctl; // from FPGA to sensor
assign PX4_MRST = sns4_dp[7]; // from FPGA to sensor
assign PX4_MCLK_PRE = sns4_dp[0]; // from FPGA to sensor
assign PX4_MCLK = sns4_dp[0]; // from FPGA to sensor
assign PX4_ARST = sns4_dn[7];
assign PX4_ARO = sns4_ctl; // from FPGA to sensor
......@@ -384,27 +275,24 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb
assign sns4_clkp = PX4_D[1]; // CNVCLK/TDO
`else
//connect parallel12 sensor to sensor port 2 (all data rotated left by 1 bit)
//connect sensor to sensor port 2 (all data rotated left by 1 bit)
assign sns2_dp[6:1] = {PX2_D[9], PX2_D[7], PX2_D[5], PX2_D[3], PX2_D[1], PX2_HACT};
assign sns2_dn[6:0] = {PX2_D[10], PX2_D[8], PX2_D[6], PX2_D[4], PX2_D[2], PX2_VACT, PX2_DCLK};
assign sns2_clkn = PX2_D[11]; // inout CNVSYNC/TDI
assign sns2_clkp = PX2_D[0]; // CNVCLK/TDO
//connect parallel12 sensor to sensor port 3 (all data rotated left by 2 bits
//connect sensor to sensor port 3 (all data rotated left by 2 bits
assign sns3_dp[6:1] = {PX3_D[8], PX3_D[6], PX3_D[4], PX3_D[2], PX3_D[0], PX3_HACT};
assign sns3_dn[6:0] = {PX3_D[9], PX3_D[7], PX3_D[5], PX3_D[3], PX3_D[1], PX3_VACT, PX3_DCLK};
assign sns3_clkn = PX3_D[10]; // inout CNVSYNC/TDI
assign sns3_clkp = PX3_D[11]; // CNVCLK/TDO
//connect parallel12 sensor to sensor port 4 (all data rotated left by 3 bits
//connect sensor to sensor port 4 (all data rotated left by 3 bits
assign sns4_dp[6:1] = {PX4_D[5], PX4_D[3], PX4_D[1], PX4_D[11], PX4_D[9], PX4_HACT};
assign sns4_dn[6:0] = {PX4_D[6], PX4_D[4], PX4_D[2], PX4_D[0], PX4_D[10], PX4_VACT, PX4_DCLK};
assign sns4_clkn = PX4_D[7]; // inout CNVSYNC/TDI
assign sns4_clkp = PX4_D[8]; // CNVCLK/TDO
`endif
`endif
wire [ 9:0] gpio_pins; // inout[9:0] ([6]-synco0,[7]-syncio0,[8]-synco1,[9]-syncio1)
// Connect trigger outs to triggets in (#10 needed for Icarus)
......@@ -2088,140 +1976,6 @@ simul_axi_hp_wr #(
.ffclk1 ({ffclk1n, ffclk1p}) // output[1:0]
);
// Testing parallel12 -> HiSPi simulation converter
`ifdef HISPI
par12_hispi_psp4l #(
.CLOCK_MPY (HISPI_CLK_MULT),
.CLOCK_DIV (HISPI_CLK_DIV),
.LANE0_DLY (1.3),
.LANE1_DLY (2.7),
.LANE2_DLY (0.2),
.LANE3_DLY (1.8),
.CLK_DLY (2.3),
.EMBED_LINES (HISPI_EMBED_LINES),
.MSB_FIRST (HISPI_MSB_FIRST),
.FIFO_LOGDEPTH (HISPI_FIFO_LOGDEPTH)
) par12_hispi_psp4l0_i (
.pclk ( PX1_MCLK), // input
.rst (!PX1_MRST), // input
.pxd (PX1_D), // input[11:0]
.vact (PX1_VACT), // input
.hact_in (PX1_HACT), // input
.lane_p (PX1_LANE_P), // output[3:0]
.lane_n (PX1_LANE_N), // output[3:0]
.clk_p (PX1_CLK_P), // output
.clk_n (PX1_CLK_N) // output
);
par12_hispi_psp4l #(
.CLOCK_MPY (HISPI_CLK_MULT),
.CLOCK_DIV (HISPI_CLK_DIV),
.LANE0_DLY (1.3),
.LANE1_DLY (2.7),
.LANE2_DLY (0.2),
.LANE3_DLY (1.8),
.CLK_DLY (2.3),
.EMBED_LINES (HISPI_EMBED_LINES),
.MSB_FIRST (HISPI_MSB_FIRST),
.FIFO_LOGDEPTH (HISPI_FIFO_LOGDEPTH)
) par12_hispi_psp4l1_i (
.pclk ( PX2_MCLK), // input
.rst (!PX2_MRST), // input
.pxd (PX2_D), // input[11:0]
.vact (PX2_VACT), // input
.hact_in (PX2_HACT), // input
.lane_p (PX2_LANE_P), // output[3:0]
.lane_n (PX2_LANE_N), // output[3:0]
.clk_p (PX2_CLK_P), // output
.clk_n (PX2_CLK_N) // output
);
par12_hispi_psp4l #(
.CLOCK_MPY (HISPI_CLK_MULT),
.CLOCK_DIV (HISPI_CLK_DIV),
.LANE0_DLY (1.3),
.LANE1_DLY (2.7),
.LANE2_DLY (0.2),
.LANE3_DLY (1.8),
.CLK_DLY (2.3),
.EMBED_LINES (HISPI_EMBED_LINES),
.MSB_FIRST (HISPI_MSB_FIRST),
.FIFO_LOGDEPTH (HISPI_FIFO_LOGDEPTH)
) par12_hispi_psp4l2_i (
.pclk ( PX3_MCLK), // input
.rst (!PX3_MRST), // input
.pxd (PX3_D), // input[11:0]
.vact (PX3_VACT), // input
.hact_in (PX3_HACT), // input
.lane_p (PX3_LANE_P), // output[3:0]
.lane_n (PX3_LANE_N), // output[3:0]
.clk_p (PX3_CLK_P), // output
.clk_n (PX3_CLK_N) // output
);
par12_hispi_psp4l #(
.CLOCK_MPY (HISPI_CLK_MULT),
.CLOCK_DIV (HISPI_CLK_DIV),
.LANE0_DLY (1.3),
.LANE1_DLY (2.7),
.LANE2_DLY (0.2),
.LANE3_DLY (1.8),
.CLK_DLY (2.3),
.EMBED_LINES (HISPI_EMBED_LINES),
.MSB_FIRST (HISPI_MSB_FIRST),
.FIFO_LOGDEPTH (HISPI_FIFO_LOGDEPTH)
) par12_hispi_psp4l3_i (
.pclk ( PX4_MCLK), // input
.rst (!PX4_MRST), // input
.pxd (PX4_D), // input[11:0]
.vact (PX4_VACT), // input
.hact_in (PX4_HACT), // input
.lane_p (PX4_LANE_P), // output[3:0]
.lane_n (PX4_LANE_N), // output[3:0]
.clk_p (PX4_CLK_P), // output
.clk_n (PX4_CLK_N) // output
);
`endif
simul_clk_mult_div #(
.MULTIPLIER (PIX_CLK_MULT),
.DIVISOR (PIX_CLK_DIV),
.SKIP_FIRST (5)
) simul_clk_div_mult_pix1_i (
.clk_in (PX1_MCLK_PRE), // input
.en (1'b1), // input
.clk_out (PX1_MCLK) // output
);
simul_clk_mult_div #(
.MULTIPLIER (PIX_CLK_MULT),
.DIVISOR (PIX_CLK_DIV),
.SKIP_FIRST (5)
) simul_clk_div_mult_pix2_i (
.clk_in (PX2_MCLK_PRE), // input
.en (1'b1), // input
.clk_out (PX2_MCLK) // output
);
simul_clk_mult_div #(
.MULTIPLIER (PIX_CLK_MULT),
.DIVISOR (PIX_CLK_DIV),
.SKIP_FIRST (5)
) simul_clk_div_mult_pix3_i (
.clk_in (PX3_MCLK_PRE), // input
.en (1'b1), // input
.clk_out (PX3_MCLK) // output
);
simul_clk_mult_div #(
.MULTIPLIER (PIX_CLK_MULT),
.DIVISOR (PIX_CLK_DIV),
.SKIP_FIRST (5)
) simul_clk_div_mult_pix4_i (
.clk_in (PX4_MCLK_PRE), // input
.en (1'b1), // input
.clk_out (PX4_MCLK) // output
);
simul_sensor12bits #(
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
......@@ -2242,7 +1996,7 @@ simul_axi_hp_wr #(
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP),
.new_bayer (1) //SENSOR12BITS_NEW_BAYER)
.new_bayer (0) // was 1 SENSOR12BITS_NEW_BAYER)
) simul_sensor12bits_i (
.MCLK (PX1_MCLK), // input
.MRST (PX1_MRST), // input
......@@ -2280,7 +2034,7 @@ simul_axi_hp_wr #(
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP),
.new_bayer (1) //SENSOR12BITS_NEW_BAYER)
.new_bayer (0) //SENSOR12BITS_NEW_BAYER) was 1
) simul_sensor12bits_2_i (
.MCLK (PX2_MCLK), // input
.MRST (PX2_MRST), // input
......@@ -2316,8 +2070,8 @@ simul_axi_hp_wr #(
.tDDO (SENSOR12BITS_TDDO),
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP),
.new_bayer (1) //SENSOR12BITS_NEW_BAYER)
.ramp (0), // SENSOR12BITS_RAMP),
.new_bayer (0) // was 1SENSOR12BITS_NEW_BAYER)
) simul_sensor12bits_3_i (
.MCLK (PX3_MCLK), // input
.MRST (PX3_MRST), // input
......@@ -2353,8 +2107,8 @@ simul_axi_hp_wr #(
.tDDO (SENSOR12BITS_TDDO),
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP),
.new_bayer (1) //SENSOR12BITS_NEW_BAYER)
.ramp (0),// SENSOR12BITS_RAMP),
.new_bayer (0) // was 1SENSOR12BITS_NEW_BAYER)
) simul_sensor12bits_4_i (
.MCLK (PX4_MCLK), // input
.MRST (PX4_MRST), // input
......@@ -2492,8 +2246,7 @@ task write_block_scanline_chn; // SuppressThisWarning VEditor : may be unused
end
endtask
// x393_mcntrl (no class)
function [12:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not used
input skip_too_late;
function [11:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not used
input disable_need;
input repetitive;
input single;
......@@ -2506,7 +2259,7 @@ function [12:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not us
input enable; // enable requests from this channel ( 0 will let current to finish, but not raise want/need)
input chn_reset; // immediately reset al;l the internal circuitry
reg [12:0] rslt;
reg [11:0] rslt;
begin
rslt = 0;
rslt[MCONTR_LINTILE_EN] = ~chn_reset;
......@@ -2519,14 +2272,12 @@ function [12:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not us
rslt[MCONTR_LINTILE_SINGLE] = single;
rslt[MCONTR_LINTILE_REPEAT] = repetitive;
rslt[MCONTR_LINTILE_DIS_NEED] = disable_need;
rslt[MCONTR_LINTILE_SKIP_LATE] = skip_too_late;
// func_encode_mode_tiled={byte32,keep_open,extra_pages,write_mem,enable,~chn_reset};
func_encode_mode_tiled = rslt;
end
endfunction
// x393_mcntrl (no class)
function [12:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not used
input skip_too_late;
function [11:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not used
input disable_need;
input repetitive;
input single;
......@@ -2537,7 +2288,7 @@ function [12:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not
input enable; // enable requests from this channel ( 0 will let current to finish, but not raise want/need)
input chn_reset; // immediately reset al;l the internal circuitry
reg [12:0] rslt;
reg [11:0] rslt;
begin
rslt = 0;
rslt[MCONTR_LINTILE_EN] = ~chn_reset;
......@@ -2548,8 +2299,6 @@ function [12:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not
rslt[MCONTR_LINTILE_SINGLE] = single;
rslt[MCONTR_LINTILE_REPEAT] = repetitive;
rslt[MCONTR_LINTILE_DIS_NEED] = disable_need;
rslt[MCONTR_LINTILE_SKIP_LATE] = skip_too_late;
// func_encode_mode_scanline={extra_pages,write_mem,enable,~chn_reset};
func_encode_mode_scanline = rslt;
end
......@@ -2638,8 +2387,8 @@ task setup_sensor_channel;
setup_compressor_channel(
num_sensor, // sensor channel number (0..3)
// 0, // qbank; // [6:3] quantization table page - 100% quality
1, // qbank; // [6:3] quantization table page - 85%? quality
0, // qbank; // [6:3] quantization table page - 100% quality
// 1, // qbank; // [6:3] quantization table page - 85%? quality
1, // dc_sub; // [8:7] subtract DC
CMPRS_CBIT_CMODE_JPEG18, //input [31:0] cmode; // [13:9] color mode:
// parameter CMPRS_CBIT_CMODE_JPEG18 = 4'h0, // color 4:2:0
......@@ -2656,7 +2405,7 @@ task setup_sensor_channel;
// parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
// parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks
1, // input [31:0] multi_frame; // [15:14] 0 - single-frame buffer, 1 - multiframe video memory buffer
0, // input [31:0] bayer; // [20:18] // Bayer shift
3, // 0, // input [31:0] bayer; // [20:18] // Bayer shift
0, // input [31:0] focus_mode; // [23:21] Set focus mode
3, // num_macro_cols_m1; // number of macroblock colums minus 1
1, // num_macro_rows_m1; // number of macroblock rows minus 1
......@@ -2728,10 +2477,10 @@ task setup_sensor_channel;
num_sensor,
0, // num_sub_sensor
// add mode "DIRECT", "ASAP", "RELATIVE", "ABSOLUTE" and frame number
19'h20000, // 0, // input [18:0] AX;
19'h20000, // 0, // input [18:0] AY;
21'h180000, //0, // input [20:0] BX;
21'h180000, //0, // input [20:0] BY;
19'h0, // 19'h20000, // 0, // input [18:0] AX;
19'h0, // 19'h20000, // 0, // input [18:0] AY;
21'h0, // 21'h180000, //0, // input [20:0] BX;
21'h0, // 21'h180000, //0, // input [20:0] BY;
'h8000, // input [18:0] C;
32768, // input [16:0] scales0;
32768, // input [16:0] scales1;
......@@ -3082,7 +2831,6 @@ task setup_sensor_memory;
begin
base_addr = MCONTR_SENS_BASE + MCONTR_SENS_INC * num_sensor;
mode= func_encode_mode_scanline(
1, // skip_too_late
0, // disable_need
1, // repetitive,
0, // single,
......@@ -3128,7 +2876,6 @@ task setup_compressor_memory;
base_addr = MCONTR_CMPRS_BASE + MCONTR_CMPRS_INC * num_sensor;
mode= func_encode_mode_tiled(
1'b0, // skip too late
disable_need,
1, // repetitive,
0, // single,
......
x393_testbench03.tf
View file @ 30fae557
......@@ -2652,7 +2652,7 @@ task setup_sensor_channel;
// Enable arbitration of sensor-to-memory controller
enable_memcntrl_en_dis(4'h8 + {2'b0,num_sensor}, 1);
// write_contol_register(MCONTR_TOP_16BIT_ADDR + MCONTR_TOP_16BIT_CHN_EN, {16'b0,ENABLED_CHANNELS});
// Set sesnor channel priority - 5 usec bonus to compressor/other channels
// Set sensor channel priority - 5 usec bonus to compressor/other channels
configure_channel_priority(4'h8 + {2'b0,num_sensor}, SENSOR_PRIORITY); // lowest priority channel 1
compressor_run (num_sensor, 0); // reset compressor
......@@ -2817,7 +2817,7 @@ task setup_sensor_channel;
TEST_TITLE = "GAMMA_CTL";
$display("===================== TEST_%s =========================",TEST_TITLE);
set_sensor_gamma_ctl (// doing last to enable sesnor data when everything else is set up
set_sensor_gamma_ctl (// doing last to enable sensor data when everything else is set up
num_sensor, // input [1:0] num_sensor; // sensor channel number (0..3)
2'h0, // 2'h3, // input [1:0] bayer; // bayer shift (0..3)
0, // input table_page; // table page (only used if SENS_GAMMA_BUFFER)
......@@ -3906,7 +3906,7 @@ task set_camsync_mode;
input en; // 1 - enable, 0 - reset module
input [1:0] en_snd; // <2 - NOP, 2 - disable, 3 - enable sending timestamp with sync pulse
input [1:0] en_ts_external; // <2 - NOP, 2 - local timestamp in the frame header, 3 - use external timestamp
input [1:0] triggered_mode; // <2 - NOP, 2 - async sesnor mode, 3 - triggered sensor mode
input [1:0] triggered_mode; // <2 - NOP, 2 - async sensor mode, 3 - triggered sensor mode
input [2:0] master_chn; // <4 - NOP, 4..7 - set master channel
input [4:0] chn_en; // <16 - NOP, [3:0] - bit mask of enabled sensor channels
reg [31:0] data;
......
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