Tested compressor version w/o 2x clock, fixed errors found (30fae557) · Commits · Elphel / x393

.gitignore

+1 −1

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		@@ -12,7 +12,7 @@ x393.prj
		*.old
		*.pyc
		*.pickle
		py393/dbg
		py393/dbg*

		includes/x393_cur_params_sim.vh
		includes/x393_cur_params_target_*.vh

.project

+8 −8

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		@@ -62,42 +62,42 @@
		<link>
		<name>vivado_logs/VivadoBitstream.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151028193641990.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151031114347621.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOpt.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151028193641990.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151031114347621.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPhys.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151028193641990.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151031114347621.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPower.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151028193641990.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151031114347621.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoPlace.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151028193641990.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151031114347621.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoRoute.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151028193641990.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151031114347621.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151028193155597.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151031113658557.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151028193641990.log</location>
		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151031114347621.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

.settings/com.elphel.vdt.FPGA_project.prefs

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		FPGA_project_0_SimulationTopFile=x393_testbench03.tf
		FPGA_project_1_SimulationTopModule=x393_testbench03
		FPGA_project_0_SimulationTopFile=x393_testbench02.tf
		FPGA_project_1_SimulationTopModule=x393_testbench02
		FPGA_project_2_ImplementationTopFile=x393.v
		FPGA_project_4_part=xc7z030fbg484-1
		FPGA_project_5_part=xc7z030fbg484-1

compressor_jp/bit_stuffer_escape.v

+12 −12

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		@@ -40,7 +40,7 @@ module bit_stuffer_escape(
		wire [31:0] fifo_pre_out;
		// mask output for flushing
		wire [31:0] fifo_out = fifo_pre_out & {{8{fifo_nempty[3]}},{8{fifo_nempty[2]}},{8{fifo_nempty[1]}},{8{fifo_nempty[0]}}};
		reg [2:0] flush_pend;
		reg [3:0] flush_pend;

		reg [3:0] bytes_in_mask_w;
		always @* case (bytes_in)
		@@ -185,17 +185,17 @@ module bit_stuffer_escape(
		default: fifo_re_mask_w <= 'bx; // impossible num_zeros_w
		endcase

		assign fifo_re = flush_pend[1]? fifo_nempty : (rdy_w ? fifo_re_mask_w : 4'b0); // when flushing read whatever is left
		assign fifo_re = flush_pend[2]? fifo_nempty : (rdy_w ? fifo_re_mask_w : 4'b0); // when flushing read whatever is left

		always @(posedge xclk) begin
		if (rst) cry_ff <= 0;
		if (rst \|\| flush_pend[2]) cry_ff <= 0;
		else if (rdy_w) cry_ff <= cry_ff_w;

		if (rst) fifo_byte_pntr <= 0;
		if (rst \|\| flush_pend[2]) fifo_byte_pntr <= 0; // flush reads all the remaining data from FIFO, byte pointer should be reset too
		else if (rdy_w) fifo_byte_pntr <= fifo_byte_pntr - num_zeros_w;

		dv <= rdy_w \|\| (flush_pend[1] && (cry_ff \|\| (\|fifo_nempty)));
		if (rdy_w \|\| (flush_pend[1] && (cry_ff \|\| (\|fifo_nempty)))) begin
		dv <= rdy_w \|\| (flush_pend[2] && (cry_ff \|\| (\|fifo_nempty)));
		if (rdy_w \|\| (flush_pend[2] && (cry_ff \|\| (\|fifo_nempty)))) begin
		case (sel3_w)
		1'b0 : d_out[31:24] <= fifo_out_barrel_w[31:24];
		1'b1 : d_out[31:24] <= 8'b0;
		@@ -228,14 +228,14 @@ module bit_stuffer_escape(
		if (rst) flush_pend[1] <= 0;
		else flush_pend[1] <= flush_pend[0] &&!flush_pend[1] && !rdy_w;

		if (rst) flush_pend[2] <= 0;
		else flush_pend[2] <= flush_pend[1];
		if (rst) flush_pend[3:2] <= 0;
		else flush_pend[3:2] <= {flush_pend[2:1]};

		if (rst) flush_out <= 0;
		else flush_out <= flush_pend[2];
		else flush_out <= flush_pend[3];

		if (rst) bytes_out <= 'bx;
		else if ( rdy_w \|\| flush_pend[1]) casex(bytes_rdy_w[3:0])
		else if ( rdy_w \|\| flush_pend[2]) casex(bytes_rdy_w[3:0])
		4'b10xx : bytes_out <= 1;
		4'b110x : bytes_out <= 2;
		4'b1110 : bytes_out <= 3;

compressor_jp/huffman_snglclk.v

+1 −1

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		@@ -110,7 +110,7 @@ module huffman_snglclk (

		always @(posedge xclk) begin
		if (rst) fifo_re_r <= 0;
		else fifo_re_r <= fifo_rdy && !(fifo_re && gotRLL) && !(\|rll[5:4]);
		else fifo_re_r <= fifo_rdy && !(fifo_re && gotRLL && (\|fifo_out[5:4])) && !(\|rll[5:4]);

		if (rst) gotAC_r <= 0;
		else gotAC_r <= {gotAC_r[1:0], gotAC && fifo_re};

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