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x393
Commit 3023d860 authored by Andrey Filippov's avatar Andrey Filippov
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creating a top module for all four sensor channels

parent cadd05c1
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includes/x393_parameters.vh
View file @ 3023d860
...@@ -195,7 +195,7 @@ ...@@ -195,7 +195,7 @@
parameter NUM_CYCLES_28 = 6, // parameter NUM_CYCLES_28 = 6, //
parameter NUM_CYCLES_29 = 6, // parameter NUM_CYCLES_29 = 6, //
parameter NUM_CYCLES_30 = 6, // parameter NUM_CYCLES_30 = 6, //
parameter NUM_CYCLES_31 = 6 // parameter NUM_CYCLES_31 = 6, //
// parameter CMD0_ADDR = 'h0800, // AXI write to command sequence memory // parameter CMD0_ADDR = 'h0800, // AXI write to command sequence memory
// parameter CMD0_ADDR_MASK = 'h1800, // AXI read address mask for the command sequence memory // parameter CMD0_ADDR_MASK = 'h1800, // AXI read address mask for the command sequence memory
......
memctrl/mcntrl_buf_wr.v
View file @ 3023d860
...@@ -51,12 +51,12 @@ module mcntrl_buf_wr #( ...@@ -51,12 +51,12 @@ module mcntrl_buf_wr #(
if (page_next || rpage_set) raddr <= 0; if (page_next || rpage_set) raddr <= 0;
else if (rd) raddr <= raddr+1; else if (rd) raddr <= raddr+1;
end end
// ram_1kx32w_512x64r #(
ram_var_w_var_r #( ram_var_w_var_r #(
.REGISTERS(1), .REGISTERS(1),
.LOG2WIDTH_WR(LOG2WIDTH_WR), .LOG2WIDTH_WR(LOG2WIDTH_WR),
.LOG2WIDTH_RD(6) .LOG2WIDTH_RD(6)
)ram_1kx32w_512x64r_i ( ) ram_var_w_var_r_i (
.rclk (rclk), // input .rclk (rclk), // input
.raddr ({page_r,raddr}), // input[8:0] .raddr ({page_r,raddr}), // input[8:0]
.ren (rd), // input .ren (rd), // input
......
sensor/sensor_channel.v
View file @ 3023d860
...@@ -22,9 +22,17 @@ ...@@ -22,9 +22,17 @@
module sensor_channel#( module sensor_channel#(
// parameters, individual to sensor channels and those likely to be modified // parameters, individual to sensor channels and those likely to be modified
parameter SENSOR_BASE_ADDR = 'h300, // sensor registers base address parameter SENSOR_NUMBER = 0, // sensor number (0..3)
parameter SENSI2C_STATUS_REG = 'h30, parameter SENSOR_GROUP_ADDR = 'h400, // sensor registers base address
parameter SENSIO_STATUS_REG = 'h31, parameter SENSOR_BASE_INC = 'h040, // increment for sesor channel
parameter SENSI2C_STATUS_REG_BASE = 'h30, // 4 locations" x30, x32, x34, x36
parameter SENSI2C_STATUS_REG_INC = 2, // increment to the next sensor
parameter SENSI2C_STATUS_REG_REL = 0, // 4 locations" 'h30, 'h32, 'h34, 'h36
parameter SENSIO_STATUS_REG_REL = 1, // 4 locations" 'h31, 'h33, 'h35, 'h37
// parameter SENSOR_BASE_ADDR = 'h300, // sensor registers base address
// parameter SENSI2C_STATUS_REG = 'h30,
// parameter SENSIO_STATUS_REG = 'h31,
parameter SENSOR_NUM_HISTOGRAM= 3, // number of histogram channels parameter SENSOR_NUM_HISTOGRAM= 3, // number of histogram channels
parameter HISTOGRAM_RAM_MODE = "NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32" parameter HISTOGRAM_RAM_MODE = "NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter SENS_GAMMA_NUM_CHN = 3, // number of subchannels for his sensor ports (1..4) parameter SENS_GAMMA_NUM_CHN = 3, // number of subchannels for his sensor ports (1..4)
...@@ -159,9 +167,10 @@ module sensor_channel#( ...@@ -159,9 +167,10 @@ module sensor_channel#(
output status_rq, // input request to send status downstream output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address) input status_start, // Acknowledge of the first status packet byte (address)
// 16/8-bit mode data to memory (8-bits are packed by 2 in 16 mode // 16/8-bit mode data to memory (8-bits are packed by 2 in 16 mode @posedge pclk
output [15:0] dout, output [15:0] dout, // @posedge pclk
output dout_valid, // in 8-bit mode continues pixel flow have dout_valid alternating on/off output dout_valid, // in 8-bit mode continues pixel flow have dout_valid alternating on/off
output last_in_line, // valid with dout_valid - last in line dout
output sof_out, // start of frame 1-clk pulse with the same delays as output data output sof_out, // start of frame 1-clk pulse with the same delays as output data
output eof_out, // end of frame 1-clk pulse with the same delays as output data output eof_out, // end of frame 1-clk pulse with the same delays as output data
...@@ -173,6 +182,11 @@ module sensor_channel#( ...@@ -173,6 +182,11 @@ module sensor_channel#(
output [31:0] hist_data // output[31:0] histogram data output [31:0] hist_data // output[31:0] histogram data
); );
localparam SENSOR_BASE_ADDR = (SENSOR_GROUP_ADDR + SENSOR_NUMBER * SENSOR_BASE_INC);
localparam SENSI2C_STATUS_REG = (SENSI2C_STATUS_REG_BASE + SENSOR_NUMBER * SENSI2C_STATUS_REG_INC + SENSI2C_STATUS_REG_REL);
localparam SENSIO_STATUS_REG = (SENSI2C_STATUS_REG_BASE + SENSOR_NUMBER * SENSI2C_STATUS_REG_INC + SENSIO_STATUS_REG_REL);
// parameter SENSOR_BASE_ADDR = 'h300; // sensor registers base address // parameter SENSOR_BASE_ADDR = 'h300; // sensor registers base address
localparam SENSOR_CTRL_ADDR = SENSOR_BASE_ADDR + SENSOR_CTRL_RADDR; // 'h300 localparam SENSOR_CTRL_ADDR = SENSOR_BASE_ADDR + SENSOR_CTRL_RADDR; // 'h300
localparam SENSI2C_CTRL_ADDR = SENSOR_BASE_ADDR + SENSI2C_CTRL_RADDR; // 'h302..'h303 localparam SENSI2C_CTRL_ADDR = SENSOR_BASE_ADDR + SENSI2C_CTRL_RADDR; // 'h302..'h303
...@@ -253,9 +267,10 @@ module sensor_channel#( ...@@ -253,9 +267,10 @@ module sensor_channel#(
assign sof_out = sof_out_r; assign sof_out = sof_out_r;
assign eof_out = eof_out_r; assign eof_out = eof_out_r;
assign dout_w = bit16 ? gamma_pxd_in : {gamma_data_r,gamma_pxd_out}; // assign dout_w = bit16 ? gamma_pxd_in : {gamma_data_r,gamma_pxd_out};
assign dout_w = bit16 ? gamma_pxd_in : {gamma_pxd_out,gamma_data_r}; // earlier data in LSB, later - MSB
assign dav_w = bit16 ? gamma_hact_in : dav_8bit; assign dav_w = bit16 ? gamma_hact_in : dav_8bit;
assign last_in_line = ! ( bit16 ? gamma_hact_in : gamma_hact_out);
assign hist_en = mode[SENSOR_HIST_EN_BIT+:4]; assign hist_en = mode[SENSOR_HIST_EN_BIT+:4];
assign hist_nrst = mode[SENSOR_HIST_NRST_BIT]; assign hist_nrst = mode[SENSOR_HIST_NRST_BIT];
......
sensor/sensor_membuf.v 0 → 100644
View file @ 3023d860
/*******************************************************************************
* Module: sensor_membuf
* Date:2015-07-12
* Author: andrey
* Description: Memory buffer for one sensor channel
*
* Copyright (c) 2015 Elphel, Inc .
* sensor_membuf.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sensor_membuf.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module sensor_membuf #(
parameter WADDR_WIDTH=9 // for 36Kb RAM
)(
input pclk,
input [15:0] px_data, // @posedge pclk pixel (pixel pair) data from the sensor channel
input px_valid, // px_data valid
input last_in_line, // valid with px_valid - last px_data in line
input mclk, // memory interface clock
input rpage_set, // set internal read page to rpage_in (reset pointers)
input rpage_next, // advance to next page (and reset lower bits to 0)
input buf_rd, // read buffer to memory, increment read address (regester enable will be delayed)
output [63:0] buf_dout // data out
);
reg [1:0] wpage;
reg [WADDR_WIDTH-1:0] waddr;
reg sim_rst = 1; // jsut for simulation - reset from system reset to the first rpage_set
reg [2:0] rst_pntr;
wire rst_wpntr;
always @ (posedge mclk) begin
rst_pntr <= {rst_pntr[1] &~rst_pntr[0], rst_pntr[0], rpage_set};
if (rpage_set) sim_rst <= 0;
end
always @ (posedge pclk) begin
if (rst_wpntr || (px_valid && last_in_line)) waddr <= 0;
else if (px_valid) waddr <= waddr + 1;
if (rst_wpntr) wpage <= 0;
else if (px_valid && (last_in_line || (&waddr))) wpage <= wpage + 1;
end
pulse_cross_clock rst_wpntr_i (
.rst (sim_rst),
.src_clk (mclk),
.dst_clk (pclk),
.in_pulse (rst_pntr[2]),
.out_pulse (rst_wpntr),
.busy ()
);
mcntrl_buf_wr #(
.LOG2WIDTH_WR(4) // 64 bit external interface
) chn1wr_buf_i (
.ext_clk (pclk), // input
.ext_waddr ({wpage, waddr}), // input[9:0]
.ext_we (px_valid), // input
.ext_data_in (px_data), // input[15:0] buf_wdata - from AXI
.rclk (mclk), // input
.rpage_in (2'b0), // input[1:0]
.rpage_set (rpage_set), // input @ posedge mclk
.page_next (rpage_next), // input
.page (), // output[1:0]
.rd (buf_rd), // input
.data_out (buf_dout) // output[63:0]
);
endmodule
sensor/sensors393.v 0 → 100644
View file @ 3023d860
This diff is collapsed.
system_defines.vh
View file @ 3023d860
...@@ -53,28 +53,60 @@ ...@@ -53,28 +53,60 @@
// chn 7 is disabled // chn 7 is disabled
`undef def_enable_mem_chn7 `undef def_enable_mem_chn7
// chn 8 is disabled // chn 8 is scanline w (sensor channel 0)
`undef def_enable_mem_chn8 `define def_enable_mem_chn8
`undef def_read_mem_chn8
// chn 9 is disabled `define def_write_mem_chn8
`undef def_enable_mem_chn9 `define def_scanline_chn8
`undef def_tiled_chn8
// chn 10 is disabled
`undef def_enable_mem_chn10 // chn 9 is scanline w (sensor channel 1)
`define def_enable_mem_chn9
// chn 11 is disabled `undef def_read_mem_chn9
`undef def_enable_mem_chn11 `define def_write_mem_chn9
`define def_scanline_chn9
// chn 12 is disabled `undef def_tiled_chn9
`undef def_enable_mem_chn12
// chn 10 is scanline w (sensor channel 2)
// chn 13 is disabled `define def_enable_mem_chn10
`undef def_enable_mem_chn13 `undef def_read_mem_chn10
`define def_write_mem_chn10
// chn 14 is disabled `define def_scanline_chn10
`undef def_enable_mem_chn14 `undef def_tiled_chn10
// chn 15 is disabled // chn 11 is scanline w (sensor channel 3)
`undef def_enable_mem_chn15 `define def_enable_mem_chn11
`undef def_read_mem_chn11
`define def_write_mem_chn11
`define def_scanline_chn11
`undef def_tiled_chn11
// chn 12 is tiled read (compressor channel 0)
`define def_enable_mem_chn12
`define def_read_mem_chn12
`undef def_write_mem_chn12
`undef def_scanline_chn12
`define def_tiled_chn12
// chn 12 is tiled read (compressor channel 1)
`define def_enable_mem_chn13
`define def_read_mem_chn13
`undef def_write_mem_chn13
`undef def_scanline_chn13
`define def_tiled_chn13
// chn 12 is tiled read (compressor channel 2)
`define def_enable_mem_chn14
`define def_read_mem_chn14
`undef def_write_mem_chn14
`undef def_scanline_chn14
`define def_tiled_chn14
// chn 12 is tiled read (compressor channel 3)
`define def_enable_mem_chn15
`define def_read_mem_chn15
`undef def_write_mem_chn15
`undef def_scanline_chn15
`define def_tiled_chn15
`endif `endif
\ No newline at end of file
x393.v
View file @ 3023d860
...@@ -479,7 +479,23 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0])); ...@@ -479,7 +479,23 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.NUM_CYCLES_12 (NUM_CYCLES_12), .NUM_CYCLES_12 (NUM_CYCLES_12),
.NUM_CYCLES_13 (NUM_CYCLES_13), .NUM_CYCLES_13 (NUM_CYCLES_13),
.NUM_CYCLES_14 (NUM_CYCLES_14), .NUM_CYCLES_14 (NUM_CYCLES_14),
.NUM_CYCLES_15 (NUM_CYCLES_15) .NUM_CYCLES_15 (NUM_CYCLES_15),
.NUM_CYCLES_16 (NUM_CYCLES_16),
.NUM_CYCLES_17 (NUM_CYCLES_17),
.NUM_CYCLES_18 (NUM_CYCLES_18),
.NUM_CYCLES_19 (NUM_CYCLES_19),
.NUM_CYCLES_20 (NUM_CYCLES_20),
.NUM_CYCLES_21 (NUM_CYCLES_21),
.NUM_CYCLES_22 (NUM_CYCLES_22),
.NUM_CYCLES_23 (NUM_CYCLES_23),
.NUM_CYCLES_24 (NUM_CYCLES_24),
.NUM_CYCLES_25 (NUM_CYCLES_25),
.NUM_CYCLES_26 (NUM_CYCLES_26),
.NUM_CYCLES_27 (NUM_CYCLES_27),
.NUM_CYCLES_28 (NUM_CYCLES_28),
.NUM_CYCLES_29 (NUM_CYCLES_29),
.NUM_CYCLES_30 (NUM_CYCLES_30),
.NUM_CYCLES_31 (NUM_CYCLES_31)
) cmd_mux_i ( // SuppressThisWarning ISExst: Output port <par_data>,<par_waddr>, <cseq_ackn> of the instance <cmd_mux_i> is unconnected or connected to loadless signal. ) cmd_mux_i ( // SuppressThisWarning ISExst: Output port <par_data>,<par_waddr>, <cseq_ackn> of the instance <cmd_mux_i> is unconnected or connected to loadless signal.
.axi_clk (axiwr_wclk), // input .axi_clk (axiwr_wclk), // input
.mclk (mclk), // input .mclk (mclk), // input
...@@ -778,6 +794,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0])); ...@@ -778,6 +794,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.line_unfinished_chn2 (line_unfinished_chn2), // output[15:0] .line_unfinished_chn2 (line_unfinished_chn2), // output[15:0]
.frame_number_chn2 (frame_number_chn2), // output[15:0] .frame_number_chn2 (frame_number_chn2), // output[15:0]
.suspend_chn2 (suspend_chn2), // input .suspend_chn2 (suspend_chn2), // input
.frame_start_chn3 (frame_start_chn3), // input .frame_start_chn3 (frame_start_chn3), // input
.next_page_chn3 (next_page_chn3), // input .next_page_chn3 (next_page_chn3), // input
.page_ready_chn3 (page_ready_chn3), // output .page_ready_chn3 (page_ready_chn3), // output
...@@ -785,6 +802,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0])); ...@@ -785,6 +802,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.line_unfinished_chn3 (line_unfinished_chn3), // output[15:0] .line_unfinished_chn3 (line_unfinished_chn3), // output[15:0]
.frame_number_chn3 (frame_number_chn3), // output[15:0] .frame_number_chn3 (frame_number_chn3), // output[15:0]
.suspend_chn3 (suspend_chn3), // input .suspend_chn3 (suspend_chn3), // input
.frame_start_chn4 (frame_start_chn4), // input .frame_start_chn4 (frame_start_chn4), // input
.next_page_chn4 (next_page_chn4), // input .next_page_chn4 (next_page_chn4), // input
.page_ready_chn4 (page_ready_chn4), // output .page_ready_chn4 (page_ready_chn4), // output
......
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