added frame start delay to memory channels, more python functions for debugging drivers (2f80e662) · Commits · Elphel / x393

cocotb/x393_cocotb_02.sav

+55 −19

Original line number	Diff line number	Diff line
		[*]
		[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
		[*] Fri Aug 26 03:11:57 2016
		[*] Mon Aug 29 02:48:05 2016
		[*]
		[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20160825202535502.fst"
		[dumpfile_mtime] "Fri Aug 26 02:56:41 2016"
		[dumpfile_size] 171390450
		[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20160828192314061.fst"
		[dumpfile_mtime] "Mon Aug 29 01:55:16 2016"
		[dumpfile_size] 172137517
		[savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_02.sav"
		[timestart] 177022600
		[timestart] 177303100
		[size] 1836 1171
		[pos] 0 23
		*-17.349640 177492388 123238096 124220833 174385000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
		[pos] 1920 23
		*-15.588772 177422388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
		[treeopen] x393_dut.
		[treeopen] x393_dut.ddr3_i.ddr3_i.
		[treeopen] x393_dut.simul_axi_master_wdata_i.
		@@ -34,22 +34,24 @@
		[treeopen] x393_dut.x393_i.frame_sequencer_block[0].
		[treeopen] x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.
		[treeopen] x393_dut.x393_i.gpio393_i.
		[treeopen] x393_dut.x393_i.mcntrl393_i.
		[treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
		[treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.
		[treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.
		[treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.
		[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].
		[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.
		[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.
		[treeopen] x393_dut.x393_i.sensors393_i.
		[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].
		[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
		[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.
		[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.
		[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.
		[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].
		[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].
		[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].
		[sst_width] 311
		[signals_width] 350
		[sst_width] 358
		[signals_width] 293
		[sst_expanded] 1
		[sst_vpaned_height] 540
		@820
		@@ -298,6 +300,26 @@ x393_dut.x393_i.sync_resets_i.rst_early_master
		-resets
		@800200
		-sensor_channel0
		@c00200
		-sens_sync
		@28
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_in
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_dly
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.hact
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.en
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.hact_r
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.hact_single
		@22
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.line_dly_pclk[15:0]
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.lines_left[15:0]
		@28
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.last_line
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.pre_sof_late
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_late
		@200
		-
		@1401200
		-sens_sync
		@22
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
		@28
		@@ -325,7 +347,21 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.pxd[11:0]
		-group_end
		@8022
		x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.pxd[11:0]
		x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.pxd[11:0]
		@800022
		#{x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.pxd[11:0]} (0)x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.pxd[11:0] (1)x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.pxd[11:0] (2)x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.pxd[11:0] (3)x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.pxd[11:0] (4)x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.pxd[11:0] (5)x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.pxd[11:0] (6)x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.pxd[11:0] (7)x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.pxd[11:0] (8)x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.pxd[11:0] (9)x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.pxd[11:0] (10)x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.pxd[11:0] (11)x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.pxd[11:0]
		@1001200
		-group_end
		@800200
		-scanline0
		@28
		x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start
		x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_late
		x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_delayed
		@22
		x393_dut.x393_i.sens_frame_run[3:0]
		x393_dut.x393_i.cmprs_frame_start_dst[3:0]
		@1000200
		-scanline0
		@800200
		-memory
		@28
		@@ -360,8 +396,6 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_paral
		x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.trigger_mode
		@1401200
		-debug_mmcm_clk
		@200
		-
		@1000200
		-sensor_channel0
		@c00200
		@@ -736,8 +770,10 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.buf_pxd[7:0]
		x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.buf_pxd[7:0]
		@1401200
		-compressors_all
		@800200
		@c00201
		-cmdseq_0
		@28
		x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.frame_sync
		@c00022
		x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.cmdseq_di[63:0]
		@28
		@@ -928,7 +964,7 @@ x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.valid
		x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.ackn
		@1001200
		-group_end
		@1000200
		@1401201
		-cmdseq_0
		@800200
		-cmdseq_mux
		@@ -980,13 +1016,13 @@ x393_dut.x393_i.cmd_seq_mux_i.pri_one[3:0]
		x393_dut.x393_i.cmd_seq_mux_i.chn_r[1:0]
		@1000200
		-cmdseq_mux
		@800200
		@c00200
		-gpio
		@28
		x393_dut.x393_i.gpio393_i.set_mode_w
		@22
		x393_dut.x393_i.gpio393_i.cmd_data[31:0]
		@c00023
		@c00022
		x393_dut.x393_i.gpio393_i.ds[9:0]
		@28
		(0)x393_dut.x393_i.gpio393_i.ds[9:0]
		@@ -999,7 +1035,7 @@ x393_dut.x393_i.gpio393_i.ds[9:0]
		(7)x393_dut.x393_i.gpio393_i.ds[9:0]
		(8)x393_dut.x393_i.gpio393_i.ds[9:0]
		(9)x393_dut.x393_i.gpio393_i.ds[9:0]
		@1401201
		@1401200
		-group_end
		@22
		x393_dut.x393_i.gpio393_i.ds_en_m[9:0]
		@@ -1076,7 +1112,7 @@ x393_dut.x393_i.gpio393_i.io_pins[9:0]
		(9)x393_dut.x393_i.gpio393_i.io_pins[9:0]
		@1001200
		-group_end
		@1000200
		@1401200
		-gpio
		@200
		-

fpga_version.vh

+2 −1

Original line number	Diff line number	Diff line
		@@ -35,7 +35,8 @@
		* contains all the components and scripts required to completely simulate it
		* with at least one of the Free Software programs.
		*/
		parameter FPGA_VERSION = 32'h039300a5; // parallel, fixing command sequencer and ARO 80.21%, -0.068
		parameter FPGA_VERSION = 32'h039300a6; // parallel, adding frame sync delays to mcntrl_linear 79.26, mclk and xclk violated
		// parameter FPGA_VERSION = 32'h039300a5; // parallel, fixing command sequencer and ARO 80.21%, -0.068
		// parameter FPGA_VERSION = 32'h039300a4; // parallel 79.66, -0.1
		// parameter FPGA_VERSION = 32'h039300a3; // hispi, after minor interface changes (separated control bits)80.52% -0.163
		// parameter FPGA_VERSION = 32'h039300a2; // hispi trying default placement 81.39% not met by -0.183

includes/x393_parameters.vh

+8 −3

Original line number	Diff line number	Diff line
		@@ -268,8 +268,11 @@
		// Start XY can be used when read command to start from the middle
		// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
		// Read back current address (for debugging)?

		parameter MCNTRL_TILED_TILE_WHS= 'h9, // low byte - 6-bit tile width in 8-bursts, second byte - tile height (0 - > 64),
		// 3-rd byte - vertical step (to control tile vertical overlap)
		parameter MCNTRL_SCANLINE_START_DELAY = 'ha, // Set start delay (to accommodate for the command sequencer

		parameter MCNTRL_TILED_STATUS_REG_CHN2_ADDR= 'h5,
		parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h7,
		parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
		@@ -292,6 +295,8 @@
		parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
		parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
		parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
		parameter MCNTRL_SCANLINE_DLY_WIDTH = 7, // delay start pulse by 1..64 mclk
		parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63, // initial delay value for start pulse

		// Channel test module parameters
		parameter MCNTRL_TEST01_ADDR= 'h0f0,
		@@ -531,7 +536,7 @@
		// Other parameters
		parameter SENS_SYNC_FBITS = 16, // number of bits in a frame counter for linescan mode
		parameter SENS_SYNC_LBITS = 16, // number of bits in a line counter for sof_late output (limited by eof)
		parameter SENS_SYNC_LATE_DFLT = 15, // number of lines to delay late frame sync
		parameter SENS_SYNC_LATE_DFLT = 4, // 15, // number of lines to delay late frame sync
		parameter SENS_SYNC_MINBITS = 8, // number of bits to enforce minimal frame period
		parameter SENS_SYNC_MINPER = 130, // minimal frame period (in pclk/mclk?)

memctrl/mcntrl393.v

+19 −4

Original line number	Diff line number	Diff line
		@@ -206,6 +206,8 @@ module mcntrl393 #(
		// Start XY can be used when read command to start from the middle
		// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
		// Read back current address (for debugging)?
		parameter MCNTRL_SCANLINE_START_DELAY = 'ha, // Set start delay (to accommodate for the command sequencer

		// parameter MCNTRL_SCANLINE_STATUS_REG_ADDR= 'h4,
		parameter MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR= 'h4,
		parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR= 'h6,
		@@ -235,6 +237,7 @@ module mcntrl393 #(
		// Read back current address (for debugging)?
		parameter MCNTRL_TILED_TILE_WHS= 'h9, // low byte - 6-bit tile width in 8-bursts, second byte - tile height (0 - > 64),
		// 3-rd byte - vertical step (to control tile vertical overlap)

		parameter MCNTRL_TILED_STATUS_REG_CHN2_ADDR= 'h5,
		parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h7,
		parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
		@@ -257,7 +260,9 @@ module mcntrl393 #(
		parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
		parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
		parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
		parameter MCONTR_LINTILE_SKIP_LATE = 12 // skip actual R/W operation when it is too late, advance pointers
		parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
		parameter MCNTRL_SCANLINE_DLY_WIDTH = 7, // delay start pulse by 1..64 mclk
		parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63 // initial delay value for start pulse

		) (
		input rst_in,
		@@ -1093,6 +1098,7 @@ module mcntrl393 #(
		.MCNTRL_SCANLINE_WINDOW_WH (MCNTRL_SCANLINE_WINDOW_WH),
		.MCNTRL_SCANLINE_WINDOW_X0Y0 (MCNTRL_SCANLINE_WINDOW_X0Y0),
		.MCNTRL_SCANLINE_WINDOW_STARTXY (MCNTRL_SCANLINE_WINDOW_STARTXY),
		.MCNTRL_SCANLINE_START_DELAY (MCNTRL_SCANLINE_START_DELAY),
		.MCNTRL_SCANLINE_STATUS_REG_ADDR (MCONTR_SENS_STATUS_BASE + MCONTR_SENS_STATUS_INC * i),
		.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
		.MCNTRL_SCANLINE_FRAME_PAGE_RESET (MCNTRL_SCANLINE_FRAME_PAGE_RESET),
		@@ -1105,7 +1111,9 @@ module mcntrl393 #(
		.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
		.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
		.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
		.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE)
		.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE),
		.MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH),
		.MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT)
		) mcntrl_linear_wr_sensor_i (
		.mrst (mrst), // input
		.mclk (mclk), // input
		@@ -1238,6 +1246,7 @@ module mcntrl393 #(
		.MCNTRL_SCANLINE_WINDOW_WH (MCNTRL_SCANLINE_WINDOW_WH),
		.MCNTRL_SCANLINE_WINDOW_X0Y0 (MCNTRL_SCANLINE_WINDOW_X0Y0),
		.MCNTRL_SCANLINE_WINDOW_STARTXY (MCNTRL_SCANLINE_WINDOW_STARTXY),
		.MCNTRL_SCANLINE_START_DELAY (MCNTRL_SCANLINE_START_DELAY),
		.MCNTRL_SCANLINE_STATUS_REG_ADDR (MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR),
		.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
		.MCNTRL_SCANLINE_FRAME_PAGE_RESET (MCNTRL_SCANLINE_FRAME_PAGE_RESET),
		@@ -1250,7 +1259,10 @@ module mcntrl393 #(
		.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
		.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
		.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
		.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE)
		.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE),
		.MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH),
		.MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT)

		) mcntrl_linear_rw_chn1_i (
		.mrst (mrst), // input
		.mclk (mclk), // input
		@@ -1308,6 +1320,7 @@ module mcntrl393 #(
		.MCNTRL_SCANLINE_WINDOW_WH (MCNTRL_SCANLINE_WINDOW_WH),
		.MCNTRL_SCANLINE_WINDOW_X0Y0 (MCNTRL_SCANLINE_WINDOW_X0Y0),
		.MCNTRL_SCANLINE_WINDOW_STARTXY (MCNTRL_SCANLINE_WINDOW_STARTXY),
		.MCNTRL_SCANLINE_START_DELAY (MCNTRL_SCANLINE_START_DELAY),
		.MCNTRL_SCANLINE_STATUS_REG_ADDR (MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR),
		.MCNTRL_SCANLINE_PENDING_CNTR_BITS (MCNTRL_SCANLINE_PENDING_CNTR_BITS),
		.MCNTRL_SCANLINE_FRAME_PAGE_RESET (MCNTRL_SCANLINE_FRAME_PAGE_RESET),
		@@ -1320,7 +1333,9 @@ module mcntrl393 #(
		.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
		.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
		.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
		.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE)
		.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE),
		.MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH),
		.MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT)
		) mcntrl_linear_rw_chn3_i (
		.mrst (mrst), // input
		.mclk (mclk), // input

memctrl/mcntrl_linear_rw.v

+46 −17

Original line number	Diff line number	Diff line
		@@ -60,6 +60,7 @@ module mcntrl_linear_rw #(
		// Start XY can be used when read command to start from the middle
		// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
		// Read back current address (for debugging)?
		parameter MCNTRL_SCANLINE_START_DELAY = 'ha, // Set start delay (to accommodate for the command sequencer
		parameter MCNTRL_SCANLINE_STATUS_REG_ADDR= 'h4,
		parameter MCNTRL_SCANLINE_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
		// if memory controller will allow programming several sequences in advance to
		@@ -76,7 +77,13 @@ module mcntrl_linear_rw #(
		parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
		parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
		parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
		parameter MCONTR_LINTILE_SKIP_LATE = 12 // skip actual R/W operation when it is too late, advance pointers
		parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers

		// TODO NC393: This delay may be too long for serail sensors. Make them always start to fill the
		// first buffer page, waiting for the request from mcntrl_linear during that first page. And if it will arrive -
		// just continue.
		parameter MCNTRL_SCANLINE_DLY_WIDTH = 7, // delay start pulse by 1..64 mclk
		parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63 // initial delay value for start pulse
		)(
		input mrst,
		input mclk,
		@@ -89,7 +96,7 @@ module mcntrl_linear_rw #(
		input status_start, // acknowledge of address (first byte) from downsteram

		input frame_start, // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page)
		output frame_run, // @mclk - enable pixels from sesnor to memory buffer
		output frame_run, // @mclk - enable pixels from sensor to memory buffer
		input next_page, // page was read/written from/to 4*1kB on-chip buffer
		// output page_ready, // == xfer_done, connect externally \| Single-cycle pulse indicating that a page was read/written from/to DDR3 memory
		output frame_done, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
		@@ -168,7 +175,7 @@ module mcntrl_linear_rw #(
		reg [PAR_MOD_LATENCY-1:0] recalc_r; // 1-hot CE for re-calculating registers
		// SuppressWarnings VEditor unused
		wire calc_valid; // calculated registers have valid values
		wire chn_en; // enable requests by channel (continue ones in progress), enable frame_start inputs
		wire chn_en; // enable requests by channel (continue ones in progress), enable frame_start_late inputs
		wire chn_rst; // resets command, including fifo;
		reg chn_rst_d; // delayed by 1 cycle do detect turning off
		// reg xfer_reset_page_r;
		@@ -245,9 +252,14 @@ module mcntrl_linear_rw #(
		reg [FRAME_HEIGHT_BITS:0] window_height; // (programmed) 0- max
		reg [FRAME_WIDTH_BITS-1:0] window_x0; // (programmed) window left
		reg [FRAME_HEIGHT_BITS-1:0] window_y0; // (programmed) window top
		reg [FRAME_WIDTH_BITS-1:0] start_x; // (programmed) normally 0, copied to curr_x on frame_start
		reg [FRAME_HEIGHT_BITS-1:0] start_y; // (programmed) normally 0, copied to curr_y on frame_start
		reg [FRAME_WIDTH_BITS-1:0] start_x; // (programmed) normally 0, copied to curr_x on frame_start_late
		reg [FRAME_HEIGHT_BITS-1:0] start_y; // (programmed) normally 0, copied to curr_y on frame_start_late
		reg xfer_done_d; // xfer_done delayed by 1 cycle (also includes xfer_skipped)
		reg [MCNTRL_SCANLINE_DLY_WIDTH-1:0] start_delay; // how much to delay frame start
		wire frame_start_late;
		wire set_start_delay_w;


		assign frame_number = frame_number_current;

		assign set_mode_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE);
		@@ -259,6 +271,7 @@ module mcntrl_linear_rw #(
		assign set_window_wh_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_WINDOW_WH);
		assign set_window_x0y0_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_WINDOW_X0Y0);
		assign set_window_start_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_WINDOW_STARTXY);
		assign set_start_delay_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_START_DELAY);

		assign single_frame_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE) && cmd_data[MCONTR_LINTILE_SINGLE];
		assign rst_frame_num_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE) && cmd_data[MCONTR_LINTILE_RST_FRAME];
		@@ -297,11 +310,11 @@ module mcntrl_linear_rw #(
		else is_last_frame <= frame_number_cntr == last_frame_number;

		// if (mrst) frame_start_r <= 0;
		// else frame_start_r <= {frame_start_r[3:0], frame_start & frame_en};
		// else frame_start_r <= {frame_start_r[3:0], frame_start_late & frame_en};

		if (mrst) frame_en <= 0;
		else if (single_frame_r \|\| repeat_frames) frame_en <= 1;
		else if (frame_start) frame_en <= 0;
		else if (frame_start_late) frame_en <= 0;

		if (mrst) frame_number_cntr <= 0;
		else if (rst_frame_num_r[0]) frame_number_cntr <= 0;
		@@ -341,6 +354,10 @@ module mcntrl_linear_rw #(
		start_x <= cmd_data[FRAME_WIDTH_BITS-1:0];
		start_y <= cmd_data[FRAME_HEIGHT_BITS+15:16];
		end

		if (mrst) start_delay <= MCNTRL_SCANLINE_DLY_DEFAULT;
		else if (set_start_delay_w) start_delay <= cmd_data[MCNTRL_SCANLINE_DLY_WIDTH-1:0];

		end
		assign mul_rslt_w= frame_y8_r * frame_full_width_r; // 5 MSBs will be discarded
		assign xfer_num128= xfer_num128_r[NUM_XFER_BITS-1:0];
		@@ -393,12 +410,12 @@ module mcntrl_linear_rw #(
		reg start_skip_r;
		reg skip_run = 0; // run "skip" - advance addresses, but no actual read/write
		reg xfer_reject_r;
		reg frame_start_pending; // frame_start came before previous one was finished
		reg frame_start_pending; // frame_start_late came before previous one was finished
		reg [1:0] frame_start_pending_long;
		wire xfer_done_skipped = xfer_skipped \|\| xfer_done;

		wire frame_start_delayed = frame_start_pending_long[1] && !frame_start_pending_long[0];
		wire frame_start_mod = (frame_start && !busy_r) \|\| frame_start_delayed; // when frame_start_delayed it will completely miss a frame_start
		wire frame_start_mod = (frame_start_late && !busy_r) \|\| frame_start_delayed; // when frame_start_delayed it will completely miss a frame_start_late
		assign xfer_reject = xfer_reject_r;
		assign start_skip_w = skip_too_late && want_r && !xfer_grant && !skip_run &&
		(((\|page_cntr) && frame_start_pending) \|\| ((page_cntr >= 4) && (cmd_wrmem \|\| page_cntr[0]))); //&& busy_r && skip_run;
		@@ -427,14 +444,14 @@ module mcntrl_linear_rw #(

		// if (mrst \|\| frame_start_delayed) frame_start_pending <= 0;
		if (mrst) frame_start_pending <= 0;
		// else frame_start_pending <= {frame_start_pending[0], busy_r && (frame_start_pending[0] \| frame_start)};
		else frame_start_pending <= busy_r && (frame_start_pending \| frame_start);
		// else frame_start_pending <= {frame_start_pending[0], busy_r && (frame_start_pending[0] \| frame_start_late)};
		else frame_start_pending <= busy_r && (frame_start_pending \| frame_start_late);

		if (mrst) frame_start_pending_long <= 0;
		else frame_start_pending_long <= {frame_start_pending_long[0], (busy_r \|\| skip_run) && (frame_start_pending_long[0] \| frame_start)};
		else frame_start_pending_long <= {frame_start_pending_long[0], (busy_r \|\| skip_run) && (frame_start_pending_long[0] \| frame_start_late)};

		if (mrst) frame_start_r <= 0;
		// else frame_start_r <= {frame_start_r[3:0], frame_start & frame_en};
		// else frame_start_r <= {frame_start_r[3:0], frame_start_late & frame_en};
		else frame_start_r <= {frame_start_r[3:0], frame_start_mod & frame_en};

		if (mrst \|\| disable_need) need_r <= 0;
		@@ -587,7 +604,7 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;

		if (recalc_r[0]) line_unfinished_relw_r <= curr_y + (cmd_wrmem ? 0: 1);

		// if (mrst \|\| (frame_start \|\| !chn_en)) line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid
		// if (mrst \|\| (frame_start_late \|\| !chn_en)) line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid
		if (mrst \|\| (frame_start_mod \|\| !chn_en)) line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid
		else if (recalc_r[2]) line_unfinished_r <= line_unfinished_relw_r + window_y0;

		@@ -670,5 +687,17 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
		.rq (status_rq), // output
		.start (status_start) // input
		);

		dly_var #(
		.WIDTH (1),
		.DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH)
		) frame_start_late_i (
		.clk (mclk), // input
		.rst (mrst), // input
		.dly (start_delay), // input[0:0]
		.din (frame_start), // input[0:0]
		.dout (frame_start_late) // output[0:0]
		);

		endmodule

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