Commit 2cb5c0b4 authored by Andrey Filippov's avatar Andrey Filippov

fixing recover from broken frames by optional disabling of pending frame starts, other debug

parent a6df0611
...@@ -35,9 +35,14 @@ ...@@ -35,9 +35,14 @@
* contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
parameter FPGA_VERSION = 32'h0393020f; // added test mode parameter FPGA_VERSION = 32'h03930215; // pclk phase -3.0 (multiple of 1.5)
// parameter FPGA_VERSION = 32'h0393020f; // changing MMCM phase -20.0 (use clk_fb) IBUF_LOW_PWR=FALSE // parameter FPGA_VERSION = 32'h03930214; // pclk phase +3.0 (multiple of 1.5)
// parameter FPGA_VERSION = 32'h0393020e; // changing MMCM phase -20.0 (use clk_fb) // parameter FPGA_VERSION = 32'h03930213; // bug fixing in frame_start_pending_long
// parameter FPGA_VERSION = 32'h03930212; // test mode interface, no-pending frames
// parameter FPGA_VERSION = 32'h03930211; // test mode, IBUF_LOW_PWR=TRUE, CLKFBOUT_PHASE_SENSOR = -21.0
// parameter FPGA_VERSION = 32'h03930210; // added test mode
// parameter FPGA_VERSION = 32'h0393020f; // changing MMCM phase -19.5 (use clk_fb) IBUF_LOW_PWR=FALSE
// parameter FPGA_VERSION = 32'h0393020e; // changing MMCM phase -19.5 (use clk_fb)
// parameter FPGA_VERSION = 32'h0393020e; // changing MMCM phase -19.5 (use clk_fb) // parameter FPGA_VERSION = 32'h0393020e; // changing MMCM phase -19.5 (use clk_fb)
// parameter FPGA_VERSION = 32'h0393020d; // changing MMCM phase -18.0 (use clk_fb) // parameter FPGA_VERSION = 32'h0393020d; // changing MMCM phase -18.0 (use clk_fb)
// parameter FPGA_VERSION = 32'h0393020c; // changing MMCM phase 18.0 (use clk_fb) // parameter FPGA_VERSION = 32'h0393020c; // changing MMCM phase 18.0 (use clk_fb)
......
...@@ -303,6 +303,7 @@ ...@@ -303,6 +303,7 @@
parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode) parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode)
parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory) parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
parameter MCONTR_LINTILE_NO_PENDING = 15, // ignore new frame start if previous frame is not finished
parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
...@@ -512,6 +513,16 @@ ...@@ -512,6 +513,16 @@
parameter SENS_UART_RECV_RST = 4, // 5: 4 parameter SENS_UART_RECV_RST = 4, // 5: 4
parameter SENS_UART_XMIT_START = 6, // 6 parameter SENS_UART_XMIT_START = 6, // 6
parameter SENS_UART_RECV_NEXT = 7, // 7 parameter SENS_UART_RECV_NEXT = 7, // 7
parameter SENS_ALT_STATUS = 24,
parameter SENS_ALT_STATUS_SET = 25,
parameter SENS_TEST_MODES = 26,
parameter SENS_TEST_BITS = 3,
parameter SENS_TEST_SET= 29,
parameter SENS_TEST_WIDTH_BITS = 10,
parameter SENS_TEST_HEIGHT_BITS= 10,
parameter SENS_TEST_WIDTH_INC = 3,
parameter SENS_TEST_HEIGHT_INC = 3,
//`else //`else
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20 parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6, parameter SENS_CTRL_QUADRANTS_WIDTH = 7, // 6,
...@@ -707,8 +718,8 @@ ...@@ -707,8 +718,8 @@
parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps parameter CLKIN_PERIOD_SENSOR = 37.037, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz) parameter CLKFBOUT_MULT_SENSOR = 30, // 27 MHz --> 810 MHz (3*270MHz)
//MMCME2_ADV_i has a CLKFBOUT_PHASE value (-20.000) with CLKFBOUT_USE_FINE_PS set to FALSE. It should be a multiple of [45 / CLKFBOUT_MULT_F] = [45 / 30.000] = 1.500. //MMCME2_ADV_i has a CLKFBOUT_PHASE value (-20.000) with CLKFBOUT_USE_FINE_PS set to FALSE. It should be a multiple of [45 / CLKFBOUT_MULT_F] = [45 / 30.000] = 1.500.
parameter CLKFBOUT_PHASE_SENSOR = -19.5, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) parameter CLKFBOUT_PHASE_SENSOR = -21.0, // 19.5, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000, parameter IPCLK_PHASE = -3.000, // trying both ways (PCLK_PHASE inside sens_103993)
parameter IPCLK2X_PHASE = 0.000, parameter IPCLK2X_PHASE = 0.000,
`ifdef TWEAKING_IOSTANDARD `ifdef TWEAKING_IOSTANDARD
parameter PXD_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage parameter PXD_IOSTANDARD = "LVCMOS25", // with 1.8 actually applied voltage
...@@ -794,7 +805,7 @@ ...@@ -794,7 +805,7 @@
parameter HISPI_DQS_BIAS = "TRUE", parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
`ifdef BOSON `ifdef BOSON
parameter HISPI_IBUF_LOW_PWR = "FALSE", // "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE", // "FALSE", // "TRUE",
`else `else
parameter HISPI_IBUF_LOW_PWR = "TRUE", // "FALSE", // try parameter HISPI_IBUF_LOW_PWR = "TRUE", // "FALSE", // try
`endif `endif
......
...@@ -264,6 +264,7 @@ module mcntrl393 #( ...@@ -264,6 +264,7 @@ module mcntrl393 #(
parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode) parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode)
parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory) parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
parameter MCONTR_LINTILE_NO_PENDING = 16, // ignore new frame start if previous frame is not finished
parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk parameter MCNTRL_SCANLINE_DLY_WIDTH = 12, // delay start pulse by 1..64 mclk
parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024 // initial delay value for start pulse parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024 // initial delay value for start pulse
...@@ -1122,6 +1123,7 @@ module mcntrl393 #( ...@@ -1122,6 +1123,7 @@ module mcntrl393 #(
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED), .MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE), .MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE),
.MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE), .MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE),
.MCONTR_LINTILE_NO_PENDING (MCONTR_LINTILE_NO_PENDING),
.MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH), .MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH),
.MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT) .MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT)
) mcntrl_linear_wr_sensor_i ( ) mcntrl_linear_wr_sensor_i (
...@@ -1281,6 +1283,7 @@ module mcntrl393 #( ...@@ -1281,6 +1283,7 @@ module mcntrl393 #(
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED), .MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE), .MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE),
.MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE), .MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE),
.MCONTR_LINTILE_NO_PENDING (MCONTR_LINTILE_NO_PENDING),
.MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH), .MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH),
.MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT) .MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT)
...@@ -1357,6 +1360,7 @@ module mcntrl393 #( ...@@ -1357,6 +1360,7 @@ module mcntrl393 #(
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED), .MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE), .MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE),
.MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE), .MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE),
.MCONTR_LINTILE_NO_PENDING (MCONTR_LINTILE_NO_PENDING),
.MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH), .MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH),
.MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT) .MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT)
) mcntrl_linear_rw_chn3_i ( ) mcntrl_linear_rw_chn3_i (
......
...@@ -80,7 +80,8 @@ module mcntrl_linear_rw #( ...@@ -80,7 +80,8 @@ module mcntrl_linear_rw #(
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory) parameter MCONTR_LINTILE_ABORT_LATE = 14, // abort frame if not finished by the new frame sync (wait pending memory)
parameter MCONTR_LINTILE_NO_PENDING = 15, // ignore new frame start if previous frame is not finished
// TODO NC393: This delay may be too long for serail sensors. Make them always start to fill the // TODO NC393: This delay may be too long for serail sensors. Make them always start to fill the
// first buffer page, waiting for the request from mcntrl_linear during that first page. And if it will arrive - // first buffer page, waiting for the request from mcntrl_linear during that first page. And if it will arrive -
...@@ -182,6 +183,7 @@ module mcntrl_linear_rw #( ...@@ -182,6 +183,7 @@ module mcntrl_linear_rw #(
wire chn_rst; // resets command, including fifo; wire chn_rst; // resets command, including fifo;
reg chn_rst_d; // delayed by 1 cycle do detect turning off reg chn_rst_d; // delayed by 1 cycle do detect turning off
wire abort_en; // enable frame abort (mode register bit) wire abort_en; // enable frame abort (mode register bit)
wire no_pending; // ignore new frame start if previous frame is not finished
reg aborting_r; // waiting pending memory transactions at if the frame was not finished at frame sync reg aborting_r; // waiting pending memory transactions at if the frame was not finished at frame sync
// reg xfer_reset_page_r; // reg xfer_reset_page_r;
reg xfer_page_rst_r=1; reg xfer_page_rst_r=1;
...@@ -245,7 +247,7 @@ module mcntrl_linear_rw #( ...@@ -245,7 +247,7 @@ module mcntrl_linear_rw #(
wire msw_zero= !(|cmd_data[31:16]); // MSW all bits are 0 - set carry bit wire msw_zero= !(|cmd_data[31:16]); // MSW all bits are 0 - set carry bit
reg [14:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset} reg [16:0] mode_reg;//mode register: {no_pending,abort_en,copy_frame,skip_too_late,dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}
reg [NUM_RC_BURST_BITS-1:0] start_range_addr; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0 reg [NUM_RC_BURST_BITS-1:0] start_range_addr; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
reg [NUM_RC_BURST_BITS-1:0] frame_size; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0 reg [NUM_RC_BURST_BITS-1:0] frame_size; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
...@@ -302,7 +304,7 @@ module mcntrl_linear_rw #( ...@@ -302,7 +304,7 @@ module mcntrl_linear_rw #(
// Set parameter registers // Set parameter registers
always @(posedge mclk) begin always @(posedge mclk) begin
if (mrst) mode_reg <= 0; if (mrst) mode_reg <= 0;
else if (set_mode_w) mode_reg <= cmd_data[14:0]; // 4:0]; // [4:0]; else if (set_mode_w) mode_reg <= cmd_data[16:0]; // 4:0]; // [4:0];
if (mrst) single_frame_r <= 0; if (mrst) single_frame_r <= 0;
else single_frame_r <= single_frame_w; else single_frame_r <= single_frame_w;
...@@ -429,6 +431,7 @@ module mcntrl_linear_rw #( ...@@ -429,6 +431,7 @@ module mcntrl_linear_rw #(
assign disable_need = mode_reg[MCONTR_LINTILE_DIS_NEED]; assign disable_need = mode_reg[MCONTR_LINTILE_DIS_NEED];
assign skip_too_late = mode_reg[MCONTR_LINTILE_SKIP_LATE]; assign skip_too_late = mode_reg[MCONTR_LINTILE_SKIP_LATE];
assign abort_en = mode_reg[MCONTR_LINTILE_ABORT_LATE]; assign abort_en = mode_reg[MCONTR_LINTILE_ABORT_LATE];
assign no_pending = mode_reg[MCONTR_LINTILE_NO_PENDING];
`ifdef DEBUG_MCNTRL_LINEAR_EXTRA_STATUS `ifdef DEBUG_MCNTRL_LINEAR_EXTRA_STATUS
assign status_data= {last_row_w, last_in_row,line_unfinished[7:0], frame_finished_r, busy_r}; assign status_data= {last_row_w, last_in_row,line_unfinished[7:0], frame_finished_r, busy_r};
...@@ -490,10 +493,10 @@ module mcntrl_linear_rw #( ...@@ -490,10 +493,10 @@ module mcntrl_linear_rw #(
// if (mrst || frame_start_delayed) frame_start_pending <= 0; // if (mrst || frame_start_delayed) frame_start_pending <= 0;
if (mrst) frame_start_pending <= 0; if (mrst) frame_start_pending <= 0;
// else frame_start_pending <= {frame_start_pending[0], busy_r && (frame_start_pending[0] | frame_start_late)}; // else frame_start_pending <= {frame_start_pending[0], busy_r && (frame_start_pending[0] | frame_start_late)};
else frame_start_pending <= busy_r && (frame_start_pending | frame_start_late); else frame_start_pending <= !no_pending && busy_r && (frame_start_pending | frame_start_late);
if (mrst) frame_start_pending_long <= 0; if (mrst) frame_start_pending_long <= 0;
else frame_start_pending_long <= {frame_start_pending_long[0], (busy_r || skip_run) && (frame_start_pending_long[0] | frame_start_late)}; else frame_start_pending_long <= {frame_start_pending_long[0], ~no_pending & (busy_r | skip_run) && (frame_start_pending_long[0] | frame_start_late)};
if (mrst) frame_start_r <= 0; if (mrst) frame_start_r <= 0;
// else frame_start_r <= {frame_start_r[3:0], frame_start_late & frame_en}; // else frame_start_r <= {frame_start_r[3:0], frame_start_late & frame_en};
......
#!/bin/bash
# Updates vrlg.py to include predefines for pydev. Needed when new parameters are added to the Verilog header files
./test_mcntrl.py @cargs_test <<< $'pydev_predefines\nexit\n'
...@@ -1432,6 +1432,9 @@ MCONTR_LINTILE_KEEP_OPEN__TYPE = str ...@@ -1432,6 +1432,9 @@ MCONTR_LINTILE_KEEP_OPEN__TYPE = str
MCONTR_LINTILE_LINEAR = int MCONTR_LINTILE_LINEAR = int
MCONTR_LINTILE_LINEAR__RAW = str MCONTR_LINTILE_LINEAR__RAW = str
MCONTR_LINTILE_LINEAR__TYPE = str MCONTR_LINTILE_LINEAR__TYPE = str
MCONTR_LINTILE_NO_PENDING = int
MCONTR_LINTILE_NO_PENDING__RAW = str
MCONTR_LINTILE_NO_PENDING__TYPE = str
MCONTR_LINTILE_NRESET = int MCONTR_LINTILE_NRESET = int
MCONTR_LINTILE_NRESET__RAW = str MCONTR_LINTILE_NRESET__RAW = str
MCONTR_LINTILE_NRESET__TYPE = str MCONTR_LINTILE_NRESET__TYPE = str
...@@ -2149,6 +2152,12 @@ SENSOR_TIMING_STATUS_REG_INC__TYPE = str ...@@ -2149,6 +2152,12 @@ SENSOR_TIMING_STATUS_REG_INC__TYPE = str
SENSOR_TIMING_TO = int SENSOR_TIMING_TO = int
SENSOR_TIMING_TO__RAW = str SENSOR_TIMING_TO__RAW = str
SENSOR_TIMING_TO__TYPE = str SENSOR_TIMING_TO__TYPE = str
SENS_ALT_STATUS = int
SENS_ALT_STATUS_SET = int
SENS_ALT_STATUS_SET__RAW = str
SENS_ALT_STATUS_SET__TYPE = str
SENS_ALT_STATUS__RAW = str
SENS_ALT_STATUS__TYPE = str
SENS_BANDWIDTH = str SENS_BANDWIDTH = str
SENS_BANDWIDTH__RAW = str SENS_BANDWIDTH__RAW = str
SENS_BANDWIDTH__TYPE = str SENS_BANDWIDTH__TYPE = str
...@@ -2380,6 +2389,27 @@ SENS_SYNC_MULT__TYPE = str ...@@ -2380,6 +2389,27 @@ SENS_SYNC_MULT__TYPE = str
SENS_SYNC_RADDR = int SENS_SYNC_RADDR = int
SENS_SYNC_RADDR__RAW = str SENS_SYNC_RADDR__RAW = str
SENS_SYNC_RADDR__TYPE = str SENS_SYNC_RADDR__TYPE = str
SENS_TEST_BITS = int
SENS_TEST_BITS__RAW = str
SENS_TEST_BITS__TYPE = str
SENS_TEST_HEIGHT_BITS = int
SENS_TEST_HEIGHT_BITS__RAW = str
SENS_TEST_HEIGHT_BITS__TYPE = str
SENS_TEST_HEIGHT_INC = int
SENS_TEST_HEIGHT_INC__RAW = str
SENS_TEST_HEIGHT_INC__TYPE = str
SENS_TEST_MODES = int
SENS_TEST_MODES__RAW = str
SENS_TEST_MODES__TYPE = str
SENS_TEST_SET = int
SENS_TEST_SET__RAW = str
SENS_TEST_SET__TYPE = str
SENS_TEST_WIDTH_BITS = int
SENS_TEST_WIDTH_BITS__RAW = str
SENS_TEST_WIDTH_BITS__TYPE = str
SENS_TEST_WIDTH_INC = int
SENS_TEST_WIDTH_INC__RAW = str
SENS_TEST_WIDTH_INC__TYPE = str
SENS_UART_EXTIF_EN = int SENS_UART_EXTIF_EN = int
SENS_UART_EXTIF_EN__RAW = str SENS_UART_EXTIF_EN__RAW = str
SENS_UART_EXTIF_EN__TYPE = str SENS_UART_EXTIF_EN__TYPE = str
...@@ -2533,6 +2563,9 @@ UART_RX_DEBOUNCE__TYPE = str ...@@ -2533,6 +2563,9 @@ UART_RX_DEBOUNCE__TYPE = str
UART_START_FRAME_BYTE = int UART_START_FRAME_BYTE = int
UART_START_FRAME_BYTE__RAW = str UART_START_FRAME_BYTE__RAW = str
UART_START_FRAME_BYTE__TYPE = str UART_START_FRAME_BYTE__TYPE = str
UART_STOP_BITS = int
UART_STOP_BITS__RAW = str
UART_STOP_BITS__TYPE = str
VERBOSE = int VERBOSE = int
VERBOSE__RAW = str VERBOSE__RAW = str
VERBOSE__TYPE = str VERBOSE__TYPE = str
......
...@@ -437,7 +437,7 @@ class X393Cmprs(object): ...@@ -437,7 +437,7 @@ class X393Cmprs(object):
write_mem = False, write_mem = False,
enable = en, enable = en,
chn_reset = rst, chn_reset = rst,
copy_frame = copy_frame, copy_frame = copy_frame,
abort_late = abort_late) abort_late = abort_late)
self.x393_axi_tasks.write_control_register(base_addr + vrlg.MCNTRL_TILED_MODE, mode) self.x393_axi_tasks.write_control_register(base_addr + vrlg.MCNTRL_TILED_MODE, mode)
......
...@@ -1706,6 +1706,7 @@ class X393ExportC(object): ...@@ -1706,6 +1706,7 @@ class X393ExportC(object):
dw.append(("skip_too_late",vrlg.MCONTR_LINTILE_SKIP_LATE,1,0, "Skip over missed blocks to preserve frame structure (increment pointers)")) dw.append(("skip_too_late",vrlg.MCONTR_LINTILE_SKIP_LATE,1,0, "Skip over missed blocks to preserve frame structure (increment pointers)"))
dw.append(("copy_frame", vrlg.MCONTR_LINTILE_COPY_FRAME,1,0, "Copy frame number from the master (sensor) channel. Combine with reset_frame to reset bjuffer")) dw.append(("copy_frame", vrlg.MCONTR_LINTILE_COPY_FRAME,1,0, "Copy frame number from the master (sensor) channel. Combine with reset_frame to reset bjuffer"))
dw.append(("abort_late", vrlg.MCONTR_LINTILE_ABORT_LATE,1,0, "abort frame if not finished by the new frame sync (wait pending memory transfers)")) dw.append(("abort_late", vrlg.MCONTR_LINTILE_ABORT_LATE,1,0, "abort frame if not finished by the new frame sync (wait pending memory transfers)"))
dw.append(("no_pending", vrlg.MCONTR_LINTILE_NO_PENDING,1,0, "Do not process frame_start until the previous one is finished"))
return dw return dw
""" """
self.x393_axi_tasks.write_control_register( self.x393_axi_tasks.write_control_register(
...@@ -2328,6 +2329,10 @@ class X393ExportC(object): ...@@ -2328,6 +2329,10 @@ class X393ExportC(object):
dw.append(("uart_recv_rst_set", vrlg.SENS_UART_RECV_RST+1, 1, 0, "set 'uart_recv_rst' field")) dw.append(("uart_recv_rst_set", vrlg.SENS_UART_RECV_RST+1, 1, 0, "set 'uart_recv_rst' field"))
dw.append(("uart_xmit_start", vrlg.SENS_UART_XMIT_START, 1, 0, "UART: start transmiting prepared packet")) dw.append(("uart_xmit_start", vrlg.SENS_UART_XMIT_START, 1, 0, "UART: start transmiting prepared packet"))
dw.append(("uart_recv_next", vrlg.SENS_UART_RECV_NEXT, 1, 0, "UART: advance receive FIFO to next byte")) dw.append(("uart_recv_next", vrlg.SENS_UART_RECV_NEXT, 1, 0, "UART: advance receive FIFO to next byte"))
dw.append(("alt_status", vrlg.SENS_ALT_STATUS, 1, 0, "Change meaning of the certain status fields"))
dw.append(("alt_status_set", vrlg.SENS_ALT_STATUS_SET, 1, 0, "set 'alt_status' field"))
dw.append(("test_modes", vrlg.SENS_TEST_MODES,vrlg.SENS_TEST_BITS,0, "Test patterns instead of the image. 0: normal, 1: LSB - col/3, MSB - row/3, 2:column, 3:row"))
dw.append(("test_modes_set", vrlg.SENS_TEST_SET, 1, 0, "set 'test_modes' field"))
return dw return dw
......
...@@ -53,7 +53,8 @@ def func_encode_mode_scan_tiled (skip_too_late = False, ...@@ -53,7 +53,8 @@ def func_encode_mode_scan_tiled (skip_too_late = False,
enable = True, enable = True,
chn_reset = False, chn_reset = False,
copy_frame = False, copy_frame = False,
abort_late = False): abort_late = False,
no_pending = False):
""" """
Combines arguments to create a 12-bit encoded data for scanline mode memory R/W Combines arguments to create a 12-bit encoded data for scanline mode memory R/W
@param skip_too_late - Skip over missed blocks to preserve frame structure (increment pointers), @param skip_too_late - Skip over missed blocks to preserve frame structure (increment pointers),
...@@ -71,6 +72,7 @@ def func_encode_mode_scan_tiled (skip_too_late = False, ...@@ -71,6 +72,7 @@ def func_encode_mode_scan_tiled (skip_too_late = False,
@param chn_reset immediately reset all the internal circuitry @param chn_reset immediately reset all the internal circuitry
@param copy_frame copy frame number from the master channel (non-persistent) @param copy_frame copy frame number from the master channel (non-persistent)
@param abort_late abort frame r/w at the next frame sync, if not finished. Wait for pending memory transfers @param abort_late abort frame r/w at the next frame sync, if not finished. Wait for pending memory transfers
@param no_pending ignore new frame start if previous frame is not finished
""" """
rslt = 0; rslt = 0;
rslt |= (1,0)[chn_reset] << vrlg.MCONTR_LINTILE_NRESET # inverted rslt |= (1,0)[chn_reset] << vrlg.MCONTR_LINTILE_NRESET # inverted
...@@ -86,7 +88,8 @@ def func_encode_mode_scan_tiled (skip_too_late = False, ...@@ -86,7 +88,8 @@ def func_encode_mode_scan_tiled (skip_too_late = False,
rslt |= (0,1)[disable_need] << vrlg.MCONTR_LINTILE_DIS_NEED rslt |= (0,1)[disable_need] << vrlg.MCONTR_LINTILE_DIS_NEED
rslt |= (0,1)[skip_too_late] << vrlg.MCONTR_LINTILE_SKIP_LATE rslt |= (0,1)[skip_too_late] << vrlg.MCONTR_LINTILE_SKIP_LATE
rslt |= (0,1)[copy_frame] << vrlg.MCONTR_LINTILE_COPY_FRAME rslt |= (0,1)[copy_frame] << vrlg.MCONTR_LINTILE_COPY_FRAME
rslt |= (0,1)[copy_frame] << vrlg.MCONTR_LINTILE_ABORT_LATE rslt |= (0,1)[abort_late] << vrlg.MCONTR_LINTILE_ABORT_LATE
rslt |= (0,1)[no_pending] << vrlg.MCONTR_LINTILE_NO_PENDING
return rslt return rslt
''' '''
......
...@@ -479,6 +479,7 @@ class X393SensCmprs(object): ...@@ -479,6 +479,7 @@ class X393SensCmprs(object):
histogram_width_m1 = None, # 2559, #0, histogram_width_m1 = None, # 2559, #0,
histogram_height_m1 = None, # 1935, #0, histogram_height_m1 = None, # 1935, #0,
bits16 = False, bits16 = False,
no_pending = False,
verbose = 1 verbose = 1
): ):
""" """
...@@ -521,8 +522,7 @@ class X393SensCmprs(object): ...@@ -521,8 +522,7 @@ class X393SensCmprs(object):
@param histogram_top - histogram window top margin @param histogram_top - histogram window top margin
@param histogram_width_m1 - one less than window width. If 0 - use frame right margin (end of HACT) @param histogram_width_m1 - one less than window width. If 0 - use frame right margin (end of HACT)
@param histogram_height_m1 - one less than window height. If 0 - use frame bottom margin (end of VACT) @param histogram_height_m1 - one less than window height. If 0 - use frame bottom margin (end of VACT)
@param no_pending ignore new frame start if previous frame is not finished
???
@param verbose - verbose level @param verbose - verbose level
@return True if all done, False if exited prematurely through exit_step @return True if all done, False if exited prematurely through exit_step
""" """
...@@ -633,6 +633,7 @@ class X393SensCmprs(object): ...@@ -633,6 +633,7 @@ class X393SensCmprs(object):
print ("num_macro_rows_m1 = ", num_macro_rows_m1) print ("num_macro_rows_m1 = ", num_macro_rows_m1)
print ("cmode = ", cmode) print ("cmode = ", cmode)
print ("bits16 = ", bits16) print ("bits16 = ", bits16)
print ("no_pending = ", no_pending)
print ("verbose = ", verbose) print ("verbose = ", verbose)
if exit_step == 10: return False if exit_step == 10: return False
...@@ -680,7 +681,8 @@ class X393SensCmprs(object): ...@@ -680,7 +681,8 @@ class X393SensCmprs(object):
# window_height = window_height, # input [31:0] window_height; # 16 bit # window_height = window_height, # input [31:0] window_height; # 16 bit
window_height = window_height_memory, # input [31:0] window_height; # 16 bit window_height = window_height_memory, # input [31:0] window_height; # 16 bit
window_left = window_left >> 4, # input [31:0] window_left; window_left = window_left >> 4, # input [31:0] window_left;
window_top = window_top); # input [31:0] window_top; window_top = window_top, # input [31:0] window_top;
no_pending = no_pending)
# Enable arbitration of sensor-to-memory controller # Enable arbitration of sensor-to-memory controller
if exit_step == 12: return False if exit_step == 12: return False
...@@ -813,6 +815,14 @@ class X393SensCmprs(object): ...@@ -813,6 +815,14 @@ class X393SensCmprs(object):
uart_xmit_start = False, uart_xmit_start = False,
uart_recv_next = False) uart_recv_next = False)
self.x393Sensor.set_sensor_uart_ctl_boson ( # trying to read initial message - no, something different
num_sensor = num_sensor,
uart_extif_en = False,
uart_xmit_rst = False,
uart_recv_rst = False,
uart_xmit_start = False,
uart_recv_next = False)
self.x393Sensor.set_sensor_io_ctl_boson ( self.x393Sensor.set_sensor_io_ctl_boson (
num_sensor = num_sensor, num_sensor = num_sensor,
mrst = False, mrst = False,
...@@ -830,6 +840,18 @@ class X393SensCmprs(object): ...@@ -830,6 +840,18 @@ class X393SensCmprs(object):
sensor_status = self.x393Sensor.get_new_status(num_sensor=num_sensor) sensor_status = self.x393Sensor.get_new_status(num_sensor=num_sensor)
locked_pxd_mmcm = ((sensor_status >> 12) & 1) != 0 locked_pxd_mmcm = ((sensor_status >> 12) & 1) != 0
print ("PCLK MMCM locked") print ("PCLK MMCM locked")
"""
fn = self.get_frame_number_i2c(channel=num_sensor)
print ("Frame number = %d"%(fn))
for _ in range (2):
self.skip_frame_i2c(
channel_mask = (1 << num_sensor),
loop_delay = 0.01,
timeout = 5.0) # 2.0)
fn = self.get_frame_number_i2c(channel=num_sensor)
print ("Frame number (after skip to make sure Boson is in booted state before UART commands) = %d"%(fn))
"""
'''
self.x393Sensor.set_sensor_uart_ctl_boson ( self.x393Sensor.set_sensor_uart_ctl_boson (
num_sensor = num_sensor, num_sensor = num_sensor,
uart_extif_en = True, uart_extif_en = True,
...@@ -837,6 +859,7 @@ class X393SensCmprs(object): ...@@ -837,6 +859,7 @@ class X393SensCmprs(object):
uart_recv_rst = False, uart_recv_rst = False,
uart_xmit_start = False, uart_xmit_start = False,
uart_recv_next = False) uart_recv_next = False)
'''
if exit_step == 17: return False if exit_step == 17: return False
...@@ -911,6 +934,17 @@ class X393SensCmprs(object): ...@@ -911,6 +934,17 @@ class X393SensCmprs(object):
chn_en = True, chn_en = True,
bits16 = bits16) #False) bits16 = bits16) #False)
if sensorType == x393_sensor.SENSOR_INTERFACE_BOSON:
fn = self.get_frame_number_i2c(channel=num_sensor)
print ("Frame number = %d"%(fn))
for _ in range (70): # 65): #70): #80): #100): # 60 10 2
self.skip_frame_i2c(
channel_mask = (1 << num_sensor),
loop_delay = 0.01,
timeout = 5.0) # 2.0)
fn = self.get_frame_number_i2c(channel=num_sensor)
print ("Frame number (after skip to make sure Boson is in booted state before UART commands) = %d"%(fn))
if verbose >0 : if verbose >0 :
print ("===================== CMPRS_EN_ARBIT =========================") print ("===================== CMPRS_EN_ARBIT =========================")
# just temporarily - enable channel immediately # just temporarily - enable channel immediately
...@@ -927,6 +961,8 @@ class X393SensCmprs(object): ...@@ -927,6 +961,8 @@ class X393SensCmprs(object):
en_input = True, en_input = True,
repet_mode = True, # Normal mode, single trigger - just for debugging TODO: re-assign? repet_mode = True, # Normal mode, single trigger - just for debugging TODO: re-assign?
trig = False) trig = False)
return True return True
def specify_window (self, def specify_window (self,
...@@ -1489,6 +1525,7 @@ class X393SensCmprs(object): ...@@ -1489,6 +1525,7 @@ class X393SensCmprs(object):
circbuf_chn_size= 0x4000000, # 64 Mib - all 4 channels? circbuf_chn_size= 0x4000000, # 64 Mib - all 4 channels?
reset_afi = False, # reset AFI multiplexer reset_afi = False, # reset AFI multiplexer
bits16 = False, bits16 = False,
no_pending = False,
verbose = 1): verbose = 1):
""" """
Setup one sensor+compressor channel (for one sub-channel only) Setup one sensor+compressor channel (for one sub-channel only)
...@@ -1545,7 +1582,8 @@ class X393SensCmprs(object): ...@@ -1545,7 +1582,8 @@ class X393SensCmprs(object):
buffer_pages_circbuf_chn0..3, buffer_pages_raw_chn0..3, page size is 4096 buffer_pages_circbuf_chn0..3, buffer_pages_raw_chn0..3, page size is 4096
@param circbuf_chn_size - circular buffer size for each channel, in bytes @param circbuf_chn_size - circular buffer size for each channel, in bytes
@param no_pending ignore new frame start if previous frame is not finished
@param verbose - verbose level @param verbose - verbose level
@return True if all done, False if exited prematurely by exit_step @return True if all done, False if exited prematurely by exit_step
""" """
...@@ -1751,6 +1789,7 @@ class X393SensCmprs(object): ...@@ -1751,6 +1789,7 @@ class X393SensCmprs(object):
histogram_width_m1 = histogram_width_m1, histogram_width_m1 = histogram_width_m1,
histogram_height_m1 = histogram_height_m1, histogram_height_m1 = histogram_height_m1,
bits16 = bits16, bits16 = bits16,
no_pending = no_pending,
verbose = verbose) verbose = verbose)
if not rslt : return False if not rslt : return False
if exit_step == 20: return False if exit_step == 20: return False
......
...@@ -595,15 +595,15 @@ class X393Sensor(object): ...@@ -595,15 +595,15 @@ class X393Sensor(object):
return rslt return rslt
def func_sensor_io_ctl_boson (self, def func_sensor_io_ctl_boson (self,
mrst = None, mrst = None,
mmcm_rst = None, mmcm_rst = None,
set_delays = False, set_delays = False,
gpio0 = None, gpio0 = None,
gpio1 = None, gpio1 = None,
gpio2 = None, gpio2 = None,
gpio3 = None, gpio3 = None,
test_patt = None, alt_status = None,
test_mode = None): test_pattern = None):
""" """
Combine sensor I/O control parameters into a control word Combine sensor I/O control parameters into a control word
@param mrst - True - activate MRST signal (low), False - deactivate MRST (high), None - no change @param mrst - True - activate MRST signal (low), False - deactivate MRST (high), None - no change
...@@ -613,16 +613,10 @@ class X393Sensor(object): ...@@ -613,16 +613,10 @@ class X393Sensor(object):
@param gpio1 - GPIO[1]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high @param gpio1 - GPIO[1]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio2 - GPIO[2]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high @param gpio2 - GPIO[2]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio3 - GPIO[3]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high @param gpio3 - GPIO[3]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param test_patt - True: set status output to test pattern (should be 0x17), False: set to MMCM phase @param alt_status - True: set status output to test pattern (should be 0x17), False: set to MMCM phase
@param test_mode - 0..7 - 0 normal data, 1+ - test petterns (1 - diagnal by 3, 2 - horizontal gradient , 3 - vertical gradient @param test_pattern - 0..7 - 0 normal data, 1+ - test petterns (1 - diagnal by 3, 2 - horizontal gradient , 3 - vertical gradient
@return sensor i/o control word @return sensor i/o control word
""" """
RESET_TEST_OUT = 24
SET_TEST_OUT = 25
SENS_TEST_MODES = 26
SENS_TEST_BITS = 3
SENS_TEST_SET= 29
rslt = 0 rslt = 0
if not mrst is None: if not mrst is None:
rslt |= (3,2)[mrst] << vrlg.SENS_CTRL_MRST rslt |= (3,2)[mrst] << vrlg.SENS_CTRL_MRST
...@@ -638,12 +632,13 @@ class X393Sensor(object): ...@@ -638,12 +632,13 @@ class X393Sensor(object):
rslt |= (4 | (gpio2 & 3)) << vrlg.SENS_CTRL_GP2 rslt |= (4 | (gpio2 & 3)) << vrlg.SENS_CTRL_GP2
if not gpio3 is None: if not gpio3 is None:
rslt |= (4 | (gpio3 & 3)) << vrlg.SENS_CTRL_GP3 rslt |= (4 | (gpio3 & 3)) << vrlg.SENS_CTRL_GP3
if not test_patt is None: if not alt_status is None:
rslt |= 1 << (RESET_TEST_OUT, SET_TEST_OUT)[test_patt] rslt |= (2,3)[alt_status] << vrlg.SENS_ALT_STATUS
if not test_mode is None:
test_mode_masked = test_mode & ((1 << SENS_TEST_BITS) - 1) if not test_pattern is None:
rslt |= test_mode_masked << SENS_TEST_MODES test_mode_masked = test_pattern & ((1 << vrlg.SENS_TEST_BITS) - 1)
rslt |= 1 << SENS_TEST_SET rslt |= test_mode_masked << vrlg.SENS_TEST_MODES
rslt |= 1 << vrlg.SENS_TEST_SET
return rslt return rslt
def func_sensor_uart_ctl_boson (self, def func_sensor_uart_ctl_boson (self,
...@@ -1323,15 +1318,15 @@ class X393Sensor(object): ...@@ -1323,15 +1318,15 @@ class X393Sensor(object):
def set_sensor_io_ctl_boson (self, def set_sensor_io_ctl_boson (self,
num_sensor, num_sensor,
mrst = None, mrst = None,
mmcm_rst = None, mmcm_rst = None,
set_delays = False, set_delays = False,
gpio0 = None, gpio0 = None,
gpio1 = None, gpio1 = None,
gpio2 = None, gpio2 = None,
gpio3 = None, gpio3 = None,
test_patt = None, alt_status = None,
test_mode = None): test_pattern = None):
""" """
Set sensor I/O controls, including I/O signals Set sensor I/O controls, including I/O signals
@param num_sensor - sensor port number (0..3) @param num_sensor - sensor port number (0..3)
...@@ -1342,8 +1337,8 @@ class X393Sensor(object): ...@@ -1342,8 +1337,8 @@ class X393Sensor(object):
@param gpio1 - GPIO[1]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high @param gpio1 - GPIO[1]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio2 - GPIO[2]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high @param gpio2 - GPIO[2]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param gpio3 - GPIO[3]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high @param gpio3 - GPIO[3]: 0 - float(input), 1 - out low, 2 out high, 3 - pulse high
@param test_patt - True: set status output to test pattern (should be 0x17), False: set to MMCM phase @param alt_status - True: set status output to test pattern (should be 0x17), False: set to MMCM phase
@param test_mode - 0..7 - 0 normal data, 1+ - test petterns (1 - diagnal by 3, 2 - horizontal gradient , 3 - vertical gradient @param test_pattern - 0..7 - 0 normal data, 1+ - test patterns (1 - LSB col//3. MSB row//3, 2 - horizontal gradient , 3 - vertical gradient
""" """
try: try:
...@@ -1357,8 +1352,8 @@ class X393Sensor(object): ...@@ -1357,8 +1352,8 @@ class X393Sensor(object):
gpio1 = gpio1, gpio1 = gpio1,
gpio2 = gpio2, gpio2 = gpio2,
gpio3 = gpio3, gpio3 = gpio3,
test_patt = test_patt, alt_status = alt_status,
test_mode = test_mode) test_pattern = test_pattern)
return return
except: except:
pass pass
...@@ -1372,8 +1367,8 @@ class X393Sensor(object): ...@@ -1372,8 +1367,8 @@ class X393Sensor(object):
gpio1 = gpio1, gpio1 = gpio1,
gpio2 = gpio2, gpio2 = gpio2,
gpio3 = gpio3, gpio3 = gpio3,
test_patt = test_patt, alt_status = alt_status,
test_mode = test_mode) test_pattern = test_pattern)
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_CTRL; reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_CTRL;
self.x393_axi_tasks.write_control_register(reg_addr, data) self.x393_axi_tasks.write_control_register(reg_addr, data)
...@@ -1602,13 +1597,50 @@ class X393Sensor(object): ...@@ -1602,13 +1597,50 @@ class X393Sensor(object):
# seq_num = seq_num) # input [5:0] seq_num; # seq_num = seq_num) # input [5:0] seq_num;
# return seq_num # return seq_num
def uart_wait_responsive(self,
num_sensor,
retries = 100):
"""
Request temperature until responds (needed after startup)
@param num_sensor - sensor port number (0..3)
@param retries - retries to read temperature before giving up
@return elapsed time
"""
wait_to_read = 0.01 # sec
time_start=time.time()
for _ in range(retries):
_=self.uart_send_packet(
num_sensor,
0x00050030, # bosonlookupFPATempDegCx10
bytearray([]),
True, # wait_ready
True, # reset_recv,
True, # reset_xmit)
0)
time.sleep(wait_to_read)
rec_pack=self.uart_receive_packet(
num_sensor,
wait_packet = False,
enable_sequencer = False)
if rec_pack:
break
et= time.time() - time_start
print ("Elapsed time: %f"%(et))
return et
"""
uart_send_packet 0 0x00050030 bytearray(b'') # bosonlookupFPATempDegCx10
uart_print_packet 0 False False
"""
def uart_send_packet(self, def uart_send_packet(self,
num_sensor, num_sensor,
command, command,
data, #bytearray data, #bytearray
wait_ready=True, wait_ready=True,
reset_recv=True, reset_recv=True,
reset_xmit=True): reset_xmit=True,
verbose = 1):
""" """
Send packet to UART Send packet to UART
@param num_sensor - sensor port number (0..3) @param num_sensor - sensor port number (0..3)
...@@ -1617,6 +1649,7 @@ class X393Sensor(object): ...@@ -1617,6 +1649,7 @@ class X393Sensor(object):
@param wait_ready Wait until all data is sent to UART @param wait_ready Wait until all data is sent to UART
@param reset_recv Reset UART receive channel simultaneously with transmit one @param reset_recv Reset UART receive channel simultaneously with transmit one
@param reset_xmit Reset UART transmit channel before sending bytes @param reset_xmit Reset UART transmit channel before sending bytes
@param verbose verbose level
Note: sequencer commands are disabled (may be (re)-enabled after reading response Note: sequencer commands are disabled (may be (re)-enabled after reading response
""" """
...@@ -1644,7 +1677,8 @@ class X393Sensor(object): ...@@ -1644,7 +1677,8 @@ class X393Sensor(object):
num_sensor = num_sensor, num_sensor = num_sensor,
uart_xmit_rst = False, uart_xmit_rst = False,
uart_recv_rst = False) uart_recv_rst = False)
print(packet) if verbose > 0:
print(packet)
for b in packet: for b in packet:
self.set_sensor_uart_fifo_byte_boson ( self.set_sensor_uart_fifo_byte_boson (
num_sensor=num_sensor, num_sensor=num_sensor,
...@@ -2590,7 +2624,8 @@ input mem mtd4 ram1 ...@@ -2590,7 +2624,8 @@ input mem mtd4 ram1
num_sensor, num_sensor,
command, command,
reset_frame = False, reset_frame = False,
abort_late = False, abort_late = False,
no_pending = False,
verbose = 1): verbose = 1):
""" """
Control memory access (write) of a sensor channel Control memory access (write) of a sensor channel
...@@ -2601,9 +2636,9 @@ input mem mtd4 ram1 ...@@ -2601,9 +2636,9 @@ input mem mtd4 ram1
single - acquire single frame , single - acquire single frame ,
repetitive - repetitive mode repetitive - repetitive mode
@param reset_frame - reset frame number. Needed after changing frame start address (i.e. initial set-up) ! @param reset_frame - reset frame number. Needed after changing frame start address (i.e. initial set-up) !
@param abort_late abort frame r/w at the next frame sync, if not finished. Wait for pending memory transfers @param abort_late - abort frame r/w at the next frame sync, if not finished. Wait for pending memory transfers
@param no_pending - ignore new frame start if previous frame is not finished
@param vebose - verbose level @param vebose - - verbose level
""" """
try: try:
if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function if (num_sensor == all) or (num_sensor[0].upper() == "A"): #all is a built-in function
...@@ -2613,6 +2648,7 @@ input mem mtd4 ram1 ...@@ -2613,6 +2648,7 @@ input mem mtd4 ram1
command = command, command = command,
reset_frame = reset_frame, reset_frame = reset_frame,
abort_late = abort_late, abort_late = abort_late,
no_pending = no_pending,
verbose = verbose) verbose = verbose)
return return
except: except:
...@@ -2648,7 +2684,8 @@ input mem mtd4 ram1 ...@@ -2648,7 +2684,8 @@ input mem mtd4 ram1
write_mem = True, write_mem = True,
enable = en, enable = en,
chn_reset = rst, chn_reset = rst,
abort_late = abort_late) abort_late = abort_late,
no_pending = no_pending)
self.x393_axi_tasks.write_control_register(base_addr + vrlg.MCNTRL_SCANLINE_MODE, mode) self.x393_axi_tasks.write_control_register(base_addr + vrlg.MCNTRL_SCANLINE_MODE, mode)
if verbose > 0 : if verbose > 0 :
print ("write_control_register(0x%08x, 0x%08x)"%(base_addr + vrlg.MCNTRL_SCANLINE_MODE, mode)) print ("write_control_register(0x%08x, 0x%08x)"%(base_addr + vrlg.MCNTRL_SCANLINE_MODE, mode))
...@@ -2662,7 +2699,8 @@ input mem mtd4 ram1 ...@@ -2662,7 +2699,8 @@ input mem mtd4 ram1
window_width, window_width,
window_height, window_height,
window_left, window_left,
window_top): window_top,
no_pending = False):
""" """
Setup memory controller for a sensor channel Setup memory controller for a sensor channel
@param num_sensor - sensor port number (0..3) @param num_sensor - sensor port number (0..3)
...@@ -2674,7 +2712,23 @@ input mem mtd4 ram1 ...@@ -2674,7 +2712,23 @@ input mem mtd4 ram1
@param window_height - 16-bit window height (in scan lines) @param window_height - 16-bit window height (in scan lines)
@param window_left - 13-bit window left margin in 8-bursts (16 bytes) @param window_left - 13-bit window left margin in 8-bursts (16 bytes)
@param window_top - 16-bit window top margin (in scan lines @param window_top - 16-bit window top margin (in scan lines
""" @param no_pending ignore new frame start if previous frame is not finished
"""
verbose = 1
if verbose >0 :
print ("----------- setup_sensor_channel -------------")
print ("num_sensor = ", num_sensor)
print ("frame_sa = ", frame_sa)
print ("frame_sa_inc = ", frame_sa_inc)
print ("last_frame_num = ", last_frame_num)
print ("frame_full_width = ", frame_full_width)
print ("window_width = ", window_width)
print ("window_height = ", window_height)
print ("window_left = ", window_left)
print ("window_top = ", window_top)
print ("no_pending = ", no_pending)
base_addr = vrlg.MCONTR_SENS_BASE + vrlg.MCONTR_SENS_INC * num_sensor; base_addr = vrlg.MCONTR_SENS_BASE + vrlg.MCONTR_SENS_INC * num_sensor;
mode= x393_mcntrl.func_encode_mode_scan_tiled( mode= x393_mcntrl.func_encode_mode_scan_tiled(
skip_too_late = True, skip_too_late = True,
...@@ -2686,7 +2740,8 @@ input mem mtd4 ram1 ...@@ -2686,7 +2740,8 @@ input mem mtd4 ram1
write_mem = True, write_mem = True,
enable = True, enable = True,
chn_reset = False, chn_reset = False,
abort_late = False) # default, change with control_sensor_memory() abort_late = False,
no_pending = no_pending) # default, change with control_sensor_memory()
self.x393_axi_tasks.write_control_register(base_addr + vrlg.MCNTRL_SCANLINE_STARTADDR, self.x393_axi_tasks.write_control_register(base_addr + vrlg.MCNTRL_SCANLINE_STARTADDR,
frame_sa); # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0) frame_sa); # RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
......
...@@ -76,6 +76,16 @@ module sens_103993 #( ...@@ -76,6 +76,16 @@ module sens_103993 #(
parameter SENS_UART_XMIT_START = 6, // 6 parameter SENS_UART_XMIT_START = 6, // 6
parameter SENS_UART_RECV_NEXT = 7, // 7 parameter SENS_UART_RECV_NEXT = 7, // 7
parameter SENS_ALT_STATUS = 24,
parameter SENS_ALT_STATUS_SET = 25,
parameter SENS_TEST_MODES = 26,
parameter SENS_TEST_BITS = 3,
parameter SENS_TEST_SET= 29,
parameter SENS_TEST_WIDTH_BITS = 10,
parameter SENS_TEST_HEIGHT_BITS = 10,
parameter SENS_TEST_WIDTH_INC = 3,
parameter SENS_TEST_HEIGHT_INC = 3,
// parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20 // parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
// parameter SENS_CTRL_QUADRANTS_WIDTH = 6, // parameter SENS_CTRL_QUADRANTS_WIDTH = 6,
// parameter SENS_CTRL_QUADRANTS_EN = 20, // 17:12, enable - 20 (2 bits reserved) // parameter SENS_CTRL_QUADRANTS_EN = 20, // 17:12, enable - 20 (2 bits reserved)
...@@ -185,43 +195,43 @@ module sens_103993 #( ...@@ -185,43 +195,43 @@ module sens_103993 #(
output extif_ready, // acknowledges extif_dav output extif_ready, // acknowledges extif_dav
input extif_rst input extif_rst
); );
/*
localparam RESET_TEST_OUT = 24; localparam SENS_ALT_STATUS = 24;
localparam SET_TEST_OUT = 25; localparam SENS_ALT_STATUS_SET = 25;
localparam SENS_TEST_MODES = 26; localparam SENS_TEST_MODES = 26;
localparam SENS_TEST_BITS = 3; localparam SENS_TEST_BITS = 3;
localparam SENS_TEST_SET= 29; localparam SENS_TEST_SET= 29;
localparam SENS_WIDTH_BITS = 10; localparam SENS_TEST_WIDTH_BITS = 10;
localparam SENS_HEIGHT_BITS = 10; localparam SENS_TEST_HEIGHT_BITS = 10;
localparam SENS_WIDTH_INC = 3; localparam SENS_TEST_WIDTH_INC = 3;
localparam SENS_HEIGHT_INC = 3; localparam SENS_TEST_HEIGHT_INC = 3;
*/
wire dvalid_w; wire dvalid_w;
wire [15:0] pxd_w; wire [15:0] pxd_w;
wire [15:0] pxd_test; wire [15:0] pxd_test;
reg [SENS_WIDTH_BITS-1:0] col_num_test; reg [SENS_TEST_WIDTH_BITS-1:0] col_num_test;
reg [SENS_HEIGHT_BITS-1:0] row_num_test; reg [SENS_TEST_HEIGHT_BITS-1:0] row_num_test;
reg [7:0] col_num8_test; reg [7:0] col_num8_test;
reg [7:0] row_num8_test; reg [7:0] row_num8_test;
reg [3:0] col_div_test; reg [3:0] col_div_test;
reg [3:0] row_div_test; reg [3:0] row_div_test;
reg dvalid_r; reg dvalid_r;
reg [31:0] data_r; reg [31:0] data_r;
reg set_uart_ctrl; // set UART control bits (both TX and receive) reg set_uart_ctrl; // set UART control bits (both TX and receive)
reg set_uart_tx; // set UART tx data (full, starting witgh channel number = 0) reg set_uart_tx; // set UART tx data (full, starting witgh channel number = 0)
reg set_idelays; reg set_idelays;
reg set_iclk_phase; reg set_iclk_phase;
reg set_ctrl_r; reg set_ctrl_r;
reg set_status_r; reg set_status_r;
wire perr; // parity error from deserializer wire perr; // parity error from deserializer
wire ps_rdy; wire ps_rdy;
wire [7:0] ps_out; wire [7:0] ps_out;
wire [7:0] test_out; // should be 0x17 from unused serial signals wire [7:0] test_out; // should be 0x17 from unused serial signals
wire clkin_pxd_stopped_mmcm; wire clkin_pxd_stopped_mmcm;
wire clkfb_pxd_stopped_mmcm; wire clkfb_pxd_stopped_mmcm;
// programmed resets to the sensor // programmed resets to the sensor
reg imrst = 0; // active low reg imrst = 0; // active low
...@@ -244,7 +254,8 @@ module sens_103993 #( ...@@ -244,7 +254,8 @@ module sens_103993 #(
wire perr_mclk; wire perr_mclk;
reg hact_alive; reg hact_alive;
reg perr_persistent; reg perr_persistent;
reg nonlock_persistent; // detects if MMCM looses lock (or input clock)
// new for Boson // new for Boson
wire txd; wire txd;
wire rxd; wire rxd;
...@@ -273,7 +284,7 @@ module sens_103993 #( ...@@ -273,7 +284,7 @@ module sens_103993 #(
recv_pav, // 14 recv_pav, // 14
imrst ? hact_alive : gp_comb, // 13 using gp_comb to keep imrst ? hact_alive : gp_comb, // 13 using gp_comb to keep
locked_pclk, // 12 // wait after mrst locked_pclk, // 12 // wait after mrst
clkin_pxd_stopped_mmcm, // 11 test_patt? nonlock_persistent : clkin_pxd_stopped_mmcm, // 11
clkfb_pxd_stopped_mmcm, // 10 clkfb_pxd_stopped_mmcm, // 10
perr_persistent, // 9 deserializer parity error perr_persistent, // 9 deserializer parity error
test_patt? perr : ps_rdy, // 8 test_patt? perr : ps_rdy, // 8
...@@ -346,8 +357,7 @@ module sens_103993 #( ...@@ -346,8 +357,7 @@ module sens_103993 #(
else if (set_ctrl_r && data_r[SENS_CTRL_GP3 + 2]) gp_r[7:6] <= data_r[SENS_CTRL_GP3+:2]; else if (set_ctrl_r && data_r[SENS_CTRL_GP3 + 2]) gp_r[7:6] <= data_r[SENS_CTRL_GP3+:2];
if (mrst) test_patt <= 0; if (mrst) test_patt <= 0;
else if (set_ctrl_r && data_r[RESET_TEST_OUT]) test_patt <= 0; else if (set_ctrl_r && data_r[SENS_ALT_STATUS_SET]) test_patt <= data_r[SENS_ALT_STATUS];
else if (set_ctrl_r && data_r[SET_TEST_OUT]) test_patt <= 1;
if (mrst) test_mode <= 0; if (mrst) test_mode <= 0;
else if (set_ctrl_r && data_r[SENS_TEST_SET]) test_mode <= data_r[SENS_TEST_MODES+:SENS_TEST_BITS]; else if (set_ctrl_r && data_r[SENS_TEST_SET]) test_mode <= data_r[SENS_TEST_MODES+:SENS_TEST_BITS];
...@@ -371,6 +381,9 @@ module sens_103993 #( ...@@ -371,6 +381,9 @@ module sens_103993 #(
if (mrst || set_ctrl_r) perr_persistent <= 0; if (mrst || set_ctrl_r) perr_persistent <= 0;
else if (perr_mclk) perr_persistent <= 1; else if (perr_mclk) perr_persistent <= 1;
if (mrst || set_ctrl_r) nonlock_persistent <= 0;
else if (!locked_pclk || clkin_pxd_stopped_mmcm || clkfb_pxd_stopped_mmcm) nonlock_persistent <= 1;
end end
cmd_deser #( cmd_deser #(
...@@ -503,8 +516,8 @@ module sens_103993 #( ...@@ -503,8 +516,8 @@ module sens_103993 #(
((test_mode == 2) ? {6'b0,col_num_test[9:0]}: ((test_mode == 2) ? {6'b0,col_num_test[9:0]}:
{6'b0,row_num_test[9:0]}); {6'b0,row_num_test[9:0]});
always @(posedge pclk) begin always @(posedge pclk) begin
if (!dvalid_w) col_div_test <= SENS_WIDTH_INC-1; if (!dvalid_w) col_div_test <= SENS_TEST_WIDTH_INC-1;
else col_div_test <= (col_div_test == 0)? (SENS_WIDTH_INC-1) : (col_div_test - 1); else col_div_test <= (col_div_test == 0)? (SENS_TEST_WIDTH_INC-1) : (col_div_test - 1);
if (!dvalid_w) col_num8_test <= 0; if (!dvalid_w) col_num8_test <= 0;
else if (col_div_test == 0) col_num8_test <= col_num8_test + 1; else if (col_div_test == 0) col_num8_test <= col_num8_test + 1;
...@@ -512,8 +525,8 @@ module sens_103993 #( ...@@ -512,8 +525,8 @@ module sens_103993 #(
if (!dvalid_w) col_num_test <= 0; if (!dvalid_w) col_num_test <= 0;
else col_num_test <= col_num_test + 1; else col_num_test <= col_num_test + 1;
if (!vsync) row_div_test <= SENS_HEIGHT_INC-1; if (!vsync) row_div_test <= SENS_TEST_HEIGHT_INC-1;
else if (!dvalid_w && dvalid_r) row_div_test <= (row_div_test == 0)? (SENS_HEIGHT_INC-1) : (row_div_test - 1); else if (!dvalid_w && dvalid_r) row_div_test <= (row_div_test == 0)? (SENS_TEST_HEIGHT_INC-1) : (row_div_test - 1);
if (!vsync) row_num8_test <= 0; if (!vsync) row_num8_test <= 0;
else if (!dvalid_w && dvalid_r && (row_div_test == 0)) row_num8_test <= row_num8_test + 1; else if (!dvalid_w && dvalid_r && (row_div_test == 0)) row_num8_test <= row_num8_test + 1;
......
...@@ -176,8 +176,8 @@ module sens_103993_clock#( ...@@ -176,8 +176,8 @@ module sens_103993_clock#(
.CLKOUT0_PHASE (PCLK_PHASE), .CLKOUT0_PHASE (PCLK_PHASE),
.CLKOUT1_PHASE (IPCLK2X_PHASE), .CLKOUT1_PHASE (IPCLK2X_PHASE),
.CLKFBOUT_USE_FINE_PS("FALSE"), .CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKOUT0_USE_FINE_PS ("TRUE"), .CLKOUT0_USE_FINE_PS ("FALSE"), //"TRUE"),
.CLKOUT1_USE_FINE_PS ("TRUE"), .CLKOUT1_USE_FINE_PS ("FALSE"), //"TRUE"),
.CLKOUT0_DIVIDE_F (CLKFBOUT_MULT_SENSOR), // /30, -> 27MHz .CLKOUT0_DIVIDE_F (CLKFBOUT_MULT_SENSOR), // /30, -> 27MHz
.CLKOUT1_DIVIDE (CLKFBOUT_MULT_SENSOR / 10), // /3, -> 270MHz .CLKOUT1_DIVIDE (CLKFBOUT_MULT_SENSOR / 10), // /3, -> 270MHz
.COMPENSATION ("ZHOLD"), .COMPENSATION ("ZHOLD"),
......
...@@ -208,6 +208,15 @@ module sensor_channel#( ...@@ -208,6 +208,15 @@ module sensor_channel#(
parameter SENS_UART_RECV_RST = 4, // 5: 4 parameter SENS_UART_RECV_RST = 4, // 5: 4
parameter SENS_UART_XMIT_START = 6, // 6 parameter SENS_UART_XMIT_START = 6, // 6
parameter SENS_UART_RECV_NEXT = 7, // 7 parameter SENS_UART_RECV_NEXT = 7, // 7
parameter SENS_ALT_STATUS = 24,
parameter SENS_ALT_STATUS_SET = 25,
parameter SENS_TEST_MODES = 26,
parameter SENS_TEST_BITS = 3,
parameter SENS_TEST_SET= 29,
parameter SENS_TEST_WIDTH_BITS = 10,
parameter SENS_TEST_HEIGHT_BITS= 10,
parameter SENS_TEST_WIDTH_INC = 3,
parameter SENS_TEST_HEIGHT_INC = 3,
`elsif PAR12 `elsif PAR12
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20 parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
...@@ -1188,6 +1197,7 @@ module sensor_channel#( ...@@ -1188,6 +1197,7 @@ module sensor_channel#(
.SENSIO_STATUS (SENSIO_STATUS), .SENSIO_STATUS (SENSIO_STATUS),
.SENSIO_DELAYS (SENSIO_DELAYS), .SENSIO_DELAYS (SENSIO_DELAYS),
.SENSIO_STATUS_REG (SENSIO_STATUS_REG), .SENSIO_STATUS_REG (SENSIO_STATUS_REG),
.SENS_CTRL_MRST (SENS_CTRL_MRST), .SENS_CTRL_MRST (SENS_CTRL_MRST),
.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM), .SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM),
.SENS_CTRL_LD_DLY (SENS_CTRL_LD_DLY), .SENS_CTRL_LD_DLY (SENS_CTRL_LD_DLY),
...@@ -1200,6 +1210,16 @@ module sensor_channel#( ...@@ -1200,6 +1210,16 @@ module sensor_channel#(
.SENS_UART_RECV_RST (SENS_UART_RECV_RST), .SENS_UART_RECV_RST (SENS_UART_RECV_RST),
.SENS_UART_XMIT_START (SENS_UART_XMIT_START), .SENS_UART_XMIT_START (SENS_UART_XMIT_START),
.SENS_UART_RECV_NEXT (SENS_UART_RECV_NEXT), .SENS_UART_RECV_NEXT (SENS_UART_RECV_NEXT),
.SENS_ALT_STATUS (SENS_ALT_STATUS),
.SENS_ALT_STATUS_SET (SENS_ALT_STATUS_SET),
.SENS_TEST_MODES (SENS_TEST_MODES),
.SENS_TEST_BITS (SENS_TEST_BITS),
.SENS_TEST_SET (SENS_TEST_SET),
.SENS_TEST_WIDTH_BITS (SENS_TEST_WIDTH_BITS),
.SENS_TEST_HEIGHT_BITS (SENS_TEST_HEIGHT_BITS),
.SENS_TEST_WIDTH_INC (SENS_TEST_WIDTH_INC),
.SENS_TEST_HEIGHT_INC (SENS_TEST_HEIGHT_INC),
.IODELAY_GRP (IODELAY_GRP), .IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE), .IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY), .REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
......
...@@ -190,6 +190,15 @@ module sensors393 #( ...@@ -190,6 +190,15 @@ module sensors393 #(
parameter SENS_UART_RECV_RST = 4, // 5: 4 parameter SENS_UART_RECV_RST = 4, // 5: 4
parameter SENS_UART_XMIT_START = 6, // 6 parameter SENS_UART_XMIT_START = 6, // 6
parameter SENS_UART_RECV_NEXT = 7, // 7 parameter SENS_UART_RECV_NEXT = 7, // 7
parameter SENS_ALT_STATUS = 24,
parameter SENS_ALT_STATUS_SET = 25,
parameter SENS_TEST_MODES = 26,
parameter SENS_TEST_BITS = 3,
parameter SENS_TEST_SET= 29,
parameter SENS_TEST_WIDTH_BITS = 10,
parameter SENS_TEST_HEIGHT_BITS= 10,
parameter SENS_TEST_WIDTH_INC = 3,
parameter SENS_TEST_HEIGHT_INC = 3,
`else `else
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20 parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
...@@ -790,6 +799,16 @@ module sensors393 #( ...@@ -790,6 +799,16 @@ module sensors393 #(
.SENS_UART_RECV_RST (SENS_UART_RECV_RST), .SENS_UART_RECV_RST (SENS_UART_RECV_RST),
.SENS_UART_XMIT_START (SENS_UART_XMIT_START), .SENS_UART_XMIT_START (SENS_UART_XMIT_START),
.SENS_UART_RECV_NEXT (SENS_UART_RECV_NEXT), .SENS_UART_RECV_NEXT (SENS_UART_RECV_NEXT),
.SENS_ALT_STATUS (SENS_ALT_STATUS),
.SENS_ALT_STATUS_SET (SENS_ALT_STATUS_SET),
.SENS_TEST_MODES (SENS_TEST_MODES),
.SENS_TEST_BITS (SENS_TEST_BITS),
.SENS_TEST_SET (SENS_TEST_SET),
.SENS_TEST_WIDTH_BITS (SENS_TEST_WIDTH_BITS),
.SENS_TEST_HEIGHT_BITS (SENS_TEST_HEIGHT_BITS),
.SENS_TEST_WIDTH_INC (SENS_TEST_WIDTH_INC),
.SENS_TEST_HEIGHT_INC (SENS_TEST_HEIGHT_INC),
`else `else
.SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS), .SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS),
.SENS_CTRL_ODD (SENS_CTRL_ODD), .SENS_CTRL_ODD (SENS_CTRL_ODD),
......
...@@ -1431,6 +1431,8 @@ assign axi_grst = axi_rst_pre; ...@@ -1431,6 +1431,8 @@ assign axi_grst = axi_rst_pre;
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT), .MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED), .MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE), .MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE),
.MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE),
.MCONTR_LINTILE_NO_PENDING (MCONTR_LINTILE_NO_PENDING),
.MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH), .MCNTRL_SCANLINE_DLY_WIDTH (MCNTRL_SCANLINE_DLY_WIDTH),
.MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT), .MCNTRL_SCANLINE_DLY_DEFAULT (MCNTRL_SCANLINE_DLY_DEFAULT),
.BUFFER_DEPTH32 (BUFFER_DEPTH32), .BUFFER_DEPTH32 (BUFFER_DEPTH32),
...@@ -1874,7 +1876,16 @@ assign axi_grst = axi_rst_pre; ...@@ -1874,7 +1876,16 @@ assign axi_grst = axi_rst_pre;
.SENS_UART_RECV_RST (SENS_UART_RECV_RST), .SENS_UART_RECV_RST (SENS_UART_RECV_RST),
.SENS_UART_XMIT_START (SENS_UART_XMIT_START), .SENS_UART_XMIT_START (SENS_UART_XMIT_START),
.SENS_UART_RECV_NEXT (SENS_UART_RECV_NEXT), .SENS_UART_RECV_NEXT (SENS_UART_RECV_NEXT),
`else .SENS_ALT_STATUS (SENS_ALT_STATUS),
.SENS_ALT_STATUS_SET (SENS_ALT_STATUS_SET),
.SENS_TEST_MODES (SENS_TEST_MODES),
.SENS_TEST_BITS (SENS_TEST_BITS),
.SENS_TEST_SET (SENS_TEST_SET),
.SENS_TEST_WIDTH_BITS (SENS_TEST_WIDTH_BITS),
.SENS_TEST_HEIGHT_BITS (SENS_TEST_HEIGHT_BITS),
.SENS_TEST_WIDTH_INC (SENS_TEST_WIDTH_INC),
.SENS_TEST_HEIGHT_INC (SENS_TEST_HEIGHT_INC),
`else
.SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS), .SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS),
.SENS_CTRL_ODD (SENS_CTRL_ODD), .SENS_CTRL_ODD (SENS_CTRL_ODD),
.SENS_CTRL_QUADRANTS_WIDTH (SENS_CTRL_QUADRANTS_WIDTH), .SENS_CTRL_QUADRANTS_WIDTH (SENS_CTRL_QUADRANTS_WIDTH),
......
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