Commit 2be629f5 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

FPGA version 039300fd (hispi), changed lanes alignment report mode

parent 07e41034

fpga_version.vh

+2 −1
Original line number Original line Diff line number Diff line
@@ -36,7 +36,8 @@ 
 * with at least one of the Free Software programs.

 * with at least one of the Free Software programs.

 */

 */

 

 

        parameter FPGA_VERSION =          32'h039300fc;      // serial - 17.4 - skipping first lines? pclk dsp1->dsp2 3*54ps

        parameter FPGA_VERSION =          32'h039300fd;      // serial - 17.4 - monitor lanes barrel (0..3)

//      parameter FPGA_VERSION =          32'h039300fc;      // serial - 17.4 - skipping first lines? pclk dsp1->dsp2 3*54ps

//      parameter FPGA_VERSION =          32'h039300fb;      // serial - 17.4 - serial, adding trigger control, lanes_alive (violated xclk by 0.004)

//      parameter FPGA_VERSION =          32'h039300fb;      // serial - 17.4 - serial, adding trigger control, lanes_alive (violated xclk by 0.004)

//      parameter FPGA_VERSION =          32'h039300fa;      // serial - 15.3 - serial, modifying lens_flat - timing met

//      parameter FPGA_VERSION =          32'h039300fa;      // serial - 15.3 - serial, modifying lens_flat - timing met

//      parameter FPGA_VERSION =          32'h039300f4;      // parallel - 17.4 - , modifying lens_flat - timing met

//      parameter FPGA_VERSION =          32'h039300f4;      // parallel - 17.4 - , modifying lens_flat - timing met

py393/x393_export_c.py

+6 −2
Original line number Original line Diff line number Diff line
@@ -1853,8 +1853,12 @@ class X393ExportC(object): 
        dw.append(("clkin_pxd_stopped_mmcm",11, 1,0,  "Sensor MMCM input clock stopped"))

        dw.append(("clkin_pxd_stopped_mmcm",11, 1,0,  "Sensor MMCM input clock stopped"))

        dw.append(("locked_pxd_mmcm",       12, 1,0,  "Sensor MMCM locked"))

        dw.append(("locked_pxd_mmcm",       12, 1,0,  "Sensor MMCM locked"))

        dw.append(("hact_alive",            13, 1,0,  "HACT signal from the sensor (or internal) is toggling"))

        dw.append(("hact_alive",            13, 1,0,  "HACT signal from the sensor (or internal) is toggling"))

        dw.append(("lanes_alive",           14, 4,0,  "Per-lane HACT toggling (reset by changing DLL delays)"))

        dw.append(("barrel_0",              14, 2,0,  "Lane 0 barrel shift"))

        dw.append(("rel_sol",               18, 3,0,  "When SOL active on the last lane @ipclk, latches all other lanes SOL"))

        dw.append(("barrel_1",              16, 2,0,  "Lane 1 barrel shift"))

        dw.append(("barrel_2",              18, 2,0,  "Lane 2 barrel shift"))

        dw.append(("barrel_3",              20, 2,0,  "Lane 3 barrel shift"))

#        dw.append(("lanes_alive",           14, 4,0,  "Per-lane HACT toggling (reset by changing DLL delays)"))

#        dw.append(("rel_sol",               18, 3,0,  "When SOL active on the last lane @ipclk, latches all other lanes SOL"))

#        dw.append(("vact_alive",            15, 1,0,  "VACT signal from the sensor is toggling (N/A for HiSPI)"))

#        dw.append(("vact_alive",            15, 1,0,  "VACT signal from the sensor is toggling (N/A for HiSPI)"))

#        dw.append(("xfpgatdo_byte",         16, 8,0,  "Multiplexer FPGA TDO output"))

#        dw.append(("xfpgatdo_byte",         16, 8,0,  "Multiplexer FPGA TDO output"))

        dw.append(("senspgmin",             24, 1,0,  "senspgm pin state"))

        dw.append(("senspgmin",             24, 1,0,  "senspgm pin state"))

sensor/sens_10398.v

+19 −13
Original line number Original line Diff line number Diff line
@@ -200,7 +200,8 @@ module sens_10398 #( 




//    wire [14:0] status;

//    wire [14:0] status;

//    wire [19:0] status;

//    wire [19:0] status;

    wire [22:0] status;

//    wire [22:0] status;

    wire [23:0] status;

    

    

    wire        cmd_we;

    wire        cmd_we;

    wire  [2:0] cmd_a;

    wire  [2:0] cmd_a;
@@ -224,11 +225,13 @@ module sens_10398 #( 
    reg            hact_r;

    reg            hact_r;

    wire           hact_mclk;

    wire           hact_mclk;

    reg            hact_alive;

    reg            hact_alive;

    wire  [HISPI_NUMLANES-1:0] monitor_pclk;

    wire  [HISPI_NUMLANES*2-1:0] mon_barrel;          // @ipclk per-lane monitor barrel shifter  

    wire  [HISPI_NUMLANES-2:0] monitor_diff;    

//    wire  [HISPI_NUMLANES-1:0] monitor_pclk;

    wire  [HISPI_NUMLANES-1:0] monitor_mclk;

//    wire  [HISPI_NUMLANES-1:0] monitor_mclk;

    reg   [HISPI_NUMLANES-1:0] lanes_alive;

//    wire  [HISPI_NUMLANES-2:0] monitor_diff;  

    assign status = {monitor_diff, lanes_alive,

//    reg   [HISPI_NUMLANES-1:0] lanes_alive;

//    assign status = {monitor_diff, lanes_alive,

    assign status = {mon_barrel,

                     hact_alive, locked_pxd_mmcm, 

                     hact_alive, locked_pxd_mmcm, 

                     clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,

                     clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,

                     ps_rdy, ps_out,

                     ps_rdy, ps_out,
@@ -318,8 +321,8 @@ module sens_10398 #( 
        if      (mrst || set_iclk_phase || set_idelays)     hact_alive <= 0;

        if      (mrst || set_iclk_phase || set_idelays)     hact_alive <= 0;

        else if (hact_mclk)                                 hact_alive <= 1;

        else if (hact_mclk)                                 hact_alive <= 1;

        

        

        if      (mrst || set_iclk_phase || set_idelays)     lanes_alive <= 0;

//        if      (mrst || set_iclk_phase || set_idelays)     lanes_alive <= 0;

        else                                                lanes_alive <= lanes_alive | monitor_mclk;

//        else                                                lanes_alive <= lanes_alive | monitor_mclk;





        if      (mrst)                                      lines_skip <= 0;

        if      (mrst)                                      lines_skip <= 0;

        else if (set_skip_r)                                lines_skip <= data_r[SENSIO_SKIP_BITS-1:0]; 

        else if (set_skip_r)                                lines_skip <= data_r[SENSIO_SKIP_BITS-1:0];
@@ -375,7 +378,8 @@ module sens_10398 #( 




    status_generate #(

    status_generate #(

        .STATUS_REG_ADDR(SENSIO_STATUS_REG),

        .STATUS_REG_ADDR(SENSIO_STATUS_REG),

        .PAYLOAD_BITS(3+15+1+HISPI_NUMLANES) // +3) // +STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS)

//        .PAYLOAD_BITS(3+15+1+HISPI_NUMLANES) // +3) // +STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS)

        .PAYLOAD_BITS(15+1+2*HISPI_NUMLANES) // +3) // +STATUS_ALIVE_WIDTH) // STATUS_PAYLOAD_BITS)

    ) status_generate_sens_io_i (

    ) status_generate_sens_io_i (

        .rst        (1'b0),                    // rst), // input

        .rst        (1'b0),                    // rst), // input

        .clk        (mclk),                    // input

        .clk        (mclk),                    // input
@@ -452,10 +456,12 @@ module sens_10398 #( 
        .locked_pxd_mmcm        (locked_pxd_mmcm),        // output

        .locked_pxd_mmcm        (locked_pxd_mmcm),        // output

        .clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output

        .clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output

        .clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm), // output

        .clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm), // output

        .monitor_pclk           (monitor_pclk),           // output reg[3:0] // for monitoring: each bit contains single cycle @pclk line starts

        .monitor_pclk           (), // monitor_pclk),           // output reg[3:0] // for monitoring: each bit contains single cycle @pclk line starts

        .monitor_diff           (monitor_diff)            // when SOL active on the last lane @ipclk, latches all other lanes SOL,

        .monitor_diff           (), // monitor_diff),           // when SOL active on the last lane @ipclk, latches all other lanes SOL,

    );

        .mon_barrel             (mon_barrel)              // output[7:0] // @ipclk per-lane monitor barrel shifter

        

        

    );

/*    

    dly_16 #(

    dly_16 #(

        .WIDTH(HISPI_NUMLANES)

        .WIDTH(HISPI_NUMLANES)

    ) dly_16_monitor_i (

    ) dly_16_monitor_i (
@@ -465,7 +471,7 @@ module sens_10398 #( 
        .din  (monitor_pclk),                // input[3:0] 

        .din  (monitor_pclk),                // input[3:0] 

        .dout (monitor_mclk)                 // output[3:0] 

        .dout (monitor_mclk)                 // output[3:0] 

    );

    );

    

*/

/*

/*

    output reg [HISPI_NUMLANES-1:0] monitor_pclk    // for monitoring: each bit contains single cycle @pclk line starts    

    output reg [HISPI_NUMLANES-1:0] monitor_pclk    // for monitoring: each bit contains single cycle @pclk line starts

sensor/sens_hispi12l4.v

+5 −4
Original line number Original line Diff line number Diff line
@@ -114,7 +114,8 @@ module sens_hispi12l4#( 
    output                         clkin_pxd_stopped_mmcm, // output

    output                         clkin_pxd_stopped_mmcm, // output

    output                         clkfb_pxd_stopped_mmcm, // output

    output                         clkfb_pxd_stopped_mmcm, // output

    output reg [HISPI_NUMLANES-1:0] monitor_pclk,       // for monitoring: each bit contains single cycle @pclk line starts    

    output reg [HISPI_NUMLANES-1:0] monitor_pclk,       // for monitoring: each bit contains single cycle @pclk line starts    

    output reg [HISPI_NUMLANES-2:0] monitor_diff        // for monitoring: when SOL active on the last lane @ipclk, latches all other lanes SOL,     

    output reg [HISPI_NUMLANES-2:0] monitor_diff,       // for monitoring: when SOL active on the last lane @ipclk, latches all other lanes SOL,

    output   [HISPI_NUMLANES*2-1:0] mon_barrel          // @ipclk per-lane monitor barrel shifter

    

    

);

);

    wire                          ipclk;  // re-generated half HiSPi clock (165 MHz) 

    wire                          ipclk;  // re-generated half HiSPi clock (165 MHz)
@@ -235,6 +236,7 @@ module sens_hispi12l4#( 
    wire      [HISPI_NUMLANES-1:0] hispi_eof;

    wire      [HISPI_NUMLANES-1:0] hispi_eof;

    wire      [HISPI_NUMLANES-1:0] hispi_sol;

    wire      [HISPI_NUMLANES-1:0] hispi_sol;

    wire      [HISPI_NUMLANES-1:0] hispi_eol;

    wire      [HISPI_NUMLANES-1:0] hispi_eol;

//    wire    [HISPI_NUMLANES*2-1:0] mon_barrel; // per-lane monitor barrel shifter

   // TODO - try to make that something will be recorded even if some lanes are bad (to simplify phase adjust

   // TODO - try to make that something will be recorded even if some lanes are bad (to simplify phase adjust

   // possibly - extra control bit (wait_all_lanes)

   // possibly - extra control bit (wait_all_lanes)

   //    use earliest SOF

   //    use earliest SOF
@@ -381,9 +383,7 @@ module sens_hispi12l4#( 
    ) dly_16_pxd_out_i (

    ) dly_16_pxd_out_i (

        .clk  (pclk),                        // input

        .clk  (pclk),                        // input

        .rst  (1'b0),                        // input

        .rst  (1'b0),                        // input

//        .dly  (4'h2),                        // input[3:0] 

        .dly  (4'h0),                        // input[3:0] 

        .dly  (4'h0),                        // input[3:0] 

//        .dly  (4'h1),                        // input[3:0] 

        .din  (pxd_out_pre),                 // input[0:0] 

        .din  (pxd_out_pre),                 // input[0:0] 

        .dout (pxd_out)                      // output[0:0] 

        .dout (pxd_out)                      // output[0:0] 

    );

    );
@@ -403,7 +403,8 @@ module sens_hispi12l4#( 
                .sof      (hispi_sof[i]),              // output reg 

                .sof      (hispi_sof[i]),              // output reg 

                .eof      (hispi_eof[i]),              // output reg 

                .eof      (hispi_eof[i]),              // output reg 

                .sol      (hispi_sol[i]),              // output reg 

                .sol      (hispi_sol[i]),              // output reg 

                .eol      (hispi_eol[i])               // output reg 

                .eol      (hispi_eol[i]),              // output reg

                .mon_barrel (mon_barrel[2*i +: 2])     // output reg 1:0 

            );

            );

            sens_hispi_fifo #(

            sens_hispi_fifo #(

//                .COUNT_START  (HISPI_FIFO_START),

//                .COUNT_START  (HISPI_FIFO_START),

sensor/sens_hispi_lane.v

+3 −1
Original line number Original line Diff line number Diff line
@@ -50,7 +50,8 @@ module sens_hispi_lane#( 
    output reg        sof,     // always before first sol - not instead of

    output reg        sof,     // always before first sol - not instead of

    output reg        eof,     // always after last eol (not instead of)

    output reg        eof,     // always after last eol (not instead of)

    output reg        sol,     // start of line - 1 cycle before dv

    output reg        sol,     // start of line - 1 cycle before dv

    output reg        eol      // end of line - last dv 

    output reg        eol,      // end of line - last dv

    output reg [1:0]  mon_barrel // monitor barrel shifter    

);

);

    localparam  [3:0] SYNC_SOF = HISPI_MSB_FIRST ? 4'h3 : 4'hc;

    localparam  [3:0] SYNC_SOF = HISPI_MSB_FIRST ? 4'h3 : 4'hc;

    localparam  [3:0] SYNC_SOL = HISPI_MSB_FIRST ? 4'h1 : 4'h8;

    localparam  [3:0] SYNC_SOL = HISPI_MSB_FIRST ? 4'h1 : 4'h8;
@@ -131,6 +132,7 @@ module sens_hispi_lane#( 
        if      (irst)       shift_val <= 0;

        if      (irst)       shift_val <= 0;

//      else if (got_sync)   shift_val <= num_first_zeros;

//      else if (got_sync)   shift_val <= num_first_zeros;

        else if (got_sync_w) shift_val <= num_first_zeros;

        else if (got_sync_w) shift_val <= num_first_zeros;

        mon_barrel <= shift_val;

        

        

        case (shift_val)

        case (shift_val)

            2'h0: barrel <= din;

            2'h0: barrel <= din;