included system_defines.vh

dsp/dct_tests_01.tf

@@ -38,6 +38,7 @@
  * with at least one of the Free Software programs.
  */
 `timescale 1ns/1ps
+`include "system_defines.vh"
 // No saturation here, and no rounding as we do not need to match decoder (be bit-precise), skipping rounding adder
 // will reduce needed resources
 //`define DCT_INPUT_UNITY

dsp/dct_tests_02.tf

@@ -38,6 +38,7 @@
  * with at least one of the Free Software programs.
  */
 `timescale 1ns/1ps
+`include "system_defines.vh"
 // No saturation here, and no rounding as we do not need to match decoder (be bit-precise), skipping rounding adder
 // will reduce needed resources
 //`define DCT_INPUT_UNITY

dsp/dct_tests_03.tf

@@ -38,6 +38,7 @@
  * with at least one of the Free Software programs.
  */
 `timescale 1ns/1ps
+`include "system_defines.vh"
 // No saturation here, and no rounding as we do not need to match decoder (be bit-precise), skipping rounding adder
 // will reduce needed resources
 //`define DCT_INPUT_UNITY

dsp/dct_tests_04.tf

@@ -38,7 +38,8 @@
  * with at least one of the Free Software programs.
  */
 `timescale 1ns/1ps
-  `define INSTANTIATE_DSP48E1 
+`include "system_defines.vh"
+//  `define INSTANTIATE_DSP48E1 
 
 // No saturation here, and no rounding as we do not need to match decoder (be bit-precise), skipping rounding adder
 // will reduce needed resources

dsp/mclt_test_01.tf

@@ -38,8 +38,10 @@
  * with at least one of the Free Software programs.
  */
 `timescale 1ns/1ps
-  `define INSTANTIATE_DSP48E1
-  `define PRELOAD_BRAMS
+`include "system_defines.vh"
+//  `define INSTANTIATE_DSP48E1
+//  `undef INSTANTIATE_DSP48E1
+//  `define PRELOAD_BRAMS
 //  `define ROUND 
 module  mclt_test_01 ();
 `ifdef IVERILOG              

dsp/mclt_test_02.tf

@@ -38,8 +38,9 @@
  * with at least one of the Free Software programs.
  */
 `timescale 1ns/1ps
-  `define INSTANTIATE_DSP48E1
-  `define PRELOAD_BRAMS
+`include "system_defines.vh"
+//  `define INSTANTIATE_DSP48E1
+//  `define PRELOAD_BRAMS
 //  `define ROUND 
 module  mclt_test_02 ();
 `ifdef IVERILOG