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Commit 2b1975c3 authored by Andrey Filippov's avatar Andrey Filippov
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implemented optional skipping/fast forward of the data blocks when buffer is... 

implemented optional skipping/fast forward of the data blocks when buffer is over/underrun during memory access
parent 75f18826
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Showing with 1069 additions and 132 deletions
includes/tasks_tests_memory.vh
View file @ 2b1975c3
......@@ -149,6 +149,7 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
(window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0},
start64, lo_addr64, size64, $time);
mode= func_encode_mode_scanline(
1'b0, // skip_too_late
disable_need,
repetitive,
single,
......@@ -250,6 +251,7 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_scanline(
1'b0, // skip_too_late
disable_need,
repetitive,
single,
......@@ -391,6 +393,7 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_scanline(
1'b0, // skip_too_late
disable_need,
repetitive,
single,
......@@ -505,6 +508,7 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_tiled(
1'b0, // skip_too_late
disable_need,
repetitive,
single,
......@@ -637,6 +641,7 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_tiled(
1'b0, // skip_too_late
disable_need,
repetitive,
single,
......
includes/x393_parameters.vh
View file @ 2b1975c3
......@@ -273,6 +273,7 @@
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
// Channel test module parameters
parameter MCNTRL_TEST01_ADDR= 'h0f0,
......@@ -526,7 +527,7 @@
//`endif
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
// parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
// parameters for the sensor-synchronous clock PLL
......
memctrl/mcntrl393.v
View file @ 2b1975c3
This diff is collapsed.
memctrl/mcntrl_linear_rw.v
View file @ 2b1975c3
......@@ -57,7 +57,8 @@ module mcntrl_linear_rw #(
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11 // disable 'need' request
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12 // skip actual R/W operation when it is too late, advance pointers
)(
input mrst,
input mclk,
......@@ -82,6 +83,7 @@ module mcntrl_linear_rw #(
output xfer_want, // "want" data transfer
output xfer_need, // "need" - really need a transfer (only 1 page/ room for 1 page left in a buffer), want should still be set.
input xfer_grant, // sequencer programming access granted, deassert wait/need
output xfer_reject, // reject granted access (when skipping)
output xfer_start_rd, // initiate a transfer (next cycle after xfer_grant)
output xfer_start_wr, // initiate a transfer (next cycle after xfer_grant)
output [2:0] xfer_bank, // bank address
......@@ -150,6 +152,7 @@ module mcntrl_linear_rw #(
// wire cmd_wrmem; //=MCNTRL_SCANLINE_WRITE_MODE; // 0: read from memory, 1:write to memory
wire [1:0] cmd_extra_pages; // external module needs more than 1 page
wire skip_too_late;
wire disable_need; // do not assert need, only want
wire repeat_frames; // mode bit
wire single_frame_w; // pulse
......@@ -191,7 +194,7 @@ module mcntrl_linear_rw #(
wire msw_zero= !(|cmd_data[31:16]); // MSW all bits are 0 - set carry bit
reg [11:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}
reg [12:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}
reg [NUM_RC_BURST_BITS-1:0] start_range_addr; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
reg [NUM_RC_BURST_BITS-1:0] frame_size; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
......@@ -233,7 +236,7 @@ module mcntrl_linear_rw #(
// Set parameter registers
always @(posedge mclk) begin
if (mrst) mode_reg <= 0;
else if (set_mode_w) mode_reg <= cmd_data[11:0]; // 4:0]; // [4:0];
else if (set_mode_w) mode_reg <= cmd_data[12:0]; // 4:0]; // [4:0];
if (mrst) single_frame_r <= 0;
else single_frame_r <= single_frame_w;
......@@ -337,19 +340,51 @@ module mcntrl_linear_rw #(
assign cmd_extra_pages = mode_reg[MCONTR_LINTILE_EXTRAPG+:MCONTR_LINTILE_EXTRAPG_BITS]; // external module needs more than 1 page
assign repeat_frames= mode_reg[MCONTR_LINTILE_REPEAT];
assign disable_need = mode_reg[MCONTR_LINTILE_DIS_NEED];
assign skip_too_late = mode_reg[MCONTR_LINTILE_SKIP_LATE];
assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit?
assign pgm_param_w= cmd_we;
localparam [COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] EXTRA_BITS=0;
assign remainder_in_xfer = {EXTRA_BITS, lim_by_xfer}-mem_page_left;
integer i;
wire xfer_limited_by_mem_page;
wire xfer_limited_by_mem_page= mem_page_left < {EXTRA_BITS,lim_by_xfer};
reg xfer_limited_by_mem_page_r;
assign xfer_limited_by_mem_page= mem_page_left < {EXTRA_BITS,lim_by_xfer};
// skipping pages that did not make it
// reg skip_tail; // skip end of frame if the next frame started (TBD)
// Now skip if write and >=4 or read and >=5 (read starts with 4 and may end with 4)
// Also if the next page signal is used by the source/dest of data, it should use reject pulse to advance external
// page counter
wire start_skip_w = skip_too_late && want_r && (page_cntr >= 4) && !xfer_grant && (cmd_wrmem || page_cntr[0]); //&& busy_r && skip_run;
reg start_skip_r;
reg skip_run = 0; // run "skip" - advance addresses, but no actual read/write
reg xfer_reject_r;
assign xfer_reject = xfer_reject_r;
always @(posedge mclk) begin // Handling skip/reject
if (mrst) xfer_reject_r <= 0;
else xfer_reject_r <= xfer_grant && !chn_rst && skip_run;
if (mrst) xfer_start_r <= 0;
else xfer_start_r <= {xfer_start_r[1:0], (xfer_grant & ~chn_rst & ~skip_run) | start_skip_r};
if (mrst) xfer_start_rd_r <= 0;
else xfer_start_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && !skip_run;
if (mrst) xfer_start_wr_r <= 0;
else xfer_start_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && !skip_run;
if (mrst || recalc_r[PAR_MOD_LATENCY-1]) skip_run <= 0;
else if (start_skip_w) skip_run <= 1;
if (mrst) start_skip_r <= 0;
else start_skip_r <= start_skip_w;
end
/// Recalcualting just after starting request - preparing for the next one. Also happens after parameter change.
/// Should dpepend only on the parameters updated separately (curr_x, curr_y)
/// Should dppend only on the parameters updated separately (curr_x, curr_y)
always @(posedge mclk) begin // TODO: Match latencies (is it needed?) Reduce consumption by CE?
if (recalc_r[0]) begin // cycle 1
frame_x <= curr_x + window_x0;
......@@ -442,14 +477,6 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
else if (chn_rst || frame_start_r[0]) frame_finished_r <= 0;
else if (frame_done_r) frame_finished_r <= 1;
if (mrst) xfer_start_r <= 0;
else xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst};
if (mrst) xfer_start_rd_r <= 0;
else xfer_start_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem;
if (mrst) xfer_start_wr_r <= 0;
else xfer_start_wr_r <= xfer_grant && !chn_rst && cmd_wrmem;
if (mrst || disable_need) need_r <= 0;
else if (chn_rst || xfer_grant) need_r <= 0;
......
memctrl/memctrl16.v
View file @ 2b1975c3
This diff is collapsed.
sensor/sens_10398.v
View file @ 2b1975c3
......@@ -97,6 +97,7 @@ module sens_10398 #(
)(
input pclk, // global clock input, pixel rate (220MHz for MT9F002)
input prst,
output prsts, // @pclk - includes sensor reset and sensor PLL reset
// delay control inputs
input mclk,
input mrst,
......@@ -189,6 +190,7 @@ module sens_10398 #(
assign iaro = trigger_mode? ~trig : iaro_soft;
assign prsts = prst_with_sens_mrst[0]; // @pclk - includes sensor reset and sensor PLL reset
always @(posedge mclk) begin
......@@ -265,8 +267,8 @@ module sens_10398 #(
if (async_prst_with_sens_mrst) prst_with_sens_mrst <= 2'h3;
else if (prst) prst_with_sens_mrst <= 2'h3;
else prst_with_sens_mrst <= prst_with_sens_mrst >> 1;
end
cmd_deser #(
.ADDR (SENSIO_ADDR),
.ADDR_MASK (SENSIO_ADDR_MASK),
......@@ -331,7 +333,7 @@ module sens_10398 #(
.HISPI_IOSTANDARD (HISPI_IOSTANDARD)
) sens_hispi12l4_i (
.pclk (pclk), // input
.prst (prst_with_sens_mrst[0]), //prst), // input
.prst (prsts), //prst), // input
.sns_dp (sns_dp[3:0]), // input[3:0]
.sns_dn (sns_dn[3:0]), // input[3:0]
.sns_clkp (sns_clkp), // input
......
sensor/sens_hispi12l4.v
View file @ 2b1975c3
......@@ -222,7 +222,8 @@ module sens_hispi12l4#(
end
always @(posedge pclk) begin
vact_pclk_strt <= {vact_pclk_strt[0],vact_ipclk};
if (prst || !vact_ipclk) vact_pclk_strt <= 0;
else vact_pclk_strt <= {vact_pclk_strt[0], 1'b1};
rd_run_d <= rd_run;
......@@ -275,8 +276,8 @@ module sens_hispi12l4#(
.rst (1'b0), // input
// .dly (4'h2), // input[3:0]
// .dly (4'h3), // input[3:0]
// .dly (4'h1), // input[3:0]
.dly (4'h2), // input[3:0]
.dly (4'h1), // input[3:0]
// .dly (4'h2), // input[3:0]
.din (sol_pclk), // input[0:0]
.dout (hact_on) // output[0:0]
);
......@@ -288,8 +289,8 @@ module sens_hispi12l4#(
.rst (1'b0), // input
// .dly (4'h2), // input[3:0]
// .dly (4'h0), // input[3:0]
// .dly (4'h1), // input[3:0]
.dly (4'h2), // input[3:0]
.dly (4'h1), // input[3:0]
// .dly (4'h2), // input[3:0]
.din (fifo_re[HISPI_NUMLANES - 1]), // input[0:0]
.dout (hact_off) // output[0:0]
);
......@@ -300,8 +301,8 @@ module sens_hispi12l4#(
.clk (pclk), // input
.rst (1'b0), // input
// .dly (4'h2), // input[3:0]
// .dly (4'h0), // input[3:0]
.dly (4'h1), // input[3:0]
.dly (4'h0), // input[3:0]
// .dly (4'h1), // input[3:0]
.din (pxd_out_pre), // input[0:0]
.dout (pxd_out) // output[0:0]
);
......
sensor/sens_parallel12.v
View file @ 2b1975c3
......@@ -83,6 +83,7 @@ module sens_parallel12 #(
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
input mclk_rst,
input prst,
output prsts, // @pclk - includes sensor reset and sensor PLL reset
output irst,
output ipclk, // re-generated sensor output clock (regional clock to drive external fifo)
......@@ -204,6 +205,12 @@ module sens_parallel12 #(
reg hact_alive;
reg [STATUS_ALIVE_WIDTH-1:0] status_alive;
reg [1:0] prst_with_sens_mrst = 2'h3; // prst extended to include sensor reset and rst_mmcm
wire async_prst_with_sens_mrst = ~imrst | rst_mmcm; // mclk domain
assign prsts = prst_with_sens_mrst[0]; // @pclk - includes sensor reset and sensor PLL reset
assign set_pxd_delay = set_idelay[2:0];
assign set_other_delay = set_idelay[3];
assign status = {vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm,
......@@ -213,8 +220,16 @@ module sens_parallel12 #(
assign iaro = trigger_mode? ~trig : iaro_soft;
assign irst=irst_r[2];
always @ (posedge ipclk) begin
irst_r <= {irst_r[1:0], prst};
// irst_r <= {irst_r[1:0], prst};
irst_r <= {irst_r[1:0], prsts}; // extended reset that includes sensor reset and rst_mmcm
end
always @(posedge pclk or posedge async_prst_with_sens_mrst) begin
if (async_prst_with_sens_mrst) prst_with_sens_mrst <= 2'h3;
else if (prst) prst_with_sens_mrst <= 2'h3;
else prst_with_sens_mrst <= prst_with_sens_mrst >> 1;
end
always @(posedge mclk) begin
......
sensor/sensor_channel.v
View file @ 2b1975c3
......@@ -205,10 +205,11 @@ module sensor_channel#(
parameter PXD_CAPACITANCE = "DONT_CARE",
parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
parameter PXD_CLK_DIV_BITS = 4,
//`else
// parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
`endif
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
// parameters for the sensor-synchronous clock PLL
......@@ -412,6 +413,7 @@ module sensor_channel#(
wire trig;
reg sof_out_r;
reg eof_out_r;
wire prsts; // @pclk - includes sensor reset and sensor PLL reset
// TODO: insert vignetting and/or flat field, pixel defects before gamma_*_in
assign lens_pxd_in = {pxd[11:0],4'b0};
......@@ -627,7 +629,8 @@ module sensor_channel#(
// for debug/test alive
pulse_cross_clock pulse_cross_clock_sol_mclk_i (
.rst (prst), // input
// .rst (prst), // input
.rst (prsts), // input extended to include sensor reset and rst_mmcm
.src_clk (pclk), // input
.dst_clk (mclk), // input
// .in_pulse (hact && !hact_r), // input
......@@ -637,7 +640,8 @@ module sensor_channel#(
);
pulse_cross_clock pulse_cross_clock_sof_mclk_i (
.rst (prst), // input
// .rst (prst), // input
.rst (prsts), // input extended to include sensor reset and rst_mmcm
.src_clk (pclk), // input
.dst_clk (mclk), // input
// .in_pulse (sof), // input
......@@ -647,7 +651,8 @@ module sensor_channel#(
);
pulse_cross_clock pulse_cross_clock_eof_mclk_i (
.rst (prst), // input
// .rst (prst), // input
.rst (prsts), // input extended to include sensor reset and rst_mmcm
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (eof), // input
......@@ -656,7 +661,8 @@ module sensor_channel#(
);
pulse_cross_clock pulse_cross_clock_dout_valid_1cyc_mclk_i (
.rst (prst), // input
// .rst (prst), // input
.rst (prsts), // input extended to include sensor reset and rst_mmcm
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (dout_valid && !dout_valid_d_pclk), // input
......@@ -665,7 +671,8 @@ module sensor_channel#(
);
pulse_cross_clock pulse_cross_clock_last_in_line_1cyc_mclk_i (
.rst (prst), // input
// .rst (prst), // input
.rst (prsts), // input extended to include sensor reset and rst_mmcm
.src_clk (pclk), // input
.dst_clk (mclk), // input
.in_pulse (last_in_line && !last_in_line_d_pclk), // input
......@@ -739,6 +746,7 @@ module sensor_channel#(
) sens_10398_i (
.pclk (pclk), // input
.prst (prst), // input
.prsts (prsts), // output
.mclk (mclk), // input
.mrst (mrst), // input
.cmd_ad (cmd_ad), // input[7:0]
......@@ -822,6 +830,7 @@ module sensor_channel#(
.pclk (pclk), // input
.mclk_rst (mrst), // input
.prst (prst), // input
.prsts (prsts), // output
.irst (irst), // output
.ipclk (ipclk), // output
.ipclk2x (), // ipclk2x), // output
......@@ -856,7 +865,9 @@ module sensor_channel#(
// .rst (rst), // input
.iclk (ipclk), // input
.pclk (pclk), // input
.prst (prst), // input
// .prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.irst (irst), // input
.pxd_in (pxd_to_fifo), // input[11:0]
.vact (vact_to_fifo), // input
......@@ -881,7 +892,8 @@ module sensor_channel#(
.pclk (pclk), // input
.mclk (mclk), // input
.mrst (mrst), // input
.prst (prst), // input
// .prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.en (en_pclk), // input @pclk
.sof_in (sof), // input
.eof_in (eof), // input
......@@ -925,7 +937,8 @@ module sensor_channel#(
.SENS_LENS_A_WIDTH (19),
.SENS_LENS_B_WIDTH (21)
) lens_flat393_i (
.prst (prst), // input
// .prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -963,7 +976,8 @@ module sensor_channel#(
// .rst (rst), // input
.pclk (pclk), // input
.mrst (mrst), // input
.prst (prst), // input
// .prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pxd_in (gamma_pxd_in), // input[15:0]
.hact_in (gamma_hact_in), // input
.sof_in (gamma_sof_in), // input
......@@ -994,7 +1008,8 @@ module sensor_channel#(
) sens_histogram_i (
// .rst (rst), // input
.mrst (mrst), // input
.prst (prst), // input
// .prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.pclk2x (pclk2x), // input
.sof (gamma_sof_out), // input
......@@ -1047,7 +1062,8 @@ module sensor_channel#(
) sens_histogram_i (
// .rst (rst), // input
.mrst (mrst), // input
.prst (prst), // input
// .prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.pclk2x (pclk2x), // input
.sof (gamma_sof_out), // input
......@@ -1100,7 +1116,8 @@ module sensor_channel#(
) sens_histogram_i (
// .rst (rst), // input
.mrst (mrst), // input
.prst (prst), // input
// .prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.pclk2x (pclk2x), // input
.sof (gamma_sof_out), // input
......@@ -1152,7 +1169,8 @@ module sensor_channel#(
) sens_histogram_i (
// .rst (rst), // input
.mrst (mrst), // input
.prst (prst), // input
// .prst (prst), // input
.prst (prsts), // input extended to include sensor reset and rst_mmcm
.pclk (pclk), // input
.pclk2x (pclk2x), // input
.sof (gamma_sof_out), // input
......
sensor/sensors393.v
View file @ 2b1975c3
......@@ -225,7 +225,7 @@ module sensors393 #(
parameter PXD_CLK_DIV_BITS = 4,
`endif
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
// parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
// parameters for the sensor-synchronous clock PLL
......@@ -560,7 +560,7 @@ module sensors393 #(
.PXD_CLK_DIV_BITS (PXD_CLK_DIV_BITS),
`endif
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
// .SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
......
simulation_modules/par12_hispi_psp4l.v
View file @ 2b1975c3
......@@ -21,6 +21,7 @@
`timescale 1ns/1ps
module par12_hispi_psp4l#(
parameter FULL_HEIGHT = 0, // number of lines in a frame. If 0 - wait to the VACT end, if > 0 - output immediately
parameter CLOCK_MPY = 10,
parameter CLOCK_DIV = 3,
parameter LANE0_DLY = 1.3,
......@@ -49,6 +50,7 @@ module par12_hispi_psp4l#(
localparam [3:0] SYNC_EOL = 6;
// localparam SYNC_EMBED = 4;
integer lines_left; // number of lines left in a frame
integer pre_lines; // Number of lines left with "embedded" (not image) data
reg [ 1:0] lane_pcntr; // count input pixels to extend hact to 4*n if needed
wire hact = hact_in || (|lane_pcntr);
......@@ -61,10 +63,18 @@ module par12_hispi_psp4l#(
reg next_sof;
reg next_line_pclk; // triggers serial output of a line (generated at SOL and EOF, wait full line)
reg next_frame_pclk; // start of a new frame on input
wire pre_fifo_we_eof_w = vact_d && !vact;
wire pre_fifo_we_sof_sol_w = vact_d && hact && !hact_d;
wire pre_fifo_we_eof_w = (FULL_HEIGHT > 0) ? (next_line_pclk && (lines_left == 0)) : (vact_d && !vact);
// wire pre_fifo_we_sof_sol_w = vact_d && ((FULL_HEIGHT > 0) ? ((next_sof && hact && !hact_d) || (hact_d && ! hact && (lines_left > 1)))
wire pre_fifo_we_sof_sol_w = vact_d && ((FULL_HEIGHT > 0) ? ((next_sof && hact && !hact_d) || (next_line_pclk && (lines_left != 0)))
: (hact && !hact_d));
wire pre_fifo_we_data_w = vact_d && hact_d && (lane_pcntr == 0);
wire pre_fifo_we_w = pre_fifo_we_eof_w || pre_fifo_we_sof_sol_w || pre_fifo_we_data_w;
always @(posedge pclk) begin
if (!vact) lines_left <= FULL_HEIGHT;
else if (hact_d && ! hact) lines_left <= lines_left - 1;
end
always @(posedge pclk) begin
vact_d <= vact;
......@@ -86,7 +96,7 @@ module par12_hispi_psp4l#(
else if (hact_d) next_sof <= 0;
if (!vact_d) next_line_pclk <= 0;
else next_line_pclk <= !vact || (hact && !hact_d && !next_sof);
else next_line_pclk <= (FULL_HEIGHT >0)? (hact_d && !hact): (!vact || (hact && !hact_d && !next_sof));
next_frame_pclk <= vact_d && hact && !hact_d && next_sof;
......@@ -123,23 +133,7 @@ module par12_hispi_psp4l#(
.en(1'b1), // input
.clk_out(oclk) // output
);
/*
simul_clk_mult #(
.MULTIPLIER(CLOCK_MPY)
) simul_clk_mult_i (
.clk_in (pclk), // input
.en (1'b1), // input
.clk_out (int_clk) // output reg
);
sim_clk_div #(
.DIVISOR (CLOCK_DIV)
) sim_clk_div_i (
.clk_in (int_clk), // input
.en (1'b1), // input
.clk_out (oclk) // output
);
*/
pulse_cross_clock #(
.EXTRA_DLY(0)
) pulse_cross_clock_sof_sol_i (
......@@ -176,7 +170,6 @@ module par12_hispi_psp4l#(
wire sof_sol_sent;
reg [1:0] lines_available; // number of lines ready in FIFO
wire line_available = |lines_available;
generate
genvar i;
for (i=0; i < 4; i=i+1) begin: cmprs_channel_block
......
x393.v
View file @ 2b1975c3
......@@ -1090,6 +1090,7 @@ assign axi_grst = axi_rst_pre;
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE),
.BUFFER_DEPTH32 (BUFFER_DEPTH32),
.RSEL (RSEL),
.WSEL (WSEL)
......@@ -1557,7 +1558,7 @@ assign axi_grst = axi_rst_pre;
.PXD_CLK_DIV_BITS (PXD_CLK_DIV_BITS),
`endif
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
// .SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKIN_PERIOD_SENSOR (CLKIN_PERIOD_SENSOR),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
......
x393_testbench02.tf
View file @ 2b1975c3
......@@ -2492,7 +2492,8 @@ task write_block_scanline_chn; // SuppressThisWarning VEditor : may be unused
end
endtask
// x393_mcntrl (no class)
function [11:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not used
function [12:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not used
input skip_too_late;
input disable_need;
input repetitive;
input single;
......@@ -2505,7 +2506,7 @@ function [11:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not us
input enable; // enable requests from this channel ( 0 will let current to finish, but not raise want/need)
input chn_reset; // immediately reset al;l the internal circuitry
reg [11:0] rslt;
reg [12:0] rslt;
begin
rslt = 0;
rslt[MCONTR_LINTILE_EN] = ~chn_reset;
......@@ -2518,12 +2519,14 @@ function [11:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not us
rslt[MCONTR_LINTILE_SINGLE] = single;
rslt[MCONTR_LINTILE_REPEAT] = repetitive;
rslt[MCONTR_LINTILE_DIS_NEED] = disable_need;
rslt[MCONTR_LINTILE_SKIP_LATE] = skip_too_late;
// func_encode_mode_tiled={byte32,keep_open,extra_pages,write_mem,enable,~chn_reset};
func_encode_mode_tiled = rslt;
end
endfunction
// x393_mcntrl (no class)
function [11:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not used
function [12:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not used
input skip_too_late;
input disable_need;
input repetitive;
input single;
......@@ -2534,7 +2537,7 @@ function [11:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not
input enable; // enable requests from this channel ( 0 will let current to finish, but not raise want/need)
input chn_reset; // immediately reset al;l the internal circuitry
reg [11:0] rslt;
reg [12:0] rslt;
begin
rslt = 0;
rslt[MCONTR_LINTILE_EN] = ~chn_reset;
......@@ -2545,6 +2548,8 @@ function [11:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not
rslt[MCONTR_LINTILE_SINGLE] = single;
rslt[MCONTR_LINTILE_REPEAT] = repetitive;
rslt[MCONTR_LINTILE_DIS_NEED] = disable_need;
rslt[MCONTR_LINTILE_SKIP_LATE] = skip_too_late;
// func_encode_mode_scanline={extra_pages,write_mem,enable,~chn_reset};
func_encode_mode_scanline = rslt;
end
......@@ -3077,6 +3082,7 @@ task setup_sensor_memory;
begin
base_addr = MCONTR_SENS_BASE + MCONTR_SENS_INC * num_sensor;
mode= func_encode_mode_scanline(
1, // skip_too_late
0, // disable_need
1, // repetitive,
0, // single,
......@@ -3122,6 +3128,7 @@ task setup_compressor_memory;
base_addr = MCONTR_CMPRS_BASE + MCONTR_CMPRS_INC * num_sensor;
mode= func_encode_mode_tiled(
1'b0, // skip too late
disable_need,
1, // repetitive,
0, // single,
......
x393_testbench03.sav
View file @ 2b1975c3
This diff is collapsed.
x393_testbench03.tf
View file @ 2b1975c3
......@@ -26,6 +26,7 @@
`undef WAIT_MRS
`define SET_PER_PIN_DELAYS 1 // set individual (including per-DQ pin delays)
`define READBACK_DELAYS 1
//`define TEST_MEMBRIDGE 1
`define PS_PIO_WAIT_COMPLETE 0 // wait until PS PIO module finished transaction before starting a new one
// Disabled already passed test to speedup simulation
//`define TEST_WRITE_LEVELLING 1
......@@ -111,10 +112,17 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb
parameter CPU_PER=10.4;
parameter TRIG_PERIOD = 6000 ;
parameter HBLANK= 52; // 12; /// 52; //*********************
parameter WOI_HEIGHT= 32;
`ifdef HISPI
parameter HBLANK= 90; // 12; /// 52; //*********************
parameter BLANK_ROWS_BEFORE= 9; // 3; //8; ///2+2 - a little faster than compressor
parameter BLANK_ROWS_AFTER= 1; //8;
`else
parameter HBLANK= 12; // 52; // 12; /// 52; //*********************
parameter BLANK_ROWS_BEFORE= 1; //8; ///2+2 - a little faster than compressor
parameter BLANK_ROWS_AFTER= 1; //8;
`endif
parameter WOI_HEIGHT= 32;
parameter TRIG_LINES= 8;
parameter VBLANK= 2; /// 2 lines //SuppressThisWarning Veditor UNUSED
parameter CYCLES_PER_PIXEL= 3; /// 2 for JP4, 3 for JPEG
......@@ -246,6 +254,7 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb
localparam PIX_CLK_MULT = 1; // scale clock from FPGA to sensor pixel clock
`endif
`ifdef HISPI
localparam HISPI_FULL_HEIGHT = FULL_HEIGHT; // >0 - count lines, ==0 - wait for the end of VACT
localparam HISPI_CLK_DIV = 3; // from pixel clock to serial output pixel rate TODO: Set real ones, adjsut sensor clock too
localparam HISPI_CLK_MULT = 10; // from pixel clock to serial output pixel rate TODO: Set real ones, adjsut sensor clock too
......@@ -1232,6 +1241,8 @@ assign #10 gpio_pins[9] = gpio_pins[8];
compressor_run (2, 2); // run single
compressor_run (3, 2); // run single
*/
`ifdef TEST_MEMBRIDGE
TEST_TITLE = "MEMBRIDGE_READ # 1";
$display("===================== TEST_%s =========================",TEST_TITLE);
TEST_TITLE = "MEMBRIDGE READ #1";
......@@ -1245,6 +1256,7 @@ assign #10 gpio_pins[9] = gpio_pins[8];
setup_sensor_membridge (0, // for sensor 0
1) ; // disable_need
`endif
`ifdef DEBUG_RING
TEST_TITLE = "READING DEBUG DATA";
......@@ -2091,6 +2103,7 @@ simul_axi_hp_wr #(
// Testing parallel12 -> HiSPi simulation converter
`ifdef HISPI
par12_hispi_psp4l #(
.FULL_HEIGHT (HISPI_FULL_HEIGHT),
.CLOCK_MPY (HISPI_CLK_MULT),
.CLOCK_DIV (HISPI_CLK_DIV),
.LANE0_DLY (1.3),
......@@ -2114,6 +2127,7 @@ simul_axi_hp_wr #(
);
par12_hispi_psp4l #(
.FULL_HEIGHT (HISPI_FULL_HEIGHT),
.CLOCK_MPY (HISPI_CLK_MULT),
.CLOCK_DIV (HISPI_CLK_DIV),
.LANE0_DLY (1.3),
......@@ -2137,6 +2151,7 @@ simul_axi_hp_wr #(
);
par12_hispi_psp4l #(
.FULL_HEIGHT (HISPI_FULL_HEIGHT),
.CLOCK_MPY (HISPI_CLK_MULT),
.CLOCK_DIV (HISPI_CLK_DIV),
.LANE0_DLY (1.3),
......@@ -2160,6 +2175,7 @@ simul_axi_hp_wr #(
);
par12_hispi_psp4l #(
.FULL_HEIGHT (HISPI_FULL_HEIGHT),
.CLOCK_MPY (HISPI_CLK_MULT),
.CLOCK_DIV (HISPI_CLK_DIV),
.LANE0_DLY (1.3),
......@@ -2492,7 +2508,8 @@ task write_block_scanline_chn; // SuppressThisWarning VEditor : may be unused
end
endtask
// x393_mcntrl (no class)
function [11:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not used
function [12:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not used
input skip_too_late;
input disable_need;
input repetitive;
input single;
......@@ -2505,7 +2522,7 @@ function [11:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not us
input enable; // enable requests from this channel ( 0 will let current to finish, but not raise want/need)
input chn_reset; // immediately reset al;l the internal circuitry
reg [11:0] rslt;
reg [12:0] rslt;
begin
rslt = 0;
rslt[MCONTR_LINTILE_EN] = ~chn_reset;
......@@ -2518,12 +2535,15 @@ function [11:0] func_encode_mode_tiled; // SuppressThisWarning VEditor - not us
rslt[MCONTR_LINTILE_SINGLE] = single;
rslt[MCONTR_LINTILE_REPEAT] = repetitive;
rslt[MCONTR_LINTILE_DIS_NEED] = disable_need;
rslt[MCONTR_LINTILE_SKIP_LATE] = skip_too_late;
// func_encode_mode_tiled={byte32,keep_open,extra_pages,write_mem,enable,~chn_reset};
func_encode_mode_tiled = rslt;
end
endfunction
// x393_mcntrl (no class)
function [11:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not used
function [12:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not used
input skip_too_late;
input disable_need;
input repetitive;
input single;
......@@ -2534,7 +2554,7 @@ function [11:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not
input enable; // enable requests from this channel ( 0 will let current to finish, but not raise want/need)
input chn_reset; // immediately reset al;l the internal circuitry
reg [11:0] rslt;
reg [12:0] rslt;
begin
rslt = 0;
rslt[MCONTR_LINTILE_EN] = ~chn_reset;
......@@ -2545,6 +2565,7 @@ function [11:0] func_encode_mode_scanline; // SuppressThisWarning VEditor - not
rslt[MCONTR_LINTILE_SINGLE] = single;
rslt[MCONTR_LINTILE_REPEAT] = repetitive;
rslt[MCONTR_LINTILE_DIS_NEED] = disable_need;
rslt[MCONTR_LINTILE_SKIP_LATE] = skip_too_late;
// func_encode_mode_scanline={extra_pages,write_mem,enable,~chn_reset};
func_encode_mode_scanline = rslt;
end
......@@ -3077,6 +3098,7 @@ task setup_sensor_memory;
begin
base_addr = MCONTR_SENS_BASE + MCONTR_SENS_INC * num_sensor;
mode= func_encode_mode_scanline(
1, // skip_too_late
0, // disable_need
1, // repetitive,
0, // single,
......@@ -3122,6 +3144,7 @@ task setup_compressor_memory;
base_addr = MCONTR_CMPRS_BASE + MCONTR_CMPRS_INC * num_sensor;
mode= func_encode_mode_tiled(
1'b0, // skip too late
disable_need,
1, // repetitive,
0, // single,
......
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