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Commit 2b1975c3 authored by Andrey Filippov's avatar Andrey Filippov
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implemented optional skipping/fast forward of the data blocks when buffer is... 

implemented optional skipping/fast forward of the data blocks when buffer is over/underrun during memory access
parent 75f18826
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Showing with 1069 additions and 132 deletions
includes/tasks_tests_memory.vh
View file @ 2b1975c3
......@@ -149,6 +149,7 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
(window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0},
start64, lo_addr64, size64, $time);
mode= func_encode_mode_scanline(
1'b0, // skip_too_late
disable_need,
repetitive,
single,
......@@ -250,6 +251,7 @@ task test_scanline_write; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_scanline(
1'b0, // skip_too_late
disable_need,
repetitive,
single,
......@@ -391,6 +393,7 @@ task test_scanline_read; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_scanline(
1'b0, // skip_too_late
disable_need,
repetitive,
single,
......@@ -505,6 +508,7 @@ task test_tiled_write; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_tiled(
1'b0, // skip_too_late
disable_need,
repetitive,
single,
......@@ -637,6 +641,7 @@ task test_tiled_read; // SuppressThisWarning VEditor - may be unused
end
endcase
mode= func_encode_mode_tiled(
1'b0, // skip_too_late
disable_need,
repetitive,
single,
......
includes/x393_parameters.vh
View file @ 2b1975c3
......@@ -273,6 +273,7 @@
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
// Channel test module parameters
parameter MCNTRL_TEST01_ADDR= 'h0f0,
......@@ -526,7 +527,7 @@
//`endif
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
// parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
// parameters for the sensor-synchronous clock PLL
......
memctrl/mcntrl393.v
View file @ 2b1975c3
......@@ -241,7 +241,8 @@ module mcntrl393 #(
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11 // disable 'need' request
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12 // skip actual R/W operation when it is too late, advance pointers
) (
input rst_in,
......@@ -411,7 +412,8 @@ module mcntrl393 #(
wire want_rq0;
wire need_rq0;
wire channel_pgm_en0;
wire channel_pgm_en0;
wire reject0 = 1'b0;
wire [9:0] seq_data0; // only 10 bits used
// wire seq_wr0; // not used
wire seq_set0;
......@@ -428,6 +430,7 @@ module mcntrl393 #(
wire want_rq1;
wire need_rq1;
wire channel_pgm_en1;
wire reject1; // = 1'b0;
wire seq_done1;
// routed outside to membredge module
/*
......@@ -441,6 +444,7 @@ module mcntrl393 #(
wire want_rq2;
wire need_rq2;
wire channel_pgm_en2;
wire reject2 = 1'b0;
wire seq_done2;
wire buf_wr_chn2;
wire buf_wpage_nxt_chn2;
......@@ -452,6 +456,7 @@ module mcntrl393 #(
wire want_rq3;
wire need_rq3;
wire channel_pgm_en3;
wire reject3; // = 1'b0;
wire seq_done3;
wire buf_wr_chn3;
wire buf_wpage_nxt_chn3;
......@@ -462,7 +467,8 @@ module mcntrl393 #(
wire want_rq4;
wire need_rq4;
wire channel_pgm_en4;
wire channel_pgm_en4;
wire reject4 = 1'b0;
wire seq_done4;
wire buf_wr_chn4;
wire buf_wpage_nxt_chn4;
......@@ -538,6 +544,7 @@ module mcntrl393 #(
wire [3:0] cmprs_need;
wire [3:0] sens_channel_pgm_en;
wire [3:0] sens_reject;
wire [3:0] sens_start_wr;
wire [11:0] sens_bank; // output[2:0]
wire [4*ADDRESS_NUMBER-1:0] sens_row; // output[14:0]
......@@ -547,6 +554,7 @@ module mcntrl393 #(
wire [3:0] sens_seq_done; // input : sequence over
wire [3:0] cmprs_channel_pgm_en;
wire [3:0] cmprs_reject = 4'h0;
wire [3:0] cmprs_start_rd16;
wire [3:0] cmprs_start_rd32;
wire [11:0] cmprs_bank; // output[2:0]
......@@ -1059,7 +1067,8 @@ module mcntrl393 #(
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE)
) mcntrl_linear_wr_sensor_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1078,6 +1087,7 @@ module mcntrl393 #(
.xfer_want (sens_want[i]), // output
.xfer_need (sens_need[i]), // output
.xfer_grant (sens_channel_pgm_en[i]), // input
.xfer_reject (sens_reject[i]), // output
.xfer_start_rd (), // output
.xfer_start_wr (sens_start_wr[i]), // output
.xfer_bank (sens_bank[3 * i +: 3]), // output[2:0]
......@@ -1124,7 +1134,7 @@ module mcntrl393 #(
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
) mcntrl_tiled_rd_compressor_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1196,7 +1206,8 @@ module mcntrl393 #(
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE)
) mcntrl_linear_rw_chn1_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1215,6 +1226,7 @@ module mcntrl393 #(
.xfer_want (want_rq1), // output
.xfer_need (need_rq1), // output
.xfer_grant (channel_pgm_en1), // input
.xfer_reject (reject1), //input
.xfer_start_rd (lin_rw_chn1_start_rd), // output
.xfer_start_wr (lin_rw_chn1_start_wr), // output
.xfer_bank (lin_rw_chn1_bank), // output[2:0]
......@@ -1257,7 +1269,8 @@ module mcntrl393 #(
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_SKIP_LATE (MCONTR_LINTILE_SKIP_LATE)
) mcntrl_linear_rw_chn3_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1276,6 +1289,7 @@ module mcntrl393 #(
.xfer_want (want_rq3), // output
.xfer_need (need_rq3), // output
.xfer_grant (channel_pgm_en3), // input
.xfer_reject (reject3), //input
.xfer_start_rd (lin_rw_chn3_start_rd), // output
.xfer_start_wr (lin_rw_chn3_start_wr), // output
.xfer_bank (lin_rw_chn3_bank), // output[2:0]
......@@ -1389,8 +1403,7 @@ module mcntrl393 #(
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED)
) mcntrl_tiled_rw_chn4_i (
.mrst (mrst), // input
.mclk (mclk), // input
......@@ -1836,6 +1849,7 @@ module mcntrl393 #(
.want_rq0 (want_rq0), // input
.need_rq0 (need_rq0), // input
.channel_pgm_en0 (channel_pgm_en0), // output reg
.reject0 (reject0), // input
.seq_done0 (seq_done0), // output
.page_nxt_chn0 (), //rpage_nxt_chn0), not used
.buf_run0 (buf_run0), // output
......@@ -1850,6 +1864,7 @@ module mcntrl393 #(
.want_rq1 (want_rq1), // input
.need_rq1 (need_rq1), // input
.channel_pgm_en1 (channel_pgm_en1), // output reg
.reject1 (reject1), // input
.seq_done1 (seq_done1), // output
.page_nxt_chn1 (page_ready_chn1), //rpage_nxt_chn0), not used
.buf_run1 (), // output
......@@ -1864,6 +1879,7 @@ module mcntrl393 #(
.want_rq2 (want_rq2), // input
.need_rq2 (need_rq2), // input
.channel_pgm_en2 (channel_pgm_en2), // output reg
.reject2 (reject2), // input
.seq_done2 (seq_done2), // output
.page_nxt_chn2 (page_ready_chn2), //rpage_nxt_chn0), not used
.buf_run2 (), // output //buf_run2),
......@@ -1878,6 +1894,7 @@ module mcntrl393 #(
.want_rq3 (want_rq3), // input
.need_rq3 (need_rq3), // input
.channel_pgm_en3 (channel_pgm_en3), // output reg
.reject3 (reject3), // input
.seq_done3 (seq_done3), // output
.page_nxt_chn3 (page_ready_chn3), //rpage_nxt_chn0), not used
.buf_run3 (), // output//buf_run3),
......@@ -1892,6 +1909,7 @@ module mcntrl393 #(
.want_rq4 (want_rq4), // input
.need_rq4 (need_rq4), // input
.channel_pgm_en4 (channel_pgm_en4), // output reg
.reject4 (reject4), // input
.seq_done4 (seq_done4), // output
.page_nxt_chn4 (page_ready_chn4), //rpage_nxt_chn0), not used
.buf_run4 (), // output //buf_run4),
......@@ -1906,6 +1924,7 @@ module mcntrl393 #(
.want_rq8 (sens_want[0]), // input
.need_rq8 (sens_need[0]), // input
.channel_pgm_en8 (sens_channel_pgm_en[0]), // output reg
.reject8 (sens_reject[0]), // input
.seq_done8 (sens_seq_done[0]), // output
.page_nxt_chn8 (), // output ?
.buf_run8 (), // output
......@@ -1916,6 +1935,7 @@ module mcntrl393 #(
.want_rq9 (sens_want[1]), // input
.need_rq9 (sens_need[1]), // input
.channel_pgm_en9 (sens_channel_pgm_en[1]), // output reg
.reject9 (sens_reject[1]), // input
.seq_done9 (sens_seq_done[1]), // output
.page_nxt_chn9 (), // output ?
.buf_run9 (), // output
......@@ -1926,6 +1946,7 @@ module mcntrl393 #(
.want_rq10 (sens_want[2]), // input
.need_rq10 (sens_need[2]), // input
.channel_pgm_en10 (sens_channel_pgm_en[2]), // output reg
.reject10 (sens_reject[2]), // input
.seq_done10 (sens_seq_done[2]), // output
.page_nxt_chn10 (), // output
.buf_run10 (), // output
......@@ -1936,6 +1957,7 @@ module mcntrl393 #(
.want_rq11 (sens_want[3]), // input
.need_rq11 (sens_need[3]), // input
.channel_pgm_en11 (sens_channel_pgm_en[3]), // output reg
.reject11 (sens_reject[3]), // input
.seq_done11 (sens_seq_done[3]), // output
.page_nxt_chn11 (), // output
.buf_run11 (), // output
......@@ -1946,6 +1968,7 @@ module mcntrl393 #(
.want_rq12 (cmprs_want[0]), // input
.need_rq12 (cmprs_need[0]), // input
.channel_pgm_en12 (cmprs_channel_pgm_en[0]), // output reg
.reject12 (cmprs_reject[0]), // input
.seq_done12 (cmprs_seq_done[0]), // output
.page_nxt_chn12 (cmprs_page_ready[0]), // output ???
.buf_run12 (), // output
......@@ -1957,6 +1980,7 @@ module mcntrl393 #(
.want_rq13 (cmprs_want[1]), // input
.need_rq13 (cmprs_need[1]), // input
.channel_pgm_en13 (cmprs_channel_pgm_en[1]), // output reg
.reject13 (cmprs_reject[1]), // input
.seq_done13 (cmprs_seq_done[1]), // output
.page_nxt_chn13 (cmprs_page_ready[1]), // output ???
.buf_run13 (), // output
......@@ -1968,6 +1992,7 @@ module mcntrl393 #(
.want_rq14 (cmprs_want[2]), // input
.need_rq14 (cmprs_need[2]), // input
.channel_pgm_en14 (cmprs_channel_pgm_en[2]), // output reg
.reject14 (cmprs_reject[2]), // input
.seq_done14 (cmprs_seq_done[2]), // output
.page_nxt_chn14 (cmprs_page_ready[2]), // output ???
.buf_run14 (), // output
......@@ -1979,6 +2004,7 @@ module mcntrl393 #(
.want_rq15 (cmprs_want[3]), // input
.need_rq15 (cmprs_need[3]), // input
.channel_pgm_en15 (cmprs_channel_pgm_en[3]), // output reg
.reject15 (cmprs_reject[3]), // input
.seq_done15 (cmprs_seq_done[3]), // output
.page_nxt_chn15 (cmprs_page_ready[3]), // output ???
.buf_run15 (), // output
......
memctrl/mcntrl_linear_rw.v
View file @ 2b1975c3
......@@ -56,8 +56,9 @@ module mcntrl_linear_rw #(
parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11 // disable 'need' request
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12 // skip actual R/W operation when it is too late, advance pointers
)(
input mrst,
input mclk,
......@@ -82,6 +83,7 @@ module mcntrl_linear_rw #(
output xfer_want, // "want" data transfer
output xfer_need, // "need" - really need a transfer (only 1 page/ room for 1 page left in a buffer), want should still be set.
input xfer_grant, // sequencer programming access granted, deassert wait/need
output xfer_reject, // reject granted access (when skipping)
output xfer_start_rd, // initiate a transfer (next cycle after xfer_grant)
output xfer_start_wr, // initiate a transfer (next cycle after xfer_grant)
output [2:0] xfer_bank, // bank address
......@@ -150,6 +152,7 @@ module mcntrl_linear_rw #(
// wire cmd_wrmem; //=MCNTRL_SCANLINE_WRITE_MODE; // 0: read from memory, 1:write to memory
wire [1:0] cmd_extra_pages; // external module needs more than 1 page
wire skip_too_late;
wire disable_need; // do not assert need, only want
wire repeat_frames; // mode bit
wire single_frame_w; // pulse
......@@ -191,7 +194,7 @@ module mcntrl_linear_rw #(
wire msw_zero= !(|cmd_data[31:16]); // MSW all bits are 0 - set carry bit
reg [11:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}
reg [12:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na[2:0],extra_pages[1:0],write_mode,enable,!reset}
reg [NUM_RC_BURST_BITS-1:0] start_range_addr; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
reg [NUM_RC_BURST_BITS-1:0] frame_size; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
......@@ -233,7 +236,7 @@ module mcntrl_linear_rw #(
// Set parameter registers
always @(posedge mclk) begin
if (mrst) mode_reg <= 0;
else if (set_mode_w) mode_reg <= cmd_data[11:0]; // 4:0]; // [4:0];
else if (set_mode_w) mode_reg <= cmd_data[12:0]; // 4:0]; // [4:0];
if (mrst) single_frame_r <= 0;
else single_frame_r <= single_frame_w;
......@@ -337,19 +340,51 @@ module mcntrl_linear_rw #(
assign cmd_extra_pages = mode_reg[MCONTR_LINTILE_EXTRAPG+:MCONTR_LINTILE_EXTRAPG_BITS]; // external module needs more than 1 page
assign repeat_frames= mode_reg[MCONTR_LINTILE_REPEAT];
assign disable_need = mode_reg[MCONTR_LINTILE_DIS_NEED];
assign skip_too_late = mode_reg[MCONTR_LINTILE_SKIP_LATE];
assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit?
assign pgm_param_w= cmd_we;
localparam [COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] EXTRA_BITS=0;
assign remainder_in_xfer = {EXTRA_BITS, lim_by_xfer}-mem_page_left;
integer i;
wire xfer_limited_by_mem_page;
wire xfer_limited_by_mem_page= mem_page_left < {EXTRA_BITS,lim_by_xfer};
reg xfer_limited_by_mem_page_r;
assign xfer_limited_by_mem_page= mem_page_left < {EXTRA_BITS,lim_by_xfer};
// skipping pages that did not make it
// reg skip_tail; // skip end of frame if the next frame started (TBD)
// Now skip if write and >=4 or read and >=5 (read starts with 4 and may end with 4)
// Also if the next page signal is used by the source/dest of data, it should use reject pulse to advance external
// page counter
wire start_skip_w = skip_too_late && want_r && (page_cntr >= 4) && !xfer_grant && (cmd_wrmem || page_cntr[0]); //&& busy_r && skip_run;
reg start_skip_r;
reg skip_run = 0; // run "skip" - advance addresses, but no actual read/write
reg xfer_reject_r;
assign xfer_reject = xfer_reject_r;
always @(posedge mclk) begin // Handling skip/reject
if (mrst) xfer_reject_r <= 0;
else xfer_reject_r <= xfer_grant && !chn_rst && skip_run;
if (mrst) xfer_start_r <= 0;
else xfer_start_r <= {xfer_start_r[1:0], (xfer_grant & ~chn_rst & ~skip_run) | start_skip_r};
if (mrst) xfer_start_rd_r <= 0;
else xfer_start_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && !skip_run;
if (mrst) xfer_start_wr_r <= 0;
else xfer_start_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && !skip_run;
if (mrst || recalc_r[PAR_MOD_LATENCY-1]) skip_run <= 0;
else if (start_skip_w) skip_run <= 1;
if (mrst) start_skip_r <= 0;
else start_skip_r <= start_skip_w;
end
/// Recalcualting just after starting request - preparing for the next one. Also happens after parameter change.
/// Should dpepend only on the parameters updated separately (curr_x, curr_y)
/// Should dppend only on the parameters updated separately (curr_x, curr_y)
always @(posedge mclk) begin // TODO: Match latencies (is it needed?) Reduce consumption by CE?
if (recalc_r[0]) begin // cycle 1
frame_x <= curr_x + window_x0;
......@@ -442,14 +477,6 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
else if (chn_rst || frame_start_r[0]) frame_finished_r <= 0;
else if (frame_done_r) frame_finished_r <= 1;
if (mrst) xfer_start_r <= 0;
else xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst};
if (mrst) xfer_start_rd_r <= 0;
else xfer_start_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem;
if (mrst) xfer_start_wr_r <= 0;
else xfer_start_wr_r <= xfer_grant && !chn_rst && cmd_wrmem;
if (mrst || disable_need) need_r <= 0;
else if (chn_rst || xfer_grant) need_r <= 0;
......
memctrl/memctrl16.v
View file @ 2b1975c3
......@@ -168,6 +168,7 @@ module memctrl16 #(
input want_rq0, // both want_rq and need_rq should go inactive after being granted
input need_rq0, // want_rq should be active when need_rq is.
output reg channel_pgm_en0, // channel can program sequence data
input reject0, // reject grant
output seq_done0, // sequencer finished executing sequence for this channel
output page_nxt_chn0,
output buf_run0, // external buffer run (may be used to force page) @posedge mclk
......@@ -189,6 +190,7 @@ module memctrl16 #(
input want_rq1, // both want_rq and need_rq should go inactive after being granted
input need_rq1,
output reg channel_pgm_en1, // channel can program sequence data
input reject1, // reject grant
output seq_done1, // sequencer finished executing sequence for this channel
output page_nxt_chn1,
output buf_run1, // external buffer run (may be used to force page) @posedge mclk
......@@ -210,6 +212,7 @@ module memctrl16 #(
input want_rq2, // both want_rq and need_rq should go inactive after being granted
input need_rq2,
output reg channel_pgm_en2, // channel can program sequence data
input reject2, // reject grant
output seq_done2, // sequencer finished executing sequence for this channel
output page_nxt_chn2,
output buf_run2, // external buffer run (may be used to force page) @posedge mclk
......@@ -231,6 +234,7 @@ module memctrl16 #(
input want_rq3, // both want_rq and need_rq should go inactive after being granted
input need_rq3,
output reg channel_pgm_en3, // channel can program sequence data
input reject3, // reject grant
output seq_done3, // sequencer finished executing sequence for this channel
output page_nxt_chn3,
output buf_run3, // external buffer run (may be used to force page) @posedge mclk
......@@ -252,6 +256,7 @@ module memctrl16 #(
input want_rq4, // both want_rq and need_rq should go inactive after being granted
input need_rq4,
output reg channel_pgm_en4, // channel can program sequence data
input reject4, // reject grant
output seq_done4, // sequencer finished executing sequence for this channel
output page_nxt_chn4,
output buf_run4, // external buffer run (may be used to force page) @posedge mclk
......@@ -273,6 +278,7 @@ module memctrl16 #(
input want_rq5, // both want_rq and need_rq should go inactive after being granted
input need_rq5,
output reg channel_pgm_en5, // channel can program sequence data
input reject5, // reject grant
output seq_done5, // sequencer finished executing sequence for this channel
output page_nxt_chn5,
output buf_run5, // external buffer run (may be used to force page) @posedge mclk
......@@ -294,6 +300,7 @@ module memctrl16 #(
input want_rq6, // both want_rq and need_rq should go inactive after being granted
input need_rq6,
output reg channel_pgm_en6, // channel can program sequence data
input reject6, // reject grant
output seq_done6, // sequencer finished executing sequence for this channel
output page_nxt_chn6,
output buf_run6, // external buffer run (may be used to force page) @posedge mclk
......@@ -315,6 +322,7 @@ module memctrl16 #(
input want_rq7, // both want_rq and need_rq should go inactive after being granted
input need_rq7,
output reg channel_pgm_en7, // channel can program sequence data
input reject7, // reject grant
output seq_done7, // sequencer finished executing sequence for this channel
output page_nxt_chn7,
output buf_run7, // external buffer run (may be used to force page) @posedge mclk
......@@ -336,6 +344,7 @@ module memctrl16 #(
input want_rq8, // both want_rq and need_rq should go inactive after being granted
input need_rq8,
output reg channel_pgm_en8, // channel can program sequence data
input reject8, // reject grant
output seq_done8, // sequencer finished executing sequence for this channel
output page_nxt_chn8,
output buf_run8, // external buffer run (may be used to force page) @posedge mclk
......@@ -357,6 +366,7 @@ module memctrl16 #(
input want_rq9, // both want_rq and need_rq should go inactive after being granted
input need_rq9,
output reg channel_pgm_en9, // channel can program sequence data
input reject9, // reject grant
output seq_done9, // sequencer finished executing sequence for this channel
output page_nxt_chn9,
output buf_run9, // external buffer run (may be used to force page) @posedge mclk
......@@ -378,6 +388,7 @@ module memctrl16 #(
input want_rq10, // both want_rq and need_rq should go inactive after being granted
input need_rq10,
output reg channel_pgm_en10, // channel can program sequence data
input reject10, // reject grant
output seq_done10, // sequencer finished executing sequence for this channel
output page_nxt_chn10,
output buf_run10, // external buffer run (may be used to force page) @posedge mclk
......@@ -399,6 +410,7 @@ module memctrl16 #(
input want_rq11, // both want_rq and need_rq should go inactive after being granted
input need_rq11,
output reg channel_pgm_en11, // channel can program sequence data
input reject11, // reject grant
output seq_done11, // sequencer finished executing sequence for this channel
output page_nxt_chn11,
output buf_run11, // external buffer run (may be used to force page) @posedge mclk
......@@ -420,6 +432,7 @@ module memctrl16 #(
input want_rq12, // both want_rq and need_rq should go inactive after being granted
input need_rq12,
output reg channel_pgm_en12, // channel can program sequence data
input reject12, // reject grant
output seq_done12, // sequencer finished executing sequence for this channel
output page_nxt_chn12,
output buf_run12, // external buffer run (may be used to force page) @posedge mclk
......@@ -441,6 +454,7 @@ module memctrl16 #(
input want_rq13, // both want_rq and need_rq should go inactive after being granted
input need_rq13,
output reg channel_pgm_en13, // channel can program sequence data
input reject13, // reject grant
output seq_done13, // sequencer finished executing sequence for this channel
output page_nxt_chn13,
output buf_run13, // external buffer run (may be used to force page) @posedge mclk
......@@ -462,6 +476,7 @@ module memctrl16 #(
input want_rq14, // both want_rq and need_rq should go inactive after being granted
input need_rq14,
output reg channel_pgm_en14, // channel can program sequence data
input reject14, // reject grant
output seq_done14, // sequencer finished executing sequence for this channel
output page_nxt_chn14,
output buf_run14, // external buffer run (may be used to force page) @posedge mclk
......@@ -483,6 +498,7 @@ module memctrl16 #(
input want_rq15, // both want_rq and need_rq should go inactive after being granted
input need_rq15,
output reg channel_pgm_en15, // channel can program sequence data
input reject15, // reject grant
output seq_done15, // sequencer finished executing sequence for this channel
output page_nxt_chn15,
output buf_run15, // external buffer run (may be used to force page) @posedge mclk
......@@ -529,7 +545,7 @@ module memctrl16 #(
// temporary debug data
,output [11:0] tmp_debug // add some signals generated here?
);
wire reject; // OR-ed reject from all channels
wire ext_buf_rd;
wire ext_buf_rpage_nxt;
wire ext_buf_page_nxt;
......@@ -779,11 +795,14 @@ assign pre_run_seq_w= mcontr_enabled && !sequencer_run_busy && !cmd_seq_run && (
assign pre_run_chn_w= pre_run_seq_w && !sel_refresh_w;
assign en_schedul= mcontr_enabled && !cmd_seq_fill && !cmd_seq_full;
reg reject_r;
// sequential logic for commands transfer to the sequencer
always @ (posedge mclk) begin
if (mrst) grant_r <= 0;
else grant_r <= grant;
if (mrst) reject_r <= 0;
else reject_r <= reject;
if (mrst) cmd_seq_set <= 0;
else if (grant_r) cmd_seq_set <= 0;
......@@ -794,9 +813,9 @@ always @ (posedge mclk) begin
//TODO: Modify,cmd_seq_fill was initially used to see if any sequaence data was written (or PS is used), now it is cmd_seq_set
if (mrst) cmd_seq_fill <= 0;
else if (!mcontr_enabled || seq_set || cmd_seq_full ) cmd_seq_fill <= 0;
else if (grant) cmd_seq_fill <= 1;
if (mrst) cmd_seq_fill <= 0;
else if (!mcontr_enabled || seq_set || cmd_seq_full || reject_r) cmd_seq_fill <= 0;
else if (grant) cmd_seq_fill <= 1;
if (mrst) cmd_seq_full <= 0;
else if (!mcontr_enabled || pre_run_chn_w ) cmd_seq_full <= 0;
......@@ -1457,5 +1476,58 @@ assign need_rq[15:0]= {need_rq15,need_rq14,need_rq13,need_rq12,need_rq11,need_
always @ (posedge mclk) channel_pgm_en15 <= grant && (grant_chn == 15);
`endif
// input reject0, // reject grant
assign reject = 1'b0
`ifdef def_enable_mem_chn0
|| reject0
`endif
`ifdef def_enable_mem_chn1
|| reject1
`endif
`ifdef def_enable_mem_chn2
|| reject2
`endif
`ifdef def_enable_mem_chn3
|| reject3
`endif
`ifdef def_enable_mem_chn4
|| reject4
`endif
`ifdef def_enable_mem_chn5
|| reject5
`endif
`ifdef def_enable_mem_chn6
|| reject6
`endif
`ifdef def_enable_mem_chn7
|| reject7
`endif
`ifdef def_enable_mem_chn8
|| reject8
`endif
`ifdef def_enable_mem_chn9
|| reject9
`endif
`ifdef def_enable_mem_chn10
|| reject10
`endif
`ifdef def_enable_mem_chn11
|| reject11
`endif
`ifdef def_enable_mem_chn12
|| reject12
`endif
`ifdef def_enable_mem_chn13
|| reject13
`endif
`ifdef def_enable_mem_chn14
|| reject14
`endif
`ifdef def_enable_mem_chn15
|| reject15
`endif
;
endmodule
sensor/sens_10398.v
View file @ 2b1975c3
......@@ -97,6 +97,7 @@ module sens_10398 #(
)(
input pclk, // global clock input, pixel rate (220MHz for MT9F002)
input prst,
output prsts, // @pclk - includes sensor reset and sensor PLL reset
// delay control inputs
input mclk,
input mrst,
......@@ -189,7 +190,8 @@ module sens_10398 #(
assign iaro = trigger_mode? ~trig : iaro_soft;
assign prsts = prst_with_sens_mrst[0]; // @pclk - includes sensor reset and sensor PLL reset
always @(posedge mclk) begin
if (mrst) data_r <= 0;
......@@ -265,8 +267,8 @@ module sens_10398 #(
if (async_prst_with_sens_mrst) prst_with_sens_mrst <= 2'h3;
else if (prst) prst_with_sens_mrst <= 2'h3;
else prst_with_sens_mrst <= prst_with_sens_mrst >> 1;
end
cmd_deser #(
.ADDR (SENSIO_ADDR),
.ADDR_MASK (SENSIO_ADDR_MASK),
......@@ -331,7 +333,7 @@ module sens_10398 #(
.HISPI_IOSTANDARD (HISPI_IOSTANDARD)
) sens_hispi12l4_i (
.pclk (pclk), // input
.prst (prst_with_sens_mrst[0]), //prst), // input
.prst (prsts), //prst), // input
.sns_dp (sns_dp[3:0]), // input[3:0]
.sns_dn (sns_dn[3:0]), // input[3:0]
.sns_clkp (sns_clkp), // input
......
sensor/sens_hispi12l4.v
View file @ 2b1975c3
......@@ -222,7 +222,8 @@ module sens_hispi12l4#(
end
always @(posedge pclk) begin
vact_pclk_strt <= {vact_pclk_strt[0],vact_ipclk};
if (prst || !vact_ipclk) vact_pclk_strt <= 0;
else vact_pclk_strt <= {vact_pclk_strt[0], 1'b1};
rd_run_d <= rd_run;
......@@ -275,8 +276,8 @@ module sens_hispi12l4#(
.rst (1'b0), // input
// .dly (4'h2), // input[3:0]
// .dly (4'h3), // input[3:0]
// .dly (4'h1), // input[3:0]
.dly (4'h2), // input[3:0]
.dly (4'h1), // input[3:0]
// .dly (4'h2), // input[3:0]
.din (sol_pclk), // input[0:0]
.dout (hact_on) // output[0:0]
);
......@@ -288,8 +289,8 @@ module sens_hispi12l4#(
.rst (1'b0), // input
// .dly (4'h2), // input[3:0]
// .dly (4'h0), // input[3:0]
// .dly (4'h1), // input[3:0]
.dly (4'h2), // input[3:0]
.dly (4'h1), // input[3:0]
// .dly (4'h2), // input[3:0]
.din (fifo_re[HISPI_NUMLANES - 1]), // input[0:0]
.dout (hact_off) // output[0:0]
);
......@@ -300,8 +301,8 @@ module sens_hispi12l4#(
.clk (pclk), // input
.rst (1'b0), // input
// .dly (4'h2), // input[3:0]
// .dly (4'h0), // input[3:0]
.dly (4'h1), // input[3:0]
.dly (4'h0), // input[3:0]
// .dly (4'h1), // input[3:0]
.din (pxd_out_pre), // input[0:0]
.dout (pxd_out) // output[0:0]
);
......
sensor/sens_parallel12.v
View file @ 2b1975c3
......@@ -83,6 +83,7 @@ module sens_parallel12 #(
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
input mclk_rst,
input prst,
output prsts, // @pclk - includes sensor reset and sensor PLL reset
output irst,
output ipclk, // re-generated sensor output clock (regional clock to drive external fifo)
......@@ -203,6 +204,12 @@ module sens_parallel12 #(
reg hact_ext_alive;
reg hact_alive;
reg [STATUS_ALIVE_WIDTH-1:0] status_alive;
reg [1:0] prst_with_sens_mrst = 2'h3; // prst extended to include sensor reset and rst_mmcm
wire async_prst_with_sens_mrst = ~imrst | rst_mmcm; // mclk domain
assign prsts = prst_with_sens_mrst[0]; // @pclk - includes sensor reset and sensor PLL reset
assign set_pxd_delay = set_idelay[2:0];
assign set_other_delay = set_idelay[3];
......@@ -213,8 +220,16 @@ module sens_parallel12 #(
assign iaro = trigger_mode? ~trig : iaro_soft;
assign irst=irst_r[2];
always @ (posedge ipclk) begin
irst_r <= {irst_r[1:0], prst};
// irst_r <= {irst_r[1:0], prst};
irst_r <= {irst_r[1:0], prsts}; // extended reset that includes sensor reset and rst_mmcm
end
always @(posedge pclk or posedge async_prst_with_sens_mrst) begin
if (async_prst_with_sens_mrst) prst_with_sens_mrst <= 2'h3;
else if (prst) prst_with_sens_mrst <= 2'h3;
else prst_with_sens_mrst <= prst_with_sens_mrst >> 1;
end
always @(posedge mclk) begin
......
sensor/sensor_channel.v
View file @ 2b1975c3
......@@ -205,10 +205,11 @@ module sensor_channel#(
parameter PXD_CAPACITANCE = "DONT_CARE",
parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz