Commit 2ac46e21 authored by Andrey Filippov's avatar Andrey Filippov

implemented read leveling, eye measurement for DDR3 on random data

parent f6b8d427
...@@ -62,72 +62,72 @@ ...@@ -62,72 +62,72 @@
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<link> <link>
<name>vivado_state/eddr3-synth.dcp</name> <name>vivado_state/eddr3-synth.dcp</name>
......
...@@ -20,7 +20,7 @@ ...@@ -20,7 +20,7 @@
*******************************************************************************/ *******************************************************************************/
`timescale 1ns/1ps `timescale 1ns/1ps
// minimizing total DQS in delay to match DQ (finedelay stage adds some?) // minimizing total DQS in delay to match DQ (finedelay stage adds some?)
`define NOFINEDELAY_DQS 1 //`define NOFINEDELAY_DQS 1
module byte_lane #( module byte_lane #(
parameter IODELAY_GRP ="IODELAY_MEMORY", parameter IODELAY_GRP ="IODELAY_MEMORY",
parameter IBUF_LOW_PWR ="TRUE", parameter IBUF_LOW_PWR ="TRUE",
......
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