fixing timestamp internal/external

fpga_version.vh

@@ -35,7 +35,8 @@
  * contains all the components and scripts required to completely simulate it
  * with at least one of the Free Software programs.
  */
-        parameter FPGA_VERSION =          32'h039300c2;      //parallel - external sync for Eyesis -0.160/71 79.84%
+        parameter FPGA_VERSION =          32'h039300c3;      //parallel - fixing timestamps
+//        parameter FPGA_VERSION =          32'h039300c2;      //parallel - external sync for Eyesis -0.160/71 79.84%
 //      parameter FPGA_VERSION =          32'h039300c1;      //parallel - modified after troubleshooting simulation -0.069/41, 79.90 %
 //      parameter FPGA_VERSION =          32'h039300c0;      //parallel - changing LOGGER_PAGE_IMU 3->0 (how it was in 353) -0.044/16, 79.59%
 //      parameter FPGA_VERSION =          32'h039300bf;      //parallel - mask extrenal timestamps mode -0.043/17 79.56%

timing/camsync393.v

@@ -227,7 +227,7 @@ module camsync393       #(
     reg     [9:0] input_use;       // 1 - use this bit
     reg     [9:0] input_pattern;   // data to be compared for trigger event to take place
     reg     [9:0] gpio_out_en_r;
-    reg           pre_input_use_intern;// @(posedge mclk) Use internal trigger generator, 0 - use external trigger (also switches delay from input to output)
+    reg           pre_input_use_intern = 1;// @(posedge mclk) Use internal trigger generator, 0 - use external trigger (also switches delay from input to output)
     reg           input_use_intern;//  @(posedge clk) 
     reg    [31:0] input_dly_chn0;  // delay value for the trigger
     reg    [31:0] input_dly_chn1;  // delay value for the trigger
@@ -418,7 +418,7 @@ module camsync393       #(
         if (!en) begin
             input_use <= 0;
             input_pattern <= 0;        
-            pre_input_use_intern <= 0; // use internal source for triggering
+            pre_input_use_intern <= 1; // use internal source for triggering
         end else if (set_trig_src_w) begin
             input_use <= input_use_w;
             input_pattern <= input_pattern_w;        
@@ -505,7 +505,7 @@ module camsync393       #(
 
         ts_snd_en_pclk<=ts_snd_en;
         input_use_intern <= pre_input_use_intern;
-        ts_external_pclk<= ts_external && !input_use_intern;
+        ts_external_pclk<= ts_external; //  && !input_use_intern;
      
         start_pclk[2:0] <= {(restart && rep_en) || 
 //                            (start_pclk[1] && !restart_cntr_run[1] && !restart_cntr_run[0] && !start_pclk[2]), // does not allow to restart