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Commit 28b974c3 authored Mar 24, 2016 by Andrey Filippov

continue on C exporting

parent fcd19b51

includes/x393_parameters.vh

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -85,7 +85,7 @@
	// 0x1030..1031 - MCONTR_EN // 0 bits, disable/enable memory controller		// 0x1030..1031 - MCONTR_EN // 0 bits, disable/enable memory controller
	// 0x1032..1033 - REFRESH_EN // 0 bits, disable/enable memory refresh		// 0x1032..1033 - REFRESH_EN // 0 bits, disable/enable memory refresh
	// 0x1034..1037 - reserved		// 0x1034..1037 - reserved
	parameter MCONTR_TOP_0BIT_MCONTR_EN = 'h0, // set pre-programmed delays		parameter MCONTR_TOP_0BIT_MCONTR_EN = 'h0, // disable/enable memory controller
	parameter MCONTR_TOP_0BIT_REFRESH_EN = 'h2, // disable/enable command/address outputs		parameter MCONTR_TOP_0BIT_REFRESH_EN = 'h2, // disable/enable command/address outputs
	//0x1040..107f - 16-bit data		//0x1040..107f - 16-bit data
	// 0x1040..104f - RUN_CHN // address to set sequncer channel and run (4 LSB-s - channel) - bits?		// 0x1040..104f - RUN_CHN // address to set sequncer channel and run (4 LSB-s - channel) - bits?

py393/x393_export_c.py

+455 −33

File changed.

Preview size limit exceeded, changes collapsed.

py393/x393_pio_sequences.py

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -822,7 +822,8 @@ class X393PIOSequences(object):
	self.x393_axi_tasks.write_control_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_REFRESH_PERIOD, t_refi)		self.x393_axi_tasks.write_control_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_REFRESH_PERIOD, t_refi)
	# enable refresh - should it be done here?		# enable refresh - should it be done here?
	if en_refresh:		if en_refresh:
	self.x393_axi_tasks.write_control_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_REFRESH_EN + 1, 0)		# self.x393_axi_tasks.write_control_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_REFRESH_EN + 1, 0)
			self.x393_axi_tasks.write_control_register(vrlg.MCONTR_TOP_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_REFRESH_EN + 1, 0)


	def set_mrs(self, # will also calibrate ZQ		def set_mrs(self, # will also calibrate ZQ