CVC defines set, part1 (26a449b6) · Commits · Elphel / x393

axi/axibram_write.v

+3 −1

Original line number	Original line	Diff line number	Diff line
	@@ -21,7 +21,9 @@
	*******************************************************************************/		*******************************************************************************/
	//`define DEBUG_FIFO 1		//`define DEBUG_FIFO 1
	`include "system_defines.vh"		`include "system_defines.vh"
			`ifdef DEBUG_FIFO
	`undef DEBUG_FIFO		`undef DEBUG_FIFO
			`endif
	module axibram_write #(		module axibram_write #(
	parameter ADDRESS_BITS = 10 // number of memory address bits		parameter ADDRESS_BITS = 10 // number of memory address bits
	)(		)(

ddr3/ddr3.v

+16 −4

Original line number	Original line	Diff line number	Diff line
	@@ -529,9 +529,21 @@ module ddr3 (
	integer rdqen_cntr;		integer rdqen_cntr;
	integer rdq_cntr;		integer rdq_cntr;

			`ifdef CVC
			wire [DQS_BITS-1:0] dqs_in0 = dqs_out_dly;
			wire [DQS_BITS-1:0] dqs_in1 = ~dqs_out_dly;
			wire [DQ_BITS-1:0] dq_in2 = dq_out_dly;
			wire [DQS_BITS-1:0] dqs_en0 = dqs_out_en_dly & {DQS_BITS{out_en}};
			wire [DQS_BITS-1:0] dqs_en1 = dqs_out_en_dly & {DQS_BITS{out_en}};
			wire [DQ_BITS-1:0] dq_en2 = dq_out_en_dly & {DQS_BITS{out_en}};
			bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_in0 ,dqs_en0 );
			bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, dqs_in1 ,dqs_en1 );
			bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_in2 , dq_en2 );
			`else
	bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en} });		bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en} });
	bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en} });		bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en} });
	bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_out_dly, dq_out_en_dly & {DQ_BITS {out_en} });		bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_out_dly, dq_out_en_dly & {DQ_BITS {out_en} });
			`endif
	assign tdqs_n = {DQS_BITS{1'bz}};		assign tdqs_n = {DQS_BITS{1'bz}};

	initial begin		initial begin

includes/x393_tasks_status.vh

+35 −1

Original line number	Original line	Diff line number	Diff line
	@@ -19,7 +19,40 @@
	* along with this program. If not, see <http://www.gnu.org/licenses/> .		* along with this program. If not, see <http://www.gnu.org/licenses/> .
	*******************************************************************************/		*******************************************************************************/

			`ifdef CVC
			task wait_status_condition;
			input [STATUS_DEPTH-1:0] status_address;
			input [29:0] status_control_address;
			input [1:0] status_mode;
			input [25:0] pattern; // bits as in read registers
			input [25:0] mask; // which bits to compare
			input invert_match; // 0 - wait until match to pattern (all bits), 1 - wait until no match (any of bits differ)
			input wait_seq;
			reg match;
			reg [5:0] seq_num;
			reg [31:0] pattern1;
			reg [31:0] mask1;
			begin
			WAITING_STATUS = 1;
			pattern1 = {6'h0,pattern};
			mask1 = {6'h0,mask};
			for (match=0; !match; match = invert_match ^ (((registered_rdata ^ pattern1) & mask1)==0)) begin
			read_status(status_address);
			if (wait_seq) begin
			seq_num = (registered_rdata[STATUS_SEQ_SHFT+:6] ^ 6'h20)&'h30;
			write_contol_register(status_control_address, {24'b0,status_mode,seq_num});
			read_status(status_address);
			while (((registered_rdata[STATUS_SEQ_SHFT+:6] ^ seq_num) & 6'h30)!=0) begin // match just 2 MSBs
			read_status(status_address);
			end
			end
			pattern1 = {6'h0,pattern};
			mask1 = {6'h0,mask};
			end
			WAITING_STATUS = 0;
			end
			endtask
			`else
	task wait_status_condition;		task wait_status_condition;
	input [STATUS_DEPTH-1:0] status_address;		input [STATUS_DEPTH-1:0] status_address;
	input [29:0] status_control_address;		input [29:0] status_control_address;
	@@ -46,6 +79,7 @@ task wait_status_condition;
	WAITING_STATUS = 0;		WAITING_STATUS = 0;
	end		end
	endtask		endtask
			`endif
	/*		/*
	task wait_status_condition_auto; // assumes status is already updating		task wait_status_condition_auto; // assumes status is already updating
	input [STATUS_DEPTH-1:0] status_address;		input [STATUS_DEPTH-1:0] status_address;

memctrl/mcntrl_ps_pio.v

+3 −1

Original line number	Original line	Diff line number	Diff line
	@@ -21,7 +21,9 @@
	*******************************************************************************/		*******************************************************************************/
	`timescale 1ns/1ps		`timescale 1ns/1ps
	`include "system_defines.vh"		`include "system_defines.vh"
			`ifdef DEBUG_FIFO
	`undef DEBUG_FIFO		`undef DEBUG_FIFO
			`endif
	module mcntrl_ps_pio#(		module mcntrl_ps_pio#(
	parameter MCNTRL_PS_ADDR= 'h100,		parameter MCNTRL_PS_ADDR= 'h100,
	parameter MCNTRL_PS_MASK= 'h3e0, // both channels 0 and 1		parameter MCNTRL_PS_MASK= 'h3e0, // both channels 0 and 1

memctrl/phy/dq_single.v

+7 −1

Original line number	Original line	Diff line number	Diff line
	@@ -110,9 +110,15 @@ idelay_fine_pipe # (
	.data_in(dq_di),		.data_in(dq_di),
	.data_out(dq_dly)		.data_out(dq_dly)
	);		);
			`ifdef CVC
			parameter FALSE_STING = "FALSE";
			`endif
	iserdes_mem #(		iserdes_mem #(
			`ifdef CVC
			.DYN_CLKDIV_INV_EN(FALSE_STING)
			`else
	.DYN_CLKDIV_INV_EN("FALSE")		.DYN_CLKDIV_INV_EN("FALSE")
			`endif
	) iserdes_mem_i (		) iserdes_mem_i (
	.iclk(iclk), // source-synchronous clock		.iclk(iclk), // source-synchronous clock
	.oclk(clk), // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin		.oclk(clk), // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin

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