Commit 26a449b6 authored by Alexey Grebenkin's avatar Alexey Grebenkin

CVC defines set, part1

parent e19ac0d8
...@@ -21,7 +21,9 @@ ...@@ -21,7 +21,9 @@
*******************************************************************************/ *******************************************************************************/
//`define DEBUG_FIFO 1 //`define DEBUG_FIFO 1
`include "system_defines.vh" `include "system_defines.vh"
`undef DEBUG_FIFO `ifdef DEBUG_FIFO
`undef DEBUG_FIFO
`endif
module axibram_write #( module axibram_write #(
parameter ADDRESS_BITS = 10 // number of memory address bits parameter ADDRESS_BITS = 10 // number of memory address bits
)( )(
......
...@@ -529,9 +529,21 @@ module ddr3 ( ...@@ -529,9 +529,21 @@ module ddr3 (
integer rdqen_cntr; integer rdqen_cntr;
integer rdq_cntr; integer rdq_cntr;
bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}}); `ifdef CVC
bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}}); wire [DQS_BITS-1:0] dqs_in0 = dqs_out_dly;
bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_out_dly, dq_out_en_dly & {DQ_BITS {out_en}}); wire [DQS_BITS-1:0] dqs_in1 = ~dqs_out_dly;
wire [DQ_BITS-1:0] dq_in2 = dq_out_dly;
wire [DQS_BITS-1:0] dqs_en0 = dqs_out_en_dly & {DQS_BITS{out_en}};
wire [DQS_BITS-1:0] dqs_en1 = dqs_out_en_dly & {DQS_BITS{out_en}};
wire [DQ_BITS-1:0] dq_en2 = dq_out_en_dly & {DQS_BITS{out_en}};
bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_in0 ,dqs_en0 );
bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, dqs_in1 ,dqs_en1 );
bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_in2 , dq_en2 );
`else
bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en} });
bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en} });
bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_out_dly, dq_out_en_dly & {DQ_BITS {out_en} });
`endif
assign tdqs_n = {DQS_BITS{1'bz}}; assign tdqs_n = {DQS_BITS{1'bz}};
initial begin initial begin
......
...@@ -19,7 +19,40 @@ ...@@ -19,7 +19,40 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> . * along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/ *******************************************************************************/
`ifdef CVC
task wait_status_condition;
input [STATUS_DEPTH-1:0] status_address;
input [29:0] status_control_address;
input [1:0] status_mode;
input [25:0] pattern; // bits as in read registers
input [25:0] mask; // which bits to compare
input invert_match; // 0 - wait until match to pattern (all bits), 1 - wait until no match (any of bits differ)
input wait_seq;
reg match;
reg [5:0] seq_num;
reg [31:0] pattern1;
reg [31:0] mask1;
begin
WAITING_STATUS = 1;
pattern1 = {6'h0,pattern};
mask1 = {6'h0,mask};
for (match=0; !match; match = invert_match ^ (((registered_rdata ^ pattern1) & mask1)==0)) begin
read_status(status_address);
if (wait_seq) begin
seq_num = (registered_rdata[STATUS_SEQ_SHFT+:6] ^ 6'h20)&'h30;
write_contol_register(status_control_address, {24'b0,status_mode,seq_num});
read_status(status_address);
while (((registered_rdata[STATUS_SEQ_SHFT+:6] ^ seq_num) & 6'h30)!=0) begin // match just 2 MSBs
read_status(status_address);
end
end
pattern1 = {6'h0,pattern};
mask1 = {6'h0,mask};
end
WAITING_STATUS = 0;
end
endtask
`else
task wait_status_condition; task wait_status_condition;
input [STATUS_DEPTH-1:0] status_address; input [STATUS_DEPTH-1:0] status_address;
input [29:0] status_control_address; input [29:0] status_control_address;
...@@ -46,6 +79,7 @@ task wait_status_condition; ...@@ -46,6 +79,7 @@ task wait_status_condition;
WAITING_STATUS = 0; WAITING_STATUS = 0;
end end
endtask endtask
`endif
/* /*
task wait_status_condition_auto; // assumes status is already updating task wait_status_condition_auto; // assumes status is already updating
input [STATUS_DEPTH-1:0] status_address; input [STATUS_DEPTH-1:0] status_address;
......
...@@ -21,7 +21,9 @@ ...@@ -21,7 +21,9 @@
*******************************************************************************/ *******************************************************************************/
`timescale 1ns/1ps `timescale 1ns/1ps
`include "system_defines.vh" `include "system_defines.vh"
`undef DEBUG_FIFO `ifdef DEBUG_FIFO
`undef DEBUG_FIFO
`endif
module mcntrl_ps_pio#( module mcntrl_ps_pio#(
parameter MCNTRL_PS_ADDR= 'h100, parameter MCNTRL_PS_ADDR= 'h100,
parameter MCNTRL_PS_MASK= 'h3e0, // both channels 0 and 1 parameter MCNTRL_PS_MASK= 'h3e0, // both channels 0 and 1
......
...@@ -110,9 +110,15 @@ idelay_fine_pipe # ( ...@@ -110,9 +110,15 @@ idelay_fine_pipe # (
.data_in(dq_di), .data_in(dq_di),
.data_out(dq_dly) .data_out(dq_dly)
); );
`ifdef CVC
parameter FALSE_STING = "FALSE";
`endif
iserdes_mem #( iserdes_mem #(
`ifdef CVC
.DYN_CLKDIV_INV_EN(FALSE_STING)
`else
.DYN_CLKDIV_INV_EN("FALSE") .DYN_CLKDIV_INV_EN("FALSE")
`endif
) iserdes_mem_i ( ) iserdes_mem_i (
.iclk(iclk), // source-synchronous clock .iclk(iclk), // source-synchronous clock
.oclk(clk), // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin .oclk(clk), // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
......
...@@ -13,21 +13,21 @@ ...@@ -13,21 +13,21 @@
`define def_enable_mem_chn0 `define def_enable_mem_chn0
`define def_read_mem_chn0 `define def_read_mem_chn0
`define def_write_mem_chn0 `define def_write_mem_chn0
`undef def_scanline_chn0 //`define def_scanline_chn0
`undef def_tiled_chn0 //`define def_tiled_chn0
// chn 1 is scanline r+w // chn 1 is scanline r+w
`define def_enable_mem_chn1 `define def_enable_mem_chn1
`define def_read_mem_chn1 `define def_read_mem_chn1
`define def_write_mem_chn1 `define def_write_mem_chn1
`define def_scanline_chn1 `define def_scanline_chn1
`undef def_tiled_chn1 //`define def_tiled_chn1
// chn 2 is tiled r+w // chn 2 is tiled r+w
`define def_enable_mem_chn2 `define def_enable_mem_chn2
`define def_read_mem_chn2 `define def_read_mem_chn2
`define def_write_mem_chn2 `define def_write_mem_chn2
`undef def_scanline_chn2 //`define def_scanline_chn2
`define def_tiled_chn2 `define def_tiled_chn2
// chn 3 is scanline r+w (reuse later) // chn 3 is scanline r+w (reuse later)
...@@ -35,46 +35,46 @@ ...@@ -35,46 +35,46 @@
`define def_read_mem_chn3 `define def_read_mem_chn3
`define def_write_mem_chn3 `define def_write_mem_chn3
`define def_scanline_chn3 `define def_scanline_chn3
`undef def_tiled_chn3 //`define def_tiled_chn3
// chn 4 is tiled r+w (reuse later) // chn 4 is tiled r+w (reuse later)
`define def_enable_mem_chn4 `define def_enable_mem_chn4
`define def_read_mem_chn4 `define def_read_mem_chn4
`define def_write_mem_chn4 `define def_write_mem_chn4
`undef def_scanline_chn4 //`define def_scanline_chn4
`define def_tiled_chn4 `define def_tiled_chn4
// chn 5 is disabled // chn 5 is disabled
`undef def_enable_mem_chn5 //`define def_enable_mem_chn5
// chn 6 is disabled // chn 6 is disabled
`undef def_enable_mem_chn6 //`define def_enable_mem_chn6
// chn 7 is disabled // chn 7 is disabled
`undef def_enable_mem_chn7 //`define def_enable_mem_chn7
// chn 8 is disabled // chn 8 is disabled
`undef def_enable_mem_chn8 //`define def_enable_mem_chn8
// chn 9 is disabled // chn 9 is disabled
`undef def_enable_mem_chn9 //`define def_enable_mem_chn9
// chn 10 is disabled // chn 10 is disabled
`undef def_enable_mem_chn10 //`define def_enable_mem_chn10
// chn 11 is disabled // chn 11 is disabled
`undef def_enable_mem_chn11 //`define def_enable_mem_chn11
// chn 12 is disabled // chn 12 is disabled
`undef def_enable_mem_chn12 //`define def_enable_mem_chn12
// chn 13 is disabled // chn 13 is disabled
`undef def_enable_mem_chn13 //`define def_enable_mem_chn13
// chn 14 is disabled // chn 14 is disabled
`undef def_enable_mem_chn14 //`define def_enable_mem_chn14
// chn 15 is disabled // chn 15 is disabled
`undef def_enable_mem_chn15 //`define def_enable_mem_chn15
`endif `endif
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
//`define use200Mhz 1 //`define use200Mhz 1
//`define DEBUG_FIFO 1 //`define DEBUG_FIFO 1
`undef WAIT_MRS //`undef WAIT_MRS
`define SET_PER_PIN_DELAYS 1 // set individual (including per-DQ pin delays) `define SET_PER_PIN_DELAYS 1 // set individual (including per-DQ pin delays)
`define READBACK_DELAYS 1 `define READBACK_DELAYS 1
`define PS_PIO_WAIT_COMPLETE 0 // wait until PS PIO module finished transaction before starting a new one `define PS_PIO_WAIT_COMPLETE 0 // wait until PS PIO module finished transaction before starting a new one
...@@ -53,10 +53,18 @@ module x393_testbench01 #( ...@@ -53,10 +53,18 @@ module x393_testbench01 #(
); );
`ifdef IVERILOG `ifdef IVERILOG
// $display("IVERILOG is defined"); // $display("IVERILOG is defined");
`ifdef NON_VDT_ENVIROMENT
parameter lxtname="x393.lxt";
`else
`include "IVERILOG_INCLUDE.v" `include "IVERILOG_INCLUDE.v"
`endif // NON_VDT_ENVIROMENT
`else `else
// $display("IVERILOG is not defined"); // $display("IVERILOG is not defined");
`ifdef CVC
parameter lxtname = "x393.fst";
`else
parameter lxtname = "x393.lxt"; parameter lxtname = "x393.lxt";
`endif // CVC
`endif `endif
`define DEBUG_WR_SINGLE 1 `define DEBUG_WR_SINGLE 1
`define DEBUG_RD_DATA 1 `define DEBUG_RD_DATA 1
......
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