merging with framepars

axi/histogram_saxi.v

@@ -388,8 +388,8 @@ module  histogram_saxi#(
         else if ( burst_done_w && !page_sent_mclk) pages_in_buf_wr <= pages_in_buf_wr + 1;
         else if (!burst_done_w &&  page_sent_mclk) pages_in_buf_wr <= pages_in_buf_wr - 1;
         
-//        grant <= en && rq_in && !buf_full && (!started || busy_r); // delay grant until chn_sel is set (first cycle of started)
-        grant <= en && rq_in && !buf_full && (grant || busy_r); // delay grant until chn_sel is set (first cycle of started)
+//        grant <= en && rq_in && !buf_full && (grant || busy_r); // delay grant until chn_sel is set (first cycle of started)
+        grant <= en && rq_in && !dav_r && !buf_full && (grant || busy_r); // delay grant until chn_sel is set (first cycle of started)
 
         
         if (!en) chn_grant <= 0;

dsp/dct_iv8_1d.v

@@ -71,11 +71,10 @@ module  dct_iv8_1d#(
     output [OUT_WIDTH -1:0]        dout,
     output reg                     pre2_start_out, // 2 clock cycle before Y0 output, full dout sequence
                                              // start_out-x-Y0-x-Y7-x-Y4-x-Y3-x-Y1-x-Y6-x-Y2-x-Y5
-    output reg                     en_out    // valid at the same time slot as pre2_start_out (goes active with pre2_start_out)                                      
+    output                         en_out,   // valid at the same time slot as pre2_start_out (goes active with pre2_start_out), 2 ahead of data
+    output reg               [2:0] y_index   // for simulation - valid with dout - index of the data output
+                                          
 );
-// X6-X7-X5-X2-X1-X3-X0-X4-*-X5-X1-X2-*-X4-X7-*
-// X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X1-X7-*
-// X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X6-X7-*
 
     localparam RSHIFT1 = 2; // safe right shift for stage 1
     localparam STAGE1_RSHIFT = COSINE_SHIFT + (WIDTH - A_WIDTH) + RSHIFT1; // divide by 4 in stage 1 - never saturates
@@ -132,6 +131,11 @@ module  dct_iv8_1d#(
     reg                         run_in;  // receiving input data
     reg                         restart; // restarting next block if en was active at phase=14;
     reg                         run_out; // running output data
+    reg                         en_out_r;
+    reg                         en_out_r2;
+    
+    
+    assign en_out = en_out_r;
     
     assign dsp_ain_2 = dsp_p_1 [STAGE1_RSHIFT +: A_WIDTH];
     
@@ -147,6 +151,23 @@ module  dct_iv8_1d#(
     wire din_zero = ~(|d_in);
     assign dsp_cin_1 = {{P_WIDTH-WIDTH-COSINE_SHIFT{d_in[WIDTH-1]}},d_in,~d_in[WIDTH-1]^din_zero,{COSINE_SHIFT-1{d_in[WIDTH-1]}}};
 
+    always @ (posedge clk) begin
+        en_out_r2 <= en_out_r;
+        if (en_out_r2) begin
+            case (phase_cnt[3:1])
+                3'h0: y_index <= 0;
+                3'h1: y_index <= 7;
+                3'h2: y_index <= 4;
+                3'h3: y_index <= 3;
+                3'h4: y_index <= 1;
+                3'h5: y_index <= 6;
+                3'h6: y_index <= 2;
+                3'h7: y_index <= 5;
+            endcase
+        end else begin
+            y_index <= 'bx;
+        end 
+    end
 
     //register files
     assign dsp_din_1 = dsp_din_1_ram[dsp_din_1_ra];
@@ -173,7 +194,7 @@ module  dct_iv8_1d#(
     
         pre2_start_out <= run_out && (phase_cnt == 14);
         
-        en_out <= run_out && !phase_cnt[0];
+        en_out_r <= run_out && !phase_cnt[0];
         
         // Cosine table, defined to fit into 17 bits for 18-bit signed DSP B-operand
         case (phase_cnt)

dsp/dct_tests_01.tf

@@ -40,7 +40,7 @@
 `timescale 1ns/1ps
 // No saturation here, and no rounding as we do not need to match decoder (be bit-precise), skipping rounding adder
 // will reduce needed resources
-//`define DCT_INPUT_UNITY
+`define DCT_INPUT_UNITY
 module  dct_tests_01 ();
 //    parameter fstname="dct_tests_01.fst";
 `ifdef IVERILOG              
@@ -61,11 +61,16 @@ module  dct_tests_01 ();
     `endif // CVC
 `endif // IVERILOG
     
-    parameter CLK_PERIOD = 10; // ns
-    parameter WIDTH =        24; // input data width
-//    parameter OUT_WIDTH =    16; // output data width
-    parameter OUT_WIDTH =    24; // output data width
-    parameter OUT_RSHIFT =    3;  // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
+    parameter CLK_PERIOD =     10; // ns
+    parameter WIDTH =           24; // input data width
+//    parameter OUT_WIDTH =     16; // output data width
+    parameter OUT_WIDTH =       24; // output data width
+    parameter TRANSPOSE_WIDTH = 24; // width of the transpose memory (intermediate results)    
+    parameter OUT_RSHIFT =       2;  // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
+    parameter OUT_RSHIFT2 =      0;  // overall right shift for the second (vertical) pass
+    
+    parameter DCT_GAP = 16; // between runs            
+    
     
     reg              RST = 1'b1;
     reg              CLK = 1'b0;
@@ -83,15 +88,17 @@ module  dct_tests_01 ();
     
     wire             x_we = !phase_in[3] && run_in;
     reg  [WIDTH-1:0] x_in;
+    reg  [WIDTH-1:0] x_in_2d;
     reg  [WIDTH-1:0] x_out;
     reg  [WIDTH-1:0] x_ram[0:7];
     wire [WIDTH-1:0] x_out_w = x_ram[x_ra];
     
     reg              start = 0;
+    reg              start2 = 0; // second start for 2d
     
-    wire [OUT_WIDTH-1:0] y_dct;           // S uppressThisWarning VEditor - simulation only
-    wire                 pre2_start_out;  // S uppressThisWarning VEditor - simulation only
-    wire                 en_out;          // S uppressThisWarning VEditor - simulation only
+    wire [OUT_WIDTH-1:0] y_dct;
+    wire                 pre2_start_out;
+    wire                 en_out;
     
     reg                  y_pre_we;
     reg                  y_we;
@@ -103,13 +110,27 @@ module  dct_tests_01 ();
     wire signed [OUT_WIDTH-1:0] y_out = y_ram[y_ra];           // SuppressThisWarning VEditor - simulation only
     reg  signed     [WIDTH-1:0] data_in[0:63];
     reg  signed [OUT_WIDTH-1:0] data_out[0:63];
-    integer              i,j;
+
+    wire                        pre_last_in_2d;    // SuppressThisWarning VEditor - simulation only
+    wire                        pre_first_out_2d;  // SuppressThisWarning VEditor - simulation only
+    wire                        pre_busy_2d;       // SuppressThisWarning VEditor - simulation only
+    wire                        dv_2d;             // SuppressThisWarning VEditor - simulation only
+    wire signed [OUT_WIDTH-1:0] d_out_2d; 
+
+    wire                        pre_last_in_2dr;   // SuppressThisWarning VEditor - simulation only
+    wire                        pre_first_out_2dr; // SuppressThisWarning VEditor - simulation only
+    wire                        pre_busy_2dr;      // SuppressThisWarning VEditor - simulation only
+    wire                        dv_2dr;            // SuppressThisWarning VEditor - simulation only
+    wire signed [OUT_WIDTH-1:0] d_out_2dr;         // SuppressThisWarning VEditor - simulation only
+
+    
+    integer              i,j, i1;
     initial begin
         for (i=0; i<64; i=i+1) begin
 `ifdef DCT_INPUT_UNITY
-            data_in[i] = (i[2:0] == i[5:3]) ? {2'b1,{WIDTH-2{1'b0}}} : 0;
+            data_in[i] =  (i[2:0] == i[5:3]) ? {2'b1,{WIDTH-2{1'b0}}} : 0;
 `else
-            data_in[i] = $random;
+            data_in[i]  = $random;
 `endif
         end
         $display("Input data in line-scan order:");
@@ -147,23 +168,6 @@ module  dct_tests_01 ();
             if (&i[2:0]) repeat (8) @(posedge CLK);
         end
         #1 x_in = 0;
-/*        
-        // running 'one' - just make a period == 17
-        repeat (7) begin
-            @(posedge CLK);
-#1          x_in = {2'b1,{WIDTH-2{1'b0}}}; // >>x_wa;
-            @(posedge CLK);
-#1            x_in = 0; 
-            repeat (15) @(posedge CLK); // 16+1= 17, non-zero will go through all of the 8 x[i]
-        end
-        begin
-            @(posedge CLK);
-#1            x_in = {2'b1,{WIDTH-2{1'b0}}};
-            @(posedge CLK);
-#1            x_in = 0; 
-            en_x = 0;
-        end
-*/        
         repeat (64) @(posedge CLK);
         
         $display("");
@@ -173,8 +177,44 @@ module  dct_tests_01 ();
                                                        data_out[i+4],data_out[i+5],data_out[i+6],data_out[i+7]);
         end
         
+//        repeat (64) @(posedge CLK);
+//        $finish;
+    end
+
+    initial begin
+        wait (!RST);
+        while (!start) begin
+            @(posedge CLK);
+            #1;
+        end    
+        for (i1 = 0; i1 < 64; i1 = i1+1) begin
+            @(posedge CLK);
+            #1;
+            x_in_2d = data_in[i1];
+            if (i1 == 63) start2 = 1;
+        end
+        for (i1 = 0; i1 < 64; i1 = i1+1) begin
+            @(posedge CLK);
+            #1;
+            start2 = 0;
+            x_in_2d = data_in[i1];
+        end
+        
+        repeat (DCT_GAP) @(posedge CLK);
+        #1;
+        start2 = 1;
+        for (i1 = 0; i1 < 64; i1 = i1+1) begin
+            @(posedge CLK);
+            #1;
+            start2 = 0;
+            x_in_2d = data_in[63-i1];
+        end
+        
+        repeat (300) @(posedge CLK);
         $finish;
+        
     end
+    
 
     initial j = 0;
     always @ (posedge CLK) begin
@@ -285,7 +325,53 @@ module  dct_tests_01 ();
         .start          (start),          // input
         .dout           (y_dct),          // output[15:0] 
         .pre2_start_out (pre2_start_out), // output reg 
-        .en_out         (en_out)          // output reg 
+        .en_out         (en_out),          // output reg
+        .y_index        () // output[2:0] reg 
     );
 
+
+
+    dct_iv_8x8 #(
+        .INPUT_WIDTH     (WIDTH),
+        .OUT_WIDTH       (OUT_WIDTH),
+        .OUT_RSHIFT1     (OUT_RSHIFT),
+        .OUT_RSHIFT2     (OUT_RSHIFT2),
+        .TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
+        .DSP_B_WIDTH     (18),
+        .DSP_A_WIDTH     (25),
+        .DSP_P_WIDTH     (48)
+    ) dct_iv_8x8_i (
+        .clk            (CLK),              // input
+        .rst            (RST),              // input
+        .start          (start || start2),  // input
+        .xin            (x_in_2d),          // input[24:0] signed 
+        .pre_last_in    (pre_last_in_2d),       // output reg 
+        .pre_first_out  (pre_first_out_2d), // output
+        .dv             (dv_2d),            // output
+        .d_out          (d_out_2d),         // output[24:0] signed
+        .pre_busy       (pre_busy_2d)       // output reg 
+    );
+
+    dct_iv_8x8 #(
+        .INPUT_WIDTH     (WIDTH),
+        .OUT_WIDTH       (OUT_WIDTH),
+        .OUT_RSHIFT1     (OUT_RSHIFT),
+        .OUT_RSHIFT2     (OUT_RSHIFT2),
+        .TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
+        .DSP_B_WIDTH     (18),
+        .DSP_A_WIDTH     (25),
+        .DSP_P_WIDTH     (48)
+    ) dct_iv_8x8r_i (
+        .clk            (CLK),               // input
+        .rst            (RST),               // input
+        .start          (pre_first_out_2d),  // input
+        .xin            (d_out_2d),          // input[24:0] signed 
+        .pre_last_in    (pre_last_in_2dr),   // output reg 
+        .pre_first_out  (pre_first_out_2dr), // output
+        .dv             (dv_2dr),            // output
+        .d_out          (d_out_2dr),         // output[24:0] signed
+        .pre_busy       (pre_busy_2dr)       // output reg 
+    );
+
+
 endmodule

fpga_version.vh

@@ -35,8 +35,11 @@
  * contains all the components and scripts required to completely simulate it
  * with at least one of the Free Software programs.
  */
-        parameter FPGA_VERSION =          32'h039300d7;      //parallel - updated SATA (v12) all met, 80.32%
-//        parameter FPGA_VERSION =          32'h039300d6;      //parallel - more SATA debug link layer -0.127/18, 80.03% -> -0.002/4, 80.26%
+        parameter FPGA_VERSION =          32'h039300da;      //parallel - sata v.13 - tolerating elidle from device during comreset/cominit -0.014 /1, 81.38%, 
+//      parameter FPGA_VERSION =          32'h039300d9;      //parallel - correcting histograms -0.022/1, 79.60%
+//      parameter FPGA_VERSION =          32'h039300d8;      //parallel - SATA is now logging irq on/off -0.054 /16, 80.50%
+//      parameter FPGA_VERSION =          32'h039300d7;      //parallel - updated SATA (v12) all met, 80.32%
+//      parameter FPGA_VERSION =          32'h039300d6;      //parallel - more SATA debug link layer -0.127/18, 80.03% -> -0.002/4, 80.26%
 //      parameter FPGA_VERSION =          32'h039300d5;      //parallel - more SATA debug (v.0xd) -0.021/8 80.20 %
 //      parameter FPGA_VERSION =          32'h039300d4;      //parallel - more SATA debug (v.0xd) -0.064 /24 80.77%
 //      parameter FPGA_VERSION =          32'h039300d3;      //parallel - Updated SATA (v.0xb) -0.073/22

includes/ahci_defaults.vh

@@ -2,6 +2,6 @@
 , .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
 , .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
 , .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000)
-, .INIT_0C (256'h000000000000000000000000000000000000000001010011001000000001FFFE)
+, .INIT_0C (256'h000000000000000000000000000000000000000001010013001000000001FFFE)
 , .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
 , .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)

includes/ahci_localparams.vh

@@ -97,7 +97,7 @@
 // RO: HBA Revision ID
     localparam PCI_Header__RID__RID__ADDR = 'h62;
     localparam PCI_Header__RID__RID__MASK = 'hff;
-    localparam PCI_Header__RID__RID__DFLT = 'h11;
+    localparam PCI_Header__RID__RID__DFLT = 'h13;
 // RO: Base Class Code: 1 - Mass Storage Device
     localparam PCI_Header__CC__BCC__ADDR = 'h62;
     localparam PCI_Header__CC__BCC__MASK = 'hff000000;

py393/x393_jpeg.py

@@ -3045,6 +3045,151 @@ set_sensor_lens_flat_parameters  3  0  None None None None None 0x1d00 0x1d00 0x
 jpeg_sim_multi 4
 
 
+################## Simulate Parallel 18 - debugging histograms  ####################
+./py393/test_mcntrl.py @py393/cocoargs  --simulated=localhost:7777
+measure_all "*DI"
+setup_all_sensors True None 0xf
+#set_sensor_io_ctl  all None None 1 # Set ARO low - check if it is still needed?
+
+#use EOF instead of SOF for i2c sequencer advance
+set_sensor_i2c_command  all  False  None  None  None None None None True
+
+#just testing
+set_gpio_ports  1   1 # enable software gpio pins and porta (camsync)
+set_gpio_pins 0 1 # pin 0 low, pin 1 - high
+
+set_logger_params_file "/home/eyesis/git/x393-neon/attic/imu_config.bin"
+
+##### write_control_register 0x480  0x400 # disable sensor chn 2
+
+reset_camsync_inout 1 # reset all outputs
+set_camsync_period 31 # set bit duration
+set_camsync_period  0 # disable
+set_camsync_delay 0 400
+set_camsync_delay 1 300
+set_camsync_delay 2 200
+set_camsync_delay 3 150
+#set_camsync_inout  <is_out>  <bit_number>  <active_positive>
+###set_camsync_inout  1  8  0
+###set_camsync_inout  0  7  0
+reset_camsync_inout  0 # start with internal trigger
+
+#set_camsync_mode  <en=None>  <en_snd=None>  <en_ts_external=None>  <triggered_mode=None>  <master_chn=None>  <chn_en=None> 
+set_camsync_mode  1 1 1 1 0 0xf
+set_camsync_period  0 # so next setting period will immadiately trigger
+set_camsync_period  8000 # 80 usec #and issue first trigger
+
+##set_sensor_histogram_window  0  0  4  4  25 21
+##set_sensor_histogram_window  1  0  4  4  41 21
+##set_sensor_histogram_window  2  0  4  4  25 41
+##set_sensor_histogram_window  3  0  4  4  41 41
+set_sensor_histogram_window  0  0  4  4  41 21
+set_sensor_histogram_window  1  0  4  4  41 41
+set_sensor_histogram_window  2  0  4  4  41 41
+set_sensor_histogram_window  3  0  4  4  41 41
+
+r
+read_control_register 0x430
+read_control_register 0x431
+write_cmd_frame_sequencer  0  1  2  0x600  0x48   # compressor q page = 1 // too late for frame 2
+set_qtables 0 0 80
+set_qtables 0 1 70
+
+#irq coming, image not changing - yes
+###write_cmd_frame_sequencer  0  1  1 0x686 0x280005 #save 4 more lines than sensor has                                                                                                                                    
+write_cmd_frame_sequencer  0  1  1 0x680 0x5507 #enable abort
+#write_cmd_frame_sequencer  0  1  1 0x6c6 0x300006 #save 4 more lines that compressor has                                                                                                                                    
+
+###write_cmd_frame_sequencer  0  1  2  0x600  0x5    #stop    compressor           `      
+###write_cmd_frame_sequencer  0  1  2  0x680  0x5405 # stop  sensor memory         (+0) // sensor memory should be controlled first, (9 commands
+###write_cmd_frame_sequencer  0  1  2  0x6c0  0x5c49 # stop compressor memory      (+0)
+
+###write_cmd_frame_sequencer  0  1  3 0x686 0x240005 # correct lines                                                                                                   
+###write_cmd_frame_sequencer  0  1  3  0x680  0x5507 # run sensor memory           (+1) Can not be 0
+
+###write_cmd_frame_sequencer  0  1  4 0x686 0x280005 #save 4 more lines than sensor has                                                                                                                                    
+###write_cmd_frame_sequencer  0  1  4 0x6c6 0x300006 #save more lines than compressor needs (sensor provides)                                                                                                                                    
+###write_cmd_frame_sequencer  0  1  4  0x6c0  0x7d4b # run compressor memory       (+2)
+###write_cmd_frame_sequencer  0  1  4  0x600  0x7    # run compressor              (+0)
+
+write_cmd_frame_sequencer  0  1  1  0x600  0x48   # compressor q page = 1
+write_cmd_frame_sequencer  0  1  4  0x600  0x40   # compressor q page = 0
+
+read_control_register 0x431
+read_control_register 0x430
+
+#testing histograms
+write_control_register 0x409 0xc0
+
+#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
+#set_sensor_io_ctl all None None None None None 1 None # load all delays?
+compressor_control  all  None  None  None None None  2
+compressor_interrupt_control all clr
+compressor_interrupt_control all en
+compressor_control  all  3
+r
+read_status 0x21
+r
+jpeg_sim_multi 4
+
+###set_camsync_period  9000 # 90 usec # change period, skip first trigger
+
+
+set_camsync_delay 0 400
+set_camsync_delay 1 300
+set_camsync_delay 2 200
+set_camsync_delay 3 100
+
+r
+read_status 0x21
+r
+###jpeg_sim_multi 3
+jpeg_sim_multi 4
+r
+read_status 0x21
+r
+set_camsync_delay 0 400
+set_camsync_delay 1 350
+set_camsync_delay 2 200
+set_camsync_delay 3 50
+
+
+
+
+
+##write_cmd_frame_sequencer  0  1  1 0x686 0x240005 # correct lines                                                                                                   
+##write_cmd_frame_sequencer  0  1  1 0x6c6 0x200006 # correct lines                                                                                                                                    
+##write_cmd_frame_sequencer  0  1  1  0x680  0x5507 # run sensor memory, update frame#, reset buffers
+##write_cmd_frame_sequencer  0  1  1  0x6c0  0x7d4b # run compressor memory
+##write_cmd_frame_sequencer  0  1  1  0x600  0x7    # run compressor
+
+#switch to external (wired) trigger
+
+jpeg_sim_multi 4
+
+set_camsync_delay 0 400
+set_camsync_delay 1 400
+set_camsync_delay 2 200
+set_camsync_delay 3 0
+
+
+
+
+### set_camsync_inout  0  9  0 # external/internal trigger mode
+
+
+###switch to external (wired) trigger
+##set_camsync_inout  0  7  0
+
+jpeg_sim_multi 4
+#set_camsync_mode  <en=None>  <en_snd=None>  <en_ts_external=None>  <triggered_mode=None>  <master_chn=None>  <chn_en=None> 
+jpeg_sim_multi 8
+
+###set_camsync_period  8000 # 80 usec - restart while waiting for external trigger
+jpeg_sim_multi 4
+
+jpeg_sim_multi 4
+
 
 
 ################## Serial ####################

sensor/sens_histogram_snglclk.v

@@ -356,6 +356,7 @@ module  sens_histogram_snglclk #(
         // prevent starting rq if grant is still on (back-to-back)
         if      (!hist_out)   en_rq_start <= 0;
         else if (!hist_grant) en_rq_start <= 1;
+
         hist_rq_r <= !hist_rst & en_mclk && hist_out && !(&hist_raddr) && en_rq_start;
         
         if      (!hist_out || (&hist_raddr[7:0])) hist_re[0] <= 0;

x393_sata/ahci/ahci_top.v

@@ -1217,6 +1217,7 @@ wire [9:0] xmit_dbg_01;
                 .d2h_ready       (d2h_ready), // input
                 .debug_link_send_data(debug_link_send_data), // input
                 .debug_link_dmatp  (debug_link_dmatp),        // link received DMATp from device
+                .irq             (irq),           // system IRQ
                 .datascope_clk   (datascope_clk), // output
                 .datascope_waddr (datascope_waddr), // output[9:0] reg 
                 .datascope_we    (datascope_we), // output
@@ -1350,6 +1351,7 @@ module datascope_timing #(
     
     input                     debug_link_send_data, // @posedge mclk (sata_clk, 75MHz)  - last symbol was data output (to count sent out)
     input                     debug_link_dmatp,     // link received DMATp from device
+    input                     irq,                  // system irq
     output                        datascope_clk,
     output reg [ADDRESS_BITS-1:0] datascope_waddr,
     output                        datascope_we,
@@ -1408,6 +1410,10 @@ module datascope_timing #(
     
     reg                       reset_link_count; // data FIS from dma command until
     reg                       was_link_dmatp;   //
+    reg                       irq_r;
+    reg                       irq_was;
+    wire                      we_w = write_punch_time || fis_start || (fis_we ? pre_we_r : (!fis_run && (fis_run_d || fis_run_d2 || fis_run_d3 || fis_run_d4  || fis_run_d5))); // 3 after
+    wire                      we_irq= (irq_was ^ irq_r) && !we_w; // only when not irq  
     
 //    input              debug_link_dmatp,      // link received DMATp from device
     
@@ -1436,11 +1442,11 @@ module datascope_timing #(
         else if (!fis_run_d2 && fis_run_d3)  datascope_di <= {8'h55,   last_dma_cmd};
         else if (!fis_run_d3 && fis_run_d4)  datascope_di <= non_dma_act;
         else if (!fis_run_d4 && fis_run_d5)  datascope_di <= {h2d_nready_cntr[7:0], was_link_dmatp, 1'b0, link_count_latched};
-
+        else if (we_irq)                     datascope_di <= {3'h7,irq_r,cur_time};
         pre_we_r <= pre_we_w || fis_start ;
     
 //        we_r <= write_punch_time || fis_start || (fis_we ? pre_we_r : (!fis_run && fis_run_d));
-        we_r <= write_punch_time || fis_start || (fis_we ? pre_we_r : (!fis_run && (fis_run_d || fis_run_d2 || fis_run_d3 || fis_run_d4  || fis_run_d5))); // 3 after
+        we_r <= we_w || we_irq;
         
         if     (fis_start) fis_left <= FIS_LEN - 1;
         else if (pre_we_w) fis_left <= fis_left - 1;
@@ -1509,6 +1515,11 @@ module datascope_timing #(
         if      (rst)  datascope_waddr <= 0;
         else if (we_r) datascope_waddr <= datascope_waddr + 1;
         
+        irq_r <= irq;
+        
+        if      (rst)    irq_was <=0;
+        else if (we_irq) irq_was <= irq_r;
+        
     end
     
 endmodule

x393_sata/device/oob_dev.v

@@ -44,7 +44,10 @@
 // All references to doc = to SerialATA_Revision_2_6_Gold.pdf
 module oob_dev #(
     parameter DATA_BYTE_WIDTH = 4,
-    parameter CLK_SPEED_GRADE = 2 // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz
+    parameter CLK_SPEED_GRADE = 2, // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz
+    parameter TEST_ELIDLE =      2,      // test transmitting eidle between data rates (number of times)
+    parameter ELIDLE_DELAY =    'h28, // 80,    // counter cycles
+    parameter ELIDLE_DURATION = 'h80    // counter cycles
 )
 (
     // sata clk = usrclk2
@@ -83,15 +86,21 @@ localparam  STATE_CALIBRATE         = 4;
 localparam  STATE_COMWAKE           = 5;
 localparam  STATE_RECAL             = 55;
 localparam  STATE_SENDALIGN         = 6;
+localparam  STATE_EIDLE_RATE        = 65; 
 localparam  STATE_READY             = 7;
 localparam  STATE_PARTIAL           = 8;
 localparam  STATE_SLUMBER           = 9;
 localparam  STATE_REDUCESPEED       = 10;
 localparam  STATE_ERROR             = 11;
 
+
+reg     [31:0]  rate_change_cntr;
+reg             was_txelecidle;
 reg     [9:0]   state;
 wire    retry_interval_elapsed;
 wire    wait_interval_elapsed;
+wire    elidle_rate_delay_elapsed; 
+wire    elidle_rate_duration_elapsed; 
 wire    nocomwake;
 wire    [31:0]  align;
 wire    [31:0]  sync;
@@ -110,9 +119,21 @@ always @ (posedge clk)
     retry_timer <= rst | ~(state == STATE_AWAITCOMWAKE) ? 32'h0 : retry_timer + 1'b1;
 
 reg [31:0]  wait_timer;
-assign  wait_interval_elapsed = wait_timer == 32'd4096;
+assign  wait_interval_elapsed =   wait_timer == 32'd4096;
+assign elidle_rate_delay_elapsed = wait_timer == ELIDLE_DELAY;
 always @ (posedge clk)
     wait_timer <= rst | ~(state == STATE_SENDALIGN) ? 32'h0 : wait_timer + 1'b1;
+reg [31:0] elidle_timer;
+assign elidle_rate_duration_elapsed = elidle_timer == ELIDLE_DURATION;    
+always @ (posedge clk)
+    elidle_timer <= rst | ~(state == STATE_EIDLE_RATE) ? 32'h0 : elidle_timer + 1'b1;
+
+always @ (posedge clk) begin
+    was_txelecidle <= txelecidle;
+    if (rst)                                rate_change_cntr <= 0;
+    else if (txelecidle && !was_txelecidle) rate_change_cntr <= rate_change_cntr + 1;  
+end
+
 
 reg [31:0]  data;
 reg [3:0]   isk;
@@ -218,6 +239,7 @@ always @ (posedge clk)
         end
         STATE_SENDALIGN:
         begin
+            txelecidle <= 1'b0;
             data    <= align;
             isk     <= 4'h1;
             if (aligndet)
@@ -225,9 +247,21 @@ always @ (posedge clk)
             else 
             if (wait_interval_elapsed)
                 state   <= STATE_ERROR;
-            else
+            else if ((rate_change_cntr < TEST_ELIDLE) && elidle_rate_delay_elapsed)
+                state   <= STATE_EIDLE_RATE;
+            else 
                 state   <= STATE_SENDALIGN;
         end
+
+        STATE_EIDLE_RATE:
+        begin
+            txelecidle <= 1'b1;
+            data    <= 0; // align; // 'bz;
+            isk     <= 4'h1;
+            if (elidle_rate_duration_elapsed)
+                state   <= STATE_SENDALIGN;
+        end
+        
         STATE_READY:
         begin
             txelecidle <= 1'b0;

x393_sata/host/oob.v

@@ -223,7 +223,11 @@ always @ (posedge clk) begin
     else                         rxdlysreset_r <= rxdlysreset_r << 1; 
 end
 
-
+reg was_rxelecidle_waiting_reset;
+always @ (posedge clk) begin
+    if      (rst || set_wait_eidle)          was_rxelecidle_waiting_reset <= 0;
+    else if (state_wait_rxrst && rxelecidle) was_rxelecidle_waiting_reset <= 1;
+end
 assign  state_idle = ~state_wait_cominit &
                      ~state_wait_comwake &
                      ~state_wait_align &
@@ -253,11 +257,17 @@ end
 assign  set_wait_cominit   = state_idle & oob_start & ~cominit_req;
 assign  set_wait_comwake   = state_idle & cominit_req_l & cominit_allow & rxcominit_done | state_wait_cominit & rxcominitdet_l & rxcominit_done;
 assign  set_recal_tx       = state_wait_comwake & rxcomwakedet_l & rxcomwake_done;
-assign  set_wait_eidle     = state_recal_tx & recal_tx_done;
+///assign  set_wait_eidle     = state_recal_tx & recal_tx_done;
+assign  set_wait_eidle     = (state_recal_tx & recal_tx_done) |
+                             (rxelecidle & 
+                              (state_wait_align | state_wait_clk_align | state_wait_align2 | (state_wait_rxrst & rxreset_ack & was_rxelecidle_waiting_reset) ));
 assign  set_wait_rxrst     = state_wait_eidle & eidle_timer_done;
-assign  set_wait_align     = state_wait_rxrst & rxreset_ack;
-assign  set_wait_clk_align = state_wait_align & (detected_alignp_r);
-assign  set_wait_align2    = state_wait_clk_align & clk_phase_align_ack;
+///assign  set_wait_align     = state_wait_rxrst & rxreset_ack;
+///assign  set_wait_clk_align = state_wait_align & (detected_alignp_r);
+///assign  set_wait_align2    = state_wait_clk_align & clk_phase_align_ack;
+assign  set_wait_align     = state_wait_rxrst & rxreset_ack & ~rxelecidle;
+assign  set_wait_clk_align = state_wait_align & (detected_alignp_r) & ~rxelecidle;
+assign  set_wait_align2    = state_wait_clk_align & clk_phase_align_ack & ~rxelecidle;
 
 
 
@@ -278,10 +288,18 @@ assign  clr_wait_cominit   = set_wait_comwake   | set_error;
 assign  clr_wait_comwake   = set_recal_tx       | set_error;
 assign  clr_recal_tx       = set_wait_eidle     | set_error;
 assign  clr_wait_eidle     = set_wait_rxrst     | set_error;
-assign  clr_wait_rxrst     = set_wait_align     | set_error;
-assign  clr_wait_align     = set_wait_clk_align | set_error;
-assign  clr_wait_clk_align = set_wait_align2    | set_error;
-assign  clr_wait_align2    = set_wait_synp      | set_error;
+///assign  clr_wait_rxrst     = set_wait_align     | set_error;
+assign  clr_wait_rxrst     = state_wait_rxrst & rxreset_ack; 
+
+///assign  clr_wait_align     = set_wait_clk_align | set_error;
+///assign  clr_wait_clk_align = set_wait_align2    | set_error;
+///assign  clr_wait_align2    = set_wait_synp      | set_error;
+assign  clr_wait_align     = set_wait_clk_align | set_error | rxelecidle;
+assign  clr_wait_clk_align = set_wait_align2    | set_error | rxelecidle;
+assign  clr_wait_align2    = set_wait_synp      | set_error | rxelecidle;
+
+
+
 assign  clr_wait_synp      = set_wait_linkup    | set_error;
 assign  clr_wait_linkup    = state_wait_linkup; //TODO not so important, but still have to trace 3 back-to-back non alignp primitives
 assign  clr_error          = state_error;