Skip to content

X
x393
Commit 2317d4fd authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

fixing for simulation with current software

parent 149d5fa7
Hide whitespace changes
Inline Side-by-side
Showing with 129 additions and 217 deletions
ddr3/ddr3.v
View file @ 2317d4fd
...@@ -2534,7 +2534,7 @@ module ddr3 ( ...@@ -2534,7 +2534,7 @@ module ddr3 (
end end
task cmd_addr_timing_check; task cmd_addr_timing_check;
input i; input [4:0]i;
reg [4:0] i; reg [4:0] i;
begin begin
if (rst_n_in && prev_cke) begin if (rst_n_in && prev_cke) begin
...@@ -2578,7 +2578,7 @@ module ddr3 ( ...@@ -2578,7 +2578,7 @@ module ddr3 (
// Processes to check setup and hold of data signals // Processes to check setup and hold of data signals
task dm_timing_check; task dm_timing_check;
input i; input [4:0] i;
reg [4:0] i; reg [4:0] i;
begin begin
if (dqs_in_valid) begin if (dqs_in_valid) begin
...@@ -2629,7 +2629,7 @@ module ddr3 ( ...@@ -2629,7 +2629,7 @@ module ddr3 (
always @(dm_in[31]) dm_timing_check(31); always @(dm_in[31]) dm_timing_check(31);
task dq_timing_check; task dq_timing_check;
input i; input [6:0] i;
reg [6:0] i; reg [6:0] i;
begin begin
if (dqs_in_valid) begin if (dqs_in_valid) begin
...@@ -2776,7 +2776,7 @@ module ddr3 ( ...@@ -2776,7 +2776,7 @@ module ddr3 (
always @(dq_in[127]) dq_timing_check(127); always @(dq_in[127]) dq_timing_check(127);
task dqs_pos_timing_check; task dqs_pos_timing_check;
input i; input [5:0] i;
reg [5:0] i; reg [5:0] i;
reg [4:0] j; reg [4:0] j;
begin begin
...@@ -2911,7 +2911,7 @@ module ddr3 ( ...@@ -2911,7 +2911,7 @@ module ddr3 (
always @(negedge dqs_in[63]) if (!dqs_in[63]) dqs_pos_timing_check(63); always @(negedge dqs_in[63]) if (!dqs_in[63]) dqs_pos_timing_check(63);
task dqs_neg_timing_check; task dqs_neg_timing_check;
input i; input [5:0] i;
reg [5:0] i; reg [5:0] i;
reg [4:0] j; reg [4:0] j;
begin begin
......
fpga_version.vh
View file @ 2317d4fd
...@@ -35,9 +35,11 @@ ...@@ -35,9 +35,11 @@
* contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
parameter FPGA_VERSION = 32'h03931003; // parallel, adding camsync trigger decimation - modifying decimation parameter FPGA_VERSION = 32'h03934016; // Boson640, for 103993A, started IMU
// parameter FPGA_VERSION = 32'h03934015; // Boson640, for 103993A, debugging 4 removed DE deglitch - modifying decimation // parameter FPGA_VERSION = 32'h03931004; // parallel, starting IMS support // not yet used
// parameter FPGA_VERSION = 32'h03931004; // parallel, adding camsync trigger decimation - modifying decimation // parameter FPGA_VERSION = 32'h03931003; // parallel, adding camsync trigger decimation - modifying decimation
// parameter FPGA_VERSION = 32'h03934015; // Boson640, for 103993A, debugging 4 removed DE deglitch - modifying decimation
// parameter FPGA_VERSION = 32'h03931004; // parallel, adding camsync trigger decimation - modifying decimation
// parameter FPGA_VERSION = 32'h03934014; // Boson640, for 103993A, debugging 4 removed DE deglitch // parameter FPGA_VERSION = 32'h03934014; // Boson640, for 103993A, debugging 4 removed DE deglitch
// parameter FPGA_VERSION = 32'h03934013; // Boson640, for 103993A, debugging 3 failed (maybe just phases) // parameter FPGA_VERSION = 32'h03934013; // Boson640, for 103993A, debugging 3 failed (maybe just phases)
// parameter FPGA_VERSION = 32'h03934012; // Boson640, for 103993A, debugging 2 works, shifted by 1 pix hor (found bug) // parameter FPGA_VERSION = 32'h03934012; // Boson640, for 103993A, debugging 2 works, shifted by 1 pix hor (found bug)
......
logger/event_logger.v
View file @ 2317d4fd
...@@ -313,12 +313,13 @@ module event_logger#( ...@@ -313,12 +313,13 @@ module event_logger#(
assign enable_syn_mclk= config_rst_mclk? 4'b0 : config_syn_mclk; assign enable_syn_mclk= config_rst_mclk? 4'b0 : config_syn_mclk;
always @ (posedge xclk) begin always @ (posedge xclk) begin
if (we_bitHalfPeriod_xclk) bitHalfPeriod[15:0] <= bitHalfPeriod_mclk[15:0]; if (xrst) config_rst <= 1'b1;
if (we_config_imu_xclk) config_imu <= config_imu_mclk; else if (we_config_rst_xclk) config_rst <= config_rst_mclk;
if (we_config_gps_xclk) config_gps <= config_gps_mclk; if (we_bitHalfPeriod_xclk) bitHalfPeriod[15:0] <= bitHalfPeriod_mclk[15:0];
if (we_config_msg_xclk) config_msg <= config_msg_mclk; if (we_config_imu_xclk) config_imu <= config_imu_mclk;
if (we_config_rst_xclk) config_rst <= config_rst_mclk; if (we_config_gps_xclk) config_gps <= config_gps_mclk;
if (we_config_debug_xclk) config_debug <= config_debug_mclk; if (we_config_msg_xclk) config_msg <= config_msg_mclk;
if (we_config_debug_xclk) config_debug <= config_debug_mclk;
enable_gps <= (^config_gps[1:0]) && !config_rst; // both 00 and 11 - disable enable_gps <= (^config_gps[1:0]) && !config_rst; // both 00 and 11 - disable
enable_msg <= (config_gps[3:0] != 4'hf) && !config_rst; enable_msg <= (config_gps[3:0] != 4'hf) && !config_rst;
enable_timestamps <= !config_rst; enable_timestamps <= !config_rst;
......
logger/nmea_decoder393.v
View file @ 2317d4fd
...@@ -106,7 +106,6 @@ module nmea_decoder393( ...@@ -106,7 +106,6 @@ module nmea_decoder393(
reg [ 7:0] debug0; reg [ 7:0] debug0;
reg [15:0] debug1; reg [15:0] debug1;
reg [15:0] debug1_or; reg [15:0] debug1_or;
assign debug[23:0] = {1'b0, assign debug[23:0] = {1'b0,
proc_fields, proc_fields,
vfy_first_comma, vfy_first_comma,
...@@ -282,10 +281,21 @@ module nmea_decoder393( ...@@ -282,10 +281,21 @@ module nmea_decoder393(
reg [3:0] odbuf1_ram[0:31]; reg [3:0] odbuf1_ram[0:31];
reg [3:0] odbuf2_ram[0:31]; reg [3:0] odbuf2_ram[0:31];
reg [3:0] odbuf3_ram[0:31]; reg [3:0] odbuf3_ram[0:31];
always @ (posedge xclk) if (nibble_stb && (nibble_count[1:0] == 2'h0)) odbuf0_ram[nibble_count[6:2]] <= nibble[3:0]; /// always @ (posedge xclk) if (nibble_stb && (nibble_count[1:0] == 2'h0)) odbuf0_ram[nibble_count[6:2]] <= nibble[3:0];
always @ (posedge xclk) if (nibble_stb && (nibble_count[1:0] == 2'h1)) odbuf1_ram[nibble_count[6:2]] <= nibble[3:0]; /// always @ (posedge xclk) if (nibble_stb && (nibble_count[1:0] == 2'h1)) odbuf1_ram[nibble_count[6:2]] <= nibble[3:0];
always @ (posedge xclk) if (nibble_stb && (nibble_count[1:0] == 2'h2)) odbuf2_ram[nibble_count[6:2]] <= nibble[3:0]; /// always @ (posedge xclk) if (nibble_stb && (nibble_count[1:0] == 2'h2)) odbuf2_ram[nibble_count[6:2]] <= nibble[3:0];
always @ (posedge xclk) if (nibble_stb && (nibble_count[1:0] == 2'h3)) odbuf3_ram[nibble_count[6:2]] <= nibble[3:0]; /// always @ (posedge xclk) if (nibble_stb && (nibble_count[1:0] == 2'h3)) odbuf3_ram[nibble_count[6:2]] <= nibble[3:0];
wire nibble_0 = nibble_count[1:0] == 2'h0;
wire nibble_1 = nibble_count[1:0] == 2'h1;
wire nibble_2 = nibble_count[1:0] == 2'h2;
wire nibble_3 = nibble_count[1:0] == 2'h3;
// writing zeros to unused nibbles (2023)
always @ (posedge xclk) if (nibble_stb && (nibble_0)) odbuf0_ram[nibble_count[6:2]] <= nibble[3:0];
always @ (posedge xclk) if (nibble_stb && (nibble_0 || nibble_1)) odbuf1_ram[nibble_count[6:2]] <= nibble[3:0] & {4{nibble_1}};
always @ (posedge xclk) if (nibble_stb && (nibble_0 || nibble_2)) odbuf2_ram[nibble_count[6:2]] <= nibble[3:0] & {4{nibble_2}};
always @ (posedge xclk) if (nibble_stb && (nibble_0 || nibble_3)) odbuf3_ram[nibble_count[6:2]] <= nibble[3:0] & {4{nibble_3}};
assign rdata[ 3: 0] = odbuf0_ram[raddr[4:0]]; assign rdata[ 3: 0] = odbuf0_ram[raddr[4:0]];
assign rdata[ 7: 4] = odbuf1_ram[raddr[4:0]]; assign rdata[ 7: 4] = odbuf1_ram[raddr[4:0]];
......
py393/x393_logger.py
View file @ 2317d4fd
...@@ -285,7 +285,8 @@ int logger_init_fpga(int force) ///< if 0, only do if not already initialized ...@@ -285,7 +285,8 @@ int logger_init_fpga(int force) ///< if 0, only do if not already initialized
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.DATA_REG, divisor - 1) self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.DATA_REG, divisor - 1)
def zterm(self,l): def zterm(self,l):
return ''.join(l[:l.index(chr(0))]) # return ''.join(l[:l.index(chr(0))])
return l[:l.index(0)]
def logger_set_nmea(self, nmea_format): def logger_set_nmea(self, nmea_format):
""" """
...@@ -294,22 +295,24 @@ int logger_init_fpga(int force) ///< if 0, only do if not already initialized ...@@ -294,22 +295,24 @@ int logger_init_fpga(int force) ///< if 0, only do if not already initialized
""" """
# int nmea_sel[16]; # int nmea_sel[16];
# int nmea_fpga_frmt[16]; # int nmea_fpga_frmt[16];
nmea_chars=list(nmea_format) nmea_chars= list(nmea_format)
nmea_sel = [0]*16 nmea_sel = [0]*16
nmea_fpga_frmt = [0]*16 nmea_fpga_frmt = [0]*16
for n in range(4): for n in range(4):
nmea_chars[32*n+27]=0; # just in case nmea_chars[32*n+27]=0; # just in case
print("Setting NMEA sentence format for $GP%s"%(self.zterm(nmea_chars[32*n:]))) print("Setting NMEA sentence format for $GP%s"%(bytearray(self.zterm(nmea_chars[32*n:])).decode()))
print("(0x%x, 0x%x, 0x%x\n"%(ord(nmea_chars[32*n]),ord(nmea_chars[32*n+1]),ord(nmea_chars[32*n+2]))); # print("(0x%x, 0x%x, 0x%x\n"%(ord(nmea_chars[32*n]),ord(nmea_chars[32*n+1]),ord(nmea_chars[32*n+2])));
print("(0x%x, 0x%x, 0x%x\n"%(nmea_chars[32*n],nmea_chars[32*n+1],nmea_chars[32*n+2]));
f=0; f=0;
for i in range(2,-1,-1): for i in range(2,-1,-1):
b=ord(nmea_chars[32*n+i]) # first 3 letters in each sentence # b=ord(nmea_chars[32*n+i]) # first 3 letters in each sentence
b=nmea_chars[32*n+i] # first 3 letters in each sentence
print("n=%d, i=%d, b=0x%x"%(n,i,b)) print("n=%d, i=%d, b=0x%x"%(n,i,b))
for j in range (4,-1,-1): # (j=4; j>=0; j--) { for j in range (4,-1,-1): # (j=4; j>=0; j--) {
f<<=1; f<<=1;
if ((b & (1<<j)) != 0): if ((b & (1<<j)) != 0):
f += 1 f += 1
print("n=%d, f=0x%x"%(n,f)) print("n=%d, f=0x%x"%(n,f)) # good
for i in range(15): for i in range(15):
if ((f & (1<<i))!=0): if ((f & (1<<i))!=0):
nmea_sel[i] |= (1<<n); nmea_sel[i] |= (1<<n);
...@@ -319,20 +322,22 @@ int logger_init_fpga(int force) ///< if 0, only do if not already initialized ...@@ -319,20 +322,22 @@ int logger_init_fpga(int force) ///< if 0, only do if not already initialized
#for (i=0; (i<24) && (nmea_format[32*n+3+i]!=0);i++ ) { #for (i=0; (i<24) && (nmea_format[32*n+3+i]!=0);i++ ) {
for i in range(24): for i in range(24):
if nmea_chars[32*n+3+i]==chr(0): # if nmea_chars[32*n+3+i]==chr(0):
if nmea_chars[32*n+3+i]==0:
break break
b=nmea_chars[32*n+3+i] b=nmea_chars[32*n+3+i]
if (b=='b') or (b=='B'): # if (b=='b') or (b=='B'):
if (b==ord('b')) or (b==ord('B')):
f |= (1<<i); f |= (1<<i);
nmea_fpga_frmt[n*4] += 1 nmea_fpga_frmt[n*4] += 1
nmea_fpga_frmt[n*4+1] = f & 0xff; nmea_fpga_frmt[n*4+1] = f & 0xff;
nmea_fpga_frmt[n*4+2] = (f >> 8) & 0xff; nmea_fpga_frmt[n*4+2] = (f >> 8) & 0xff;
nmea_fpga_frmt[n*4+3] = (f >> 16) & 0xff; nmea_fpga_frmt[n*4+3] = (f >> 16) & 0xff;
print("Selection data is %x%x%x%x%x%x%x%x%x%x%x%x%x%x%x"%(nmea_sel[0],nmea_sel[1],nmea_sel[2], print("Selection data is %x%x%x%x%x%x%x%x%x%x%x%x%x%x%x"%(nmea_sel[0],nmea_sel[1],nmea_sel[2],
nmea_sel[3],nmea_sel[4],nmea_sel[5],nmea_sel[6],nmea_sel[7],nmea_sel[8],nmea_sel[9], nmea_sel[3],nmea_sel[4],nmea_sel[5],nmea_sel[6],nmea_sel[7],nmea_sel[8],nmea_sel[9],
nmea_sel[10],nmea_sel[11],nmea_sel[12],nmea_sel[13],nmea_sel[14])) nmea_sel[10],nmea_sel[11],nmea_sel[12],nmea_sel[13],nmea_sel[14])) # good
print("Format data for sentence 1 is %02x %02x %02x %02x\n"%(nmea_fpga_frmt[ 0],nmea_fpga_frmt[ 1],nmea_fpga_frmt[ 2],nmea_fpga_frmt[ 3])) print("Format data for sentence 1 is %02x %02x %02x %02x\n"%(nmea_fpga_frmt[ 0],nmea_fpga_frmt[ 1],nmea_fpga_frmt[ 2],nmea_fpga_frmt[ 3])) # all but [0] are 0
print("Format data for sentence 2 is %02x %02x %02x %02x\n"%(nmea_fpga_frmt[ 4],nmea_fpga_frmt[ 5],nmea_fpga_frmt[ 6],nmea_fpga_frmt[ 7])) print("Format data for sentence 2 is %02x %02x %02x %02x\n"%(nmea_fpga_frmt[ 4],nmea_fpga_frmt[ 5],nmea_fpga_frmt[ 6],nmea_fpga_frmt[ 7]))
print("Format data for sentence 3 is %02x %02x %02x %02x\n"%(nmea_fpga_frmt[ 8],nmea_fpga_frmt[ 9],nmea_fpga_frmt[10],nmea_fpga_frmt[11])) print("Format data for sentence 3 is %02x %02x %02x %02x\n"%(nmea_fpga_frmt[ 8],nmea_fpga_frmt[ 9],nmea_fpga_frmt[10],nmea_fpga_frmt[11]))
print("Format data for sentence 4 is %02x %02x %02x %02x\n"%(nmea_fpga_frmt[12],nmea_fpga_frmt[13],nmea_fpga_frmt[14],nmea_fpga_frmt[15])) print("Format data for sentence 4 is %02x %02x %02x %02x\n"%(nmea_fpga_frmt[12],nmea_fpga_frmt[13],nmea_fpga_frmt[14],nmea_fpga_frmt[15]))
...@@ -362,7 +367,8 @@ int logger_init_fpga(int force) ///< if 0, only do if not already initialized ...@@ -362,7 +367,8 @@ int logger_init_fpga(int force) ///< if 0, only do if not already initialized
""" """
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.ADDR_REG, self.X313_IMU_REGISTERS_ADDR); self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.ADDR_REG, self.X313_IMU_REGISTERS_ADDR);
for i,c in enumerate(registers): for i,c in enumerate(registers):
d = ord(c) # d = ord(c)
d = c
print("%d: logging IMU register with 0x%lx"%(i+1, d)) print("%d: logging IMU register with 0x%lx"%(i+1, d))
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.DATA_REG, d); self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.DATA_REG, d);
...@@ -375,11 +381,11 @@ int logger_init_fpga(int force) ///< if 0, only do if not already initialized ...@@ -375,11 +381,11 @@ int logger_init_fpga(int force) ///< if 0, only do if not already initialized
if len(lmessage) < 56: if len(lmessage) < 56:
lmessage +=chr(0)*(56-len(lmessage)) lmessage +=chr(0)*(56-len(lmessage))
lmessage = lmessage[:56] lmessage = lmessage[:56]
print("Setting odometer message %56s"%(self.zterm(lmessage))) print("Setting odometer message %56s"%(bytearray(self.zterm(lmessage)).decode()))
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.ADDR_REG, self.X313_IMU_REGISTERS_ADDR) self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.ADDR_REG, self.X313_IMU_REGISTERS_ADDR)
for i in range(0,56,4): for i in range(0,56,4):
d=ord(lmessage[i]) + (ord(lmessage[i+1]) << 8) + (ord(lmessage[i+1]) << 16) + (ord(lmessage[i+1]) << 24) # d=ord(lmessage[i]) + (ord(lmessage[i+1]) << 8) + (ord(lmessage[i+1]) << 16) + (ord(lmessage[i+1]) << 24)
d=lmessage[i] + (lmessage[i+1] << 8) + (lmessage[i+1] << 16) + (lmessage[i+1] << 24)
print("%d: message 4 bytes= 0x%08x"%((i//4)+1,d)) print("%d: message 4 bytes= 0x%08x"%((i//4)+1,d))
self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.DATA_REG, d) self.x393_axi_tasks.write_control_register(vrlg.LOGGER_ADDR + self.DATA_REG, d)
...@@ -427,7 +433,7 @@ int logger_init_fpga(int force) ///< if 0, only do if not already initialized ...@@ -427,7 +433,7 @@ int logger_init_fpga(int force) ///< if 0, only do if not already initialized
for i, d in enumerate(wbuf): for i, d in enumerate(wbuf):
if (i & 0x1f) == 0: if (i & 0x1f) == 0:
print("\n %03x"%(i), end = "") print("\n %03x"%(i), end = "")
print(" %02x"%(ord(wbuf[i])),end="") print(" %02x"%(wbuf[i]),end="")
if which & self.WHICH_RESET: if which & self.WHICH_RESET:
self.logger_reset(1) self.logger_reset(1)
if which & self.WHICH_INIT: if which & self.WHICH_INIT:
...@@ -470,10 +476,10 @@ int logger_init_fpga(int force) ///< if 0, only do if not already initialized ...@@ -470,10 +476,10 @@ int logger_init_fpga(int force) ///< if 0, only do if not already initialized
WHICH_EN_LOGGER = 2048 WHICH_EN_LOGGER = 2048
@param wbuf - string with configuration data (as generated by start_gps_compas.php @param wbuf - string with configuration data (as generated by start_gps_compas.php
""" """
with open (file_path,"r") as f: with open (file_path,"rb") as f:
wbuf=f.read() wbuf=f.read()
self.set_logger_params(which = which, wbuf=wbuf) self.set_logger_params(which = which, wbuf=wbuf)
""" """
def logger_reset(self, rst): def logger_reset(self, rst):
def logger_init(self,config): def logger_init(self,config):
...@@ -604,4 +610,4 @@ X313_IMU_REGISTERS_OFFS = 0x14 # .. 0x2f ...@@ -604,4 +610,4 @@ X313_IMU_REGISTERS_OFFS = 0x14 # .. 0x2f
X313_IMU_NMEA_FORMAT_OFFS = 0x30 X313_IMU_NMEA_FORMAT_OFFS = 0x30
X313_IMU_MESSAGE_OFFS = 0xB0 # 0xB0..0xE7 X313_IMU_MESSAGE_OFFS = 0xB0 # 0xB0..0xE7
""" """
\ No newline at end of file
py393/x393_sens_cmprs.py
View file @ 2317d4fd
...@@ -900,9 +900,10 @@ class X393SensCmprs(object): ...@@ -900,9 +900,10 @@ class X393SensCmprs(object):
height2_m1 = 0) height2_m1 = 0)
# Configure histograms # Configure histograms
if verbose >0 : if (histogram_left >= 0):
print ("===================== HISTOGRAMS_SETUP =========================") if verbose >0 :
self.x393Sensor.set_sensor_histogram_window ( # 353 did it using command sequencer) print ("===================== HISTOGRAMS_SETUP =========================")
self.x393Sensor.set_sensor_histogram_window ( # 353 did it using command sequencer)
num_sensor = num_sensor, num_sensor = num_sensor,
subchannel = 0, subchannel = 0,
left = histogram_left, left = histogram_left,
...@@ -910,16 +911,20 @@ class X393SensCmprs(object): ...@@ -910,16 +911,20 @@ class X393SensCmprs(object):
width_m1 = histogram_width_m1, width_m1 = histogram_width_m1,
height_m1 = histogram_height_m1) height_m1 = histogram_height_m1)
self.x393Sensor.set_sensor_histogram_saxi_addr ( self.x393Sensor.set_sensor_histogram_saxi_addr (
num_sensor = num_sensor, num_sensor = num_sensor,
subchannel = 0, subchannel = 0,
page = histogram_start_phys_page) # for the channel/subchannel = 0/0 page = histogram_start_phys_page) # for the channel/subchannel = 0/0
self.x393Sensor.set_sensor_histogram_saxi ( self.x393Sensor.set_sensor_histogram_saxi (
en = True, en = True,
nrst = True, nrst = True,
confirm_write = False, # True, confirm_write = False, # True,
cache_mode = 3) cache_mode = 3)
else:
if verbose >0 :
print ("===================== HISTOGRAMS_SETUP SKIPPED!=========================")
if exit_step == 18: return False if exit_step == 18: return False
......
system_defines.vh
View file @ 2317d4fd
...@@ -65,7 +65,7 @@ ...@@ -65,7 +65,7 @@
`define DISPLAY_COMPRESSED_DATA `define DISPLAY_COMPRESSED_DATA
// if specific sesnor is not defined, parallel sensor interface is used for all channels // if specific sesnor is not defined, parallel sensor interface is used for all channels
/*************** CHANGE here and x393_hispi | x393_parallel | x393_lwir | x393_boson in bitstream (and few other) tool settings ****************/ /*************** CHANGE here and x393_hispi | x393_parallel | x393_lwir | x393_boson in bitstream (and few other) tool settings ****************/
// `define BOSON 1 `define BOSON 1
// `define LWIR // `define LWIR
// `define HISPI // `define HISPI
// also change in utilization and timimg summary tools (x393_parallel_utilization.report, ...) // also change in utilization and timimg summary tools (x393_parallel_utilization.report, ...)
......
timing/camsync393.v
View file @ 2317d4fd
...@@ -265,10 +265,10 @@ module camsync393 #( ...@@ -265,10 +265,10 @@ module camsync393 #(
reg [9:0] gpio_out_en_r; reg [9:0] gpio_out_en_r;
reg pre_input_use_intern = 1;// @(posedge mclk) Use internal trigger generator, 0 - use external trigger (also switches delay from input to output) reg pre_input_use_intern = 1;// @(posedge mclk) Use internal trigger generator, 0 - use external trigger (also switches delay from input to output)
reg input_use_intern;// @(posedge clk) reg input_use_intern;// @(posedge clk)
reg [31:0] input_dly_chn0; // delay value for the trigger reg [31:0] input_dly_chn0 = 0; // delay value for the trigger
reg [31:0] input_dly_chn1; // delay value for the trigger reg [31:0] input_dly_chn1 = 0; // delay value for the trigger
reg [31:0] input_dly_chn2; // delay value for the trigger reg [31:0] input_dly_chn2 = 0; // delay value for the trigger
reg [31:0] input_dly_chn3; // delay value for the trigger reg [31:0] input_dly_chn3 = 0; // delay value for the trigger
reg [3:0] chn_en_r; reg [3:0] chn_en_r;
wire [3:0] chn_en = chn_en_r & {4{en}}; // enable channels wire [3:0] chn_en = chn_en_r & {4{en}}; // enable channels
......
x393_sata/wrapper/GTXE2_GPL.v
View file @ 2317d4fd
...@@ -772,7 +772,9 @@ assign next_disparity = ^oword[word_count - 1] ? word_disparity[word_count - 1] ...@@ -772,7 +772,9 @@ assign next_disparity = ^oword[word_count - 1] ? word_disparity[word_count - 1]
endmodule endmodule
module gtxe2_chnl_tx_oob #( module gtxe2_chnl_tx_oob #(
parameter width = 20 parameter width = 20,
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b0101,
parameter SATA_CPLL_CFG = "VCO_3000MHZ"
) )
( (
// top-level ifaces // top-level ifaces
...@@ -787,8 +789,8 @@ module gtxe2_chnl_tx_oob #( ...@@ -787,8 +789,8 @@ module gtxe2_chnl_tx_oob #(
output wire [width - 1:0] outdata, output wire [width - 1:0] outdata,
output wire outval output wire outval
); );
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b0101; //parameter [3:0] SATA_BURST_SEQ_LEN = 4'b0101;
parameter SATA_CPLL_CFG = "VCO_3000MHZ"; //parameter SATA_CPLL_CFG = "VCO_3000MHZ";
localparam burst_len_mult = SATA_CPLL_CFG == "VCO_3000MHZ" ? 2 // assuming each usrclk cycle == 20 sata serial clk cycles localparam burst_len_mult = SATA_CPLL_CFG == "VCO_3000MHZ" ? 2 // assuming each usrclk cycle == 20 sata serial clk cycles
: SATA_CPLL_CFG == "VCO_1500MHZ" ? 4 : SATA_CPLL_CFG == "VCO_1500MHZ" ? 4
...@@ -1140,6 +1142,7 @@ wire [internal_data_width - 1:0] oob_data; ...@@ -1140,6 +1142,7 @@ wire [internal_data_width - 1:0] oob_data;
wire oob_val; wire oob_val;
assign oob_active = oob_val; assign oob_active = oob_val;
gtxe2_chnl_tx_oob #( gtxe2_chnl_tx_oob #(
.width (internal_data_width), .width (internal_data_width),
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN), .SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN),
......
x393_testbench04.gtkw
View file @ 2317d4fd
[*] [*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
[*] Wed Mar 16 06:26:20 2016 [*] Fri Feb 3 08:57:07 2023
[*] [*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20160315224430019.fst" [dumpfile] "/home/elphel/git/x393/simulation/x393_dut-20230203013317437.fst"
[dumpfile_mtime] "Wed Mar 16 05:18:26 2016" [dumpfile_mtime] "Fri Feb 3 08:56:46 2023"
[dumpfile_size] 287405686 [dumpfile_size] 119037938
[savefile] "/home/andrey/git/x393/x393_testbench04.gtkw" [savefile] "/home/elphel/git/x393/x393_testbench04.gtkw"
[timestart] 0 [timestart] 11741760
[size] 1823 1180 [size] 1828 1171
[pos] -1 -1 [pos] 105 -1
*-25.170794 11766250 105383200 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-13.170794 11761250 105383200 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03. [treeopen] x393_dut.
[treeopen] x393_testbench03.simul_axi_hp1_wr_i. [treeopen] x393_dut.simul_axi_hp1_wr_i.
[treeopen] x393_testbench03.simul_axi_hp_wr_i. [treeopen] x393_dut.x393_i.
[treeopen] x393_testbench03.x393_i. [treeopen] x393_dut.x393_i.cmd_mux_i.
[treeopen] x393_testbench03.x393_i.compressor393_i. [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0]. [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i. [treeopen] x393_dut.x393_i.event_logger_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3. [treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].
[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i. [treeopen] x393_dut.x393_i.sensors393_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_103993_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_103993_i.sens_103993_l3_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_103993_i.serial_103993_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_103993_i.serial_103993_i.serial_fslp_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.chn1wr_buf_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_103993_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_103993_i.sens_103993_l3_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_103993_i.
[treeopen] x393_dut.x393_i.timing393_i.
[treeopen] x393_dut.x393_i.timing393_i.rtc393_i.
[sst_width] 391 [sst_width] 391
[signals_width] 325 [signals_width] 325
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 500 [sst_vpaned_height] 537
@800200
-interrupts
-wresp
@28 @28
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.hclk x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sof
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.afi_bvalid_r x393_dut.x393_i.timing393_i.rtc393_i.khz
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.afi_bready_r x393_dut.x393_i.event_logger_i.enable_gps
x393_dut.x393_i.event_logger_i.enable_msg
@22 @22
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.id_r[4:0] x393_dut.x393_i.event_logger_i.enable_syn_mclk[3:0]
@200 x393_dut.x393_i.event_logger_i.imu_data[15:0]
-
@1000200
-wresp
@800022
[color] 3
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.eof_stb[3:0]
@28 @28
[color] 2 x393_dut.x393_i.event_logger_i.mclk
(0)x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.eof_stb[3:0] x393_dut.x393_i.event_logger_i.miso
[color] 2 x393_dut.x393_i.event_logger_i.mosi
(1)x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.eof_stb[3:0]
[color] 2
(2)x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.eof_stb[3:0]
[color] 2
(3)x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.eof_stb[3:0]
@1001200
-group_end
@28
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.eof_written3
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.eof_written2
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.eof_written1
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.eof_written0
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.afi_bvalid
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.afi_bvalid_r
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.afi_bready
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.afi_bready_r
@22 @22
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.afi_bid[5:0] x393_dut.x393_i.event_logger_i.sample_counter[23:0]
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.id_r[4:0]
@28
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.pre_busy
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.en
@c00022
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.busy[4:0]
@28
(0)x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.busy[4:0]
(1)x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.busy[4:0]
(2)x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.busy[4:0]
(3)x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.busy[4:0]
(4)x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.cmprs_afi_mux_ptr_wresp_i.busy[4:0]
@1401200
-group_end
@28 @28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.is_r x393_dut.x393_i.event_logger_i.we_gps
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_status_i.mrst x393_dut.x393_i.event_logger_i.we_imu
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.mrst x393_dut.x393_i.event_logger_i.we_message
@800023 x393_dut.x393_i.event_logger_i.we_period
x393_testbench03.x393_i.frseq_is[3:0]
@29 @29
(0)x393_testbench03.x393_i.frseq_is[3:0] x393_dut.x393_i.event_logger_i.xclk
(1)x393_testbench03.x393_i.frseq_is[3:0]
(2)x393_testbench03.x393_i.frseq_is[3:0]
(3)x393_testbench03.x393_i.frseq_is[3:0]
@1001201
-group_end
@22
x393_testbench03.x393_i.frseq_im[3:0]
x393_testbench03.x393_i.frseq_irq[3:0]
@1000200
-interrupts
@800200
-simulate_hp
@c00022
x393_testbench03.simul_axi_hp1_wr_i.wresp_i.data_out[7:0]
@28
(0)x393_testbench03.simul_axi_hp1_wr_i.wresp_i.data_out[7:0]
(1)x393_testbench03.simul_axi_hp1_wr_i.wresp_i.data_out[7:0]
(2)x393_testbench03.simul_axi_hp1_wr_i.wresp_i.data_out[7:0]
(3)x393_testbench03.simul_axi_hp1_wr_i.wresp_i.data_out[7:0]
(4)x393_testbench03.simul_axi_hp1_wr_i.wresp_i.data_out[7:0]
(5)x393_testbench03.simul_axi_hp1_wr_i.wresp_i.data_out[7:0]
(6)x393_testbench03.simul_axi_hp1_wr_i.wresp_i.data_out[7:0]
(7)x393_testbench03.simul_axi_hp1_wr_i.wresp_i.data_out[7:0]
@1401200
-group_end
@28
x393_testbench03.simul_axi_hp1_wr_i.bready
x393_testbench03.simul_axi_hp1_wr_i.bresp_in[1:0]
x393_testbench03.simul_axi_hp1_wr_i.bvalid
@22
x393_testbench03.simul_axi_hp1_wr_i.bid[5:0]
x393_testbench03.simul_axi_hp1_wr_i.bid_in[5:0]
@28
x393_testbench03.simul_axi_hp1_wr_i.bresp[1:0]
x393_testbench03.simul_axi_hp1_wr_i.last_confirmed_write
@22
x393_testbench03.simul_axi_hp1_wr_i.wid[5:0]
@28
x393_testbench03.simul_axi_hp1_wr_i.wresp_ext_i.we
x393_testbench03.simul_axi_hp1_wr_i.fifo_wd_rd_dly
@22
x393_testbench03.simul_axi_hp1_wr_i.bid_in[5:0]
@c00022
x393_testbench03.simul_axi_hp1_wr_i.wresp_num_in_fifo[5:0]
@28
(0)x393_testbench03.simul_axi_hp1_wr_i.wresp_num_in_fifo[5:0]
(1)x393_testbench03.simul_axi_hp1_wr_i.wresp_num_in_fifo[5:0]
(2)x393_testbench03.simul_axi_hp1_wr_i.wresp_num_in_fifo[5:0]
(3)x393_testbench03.simul_axi_hp1_wr_i.wresp_num_in_fifo[5:0]
(4)x393_testbench03.simul_axi_hp1_wr_i.wresp_num_in_fifo[5:0]
(5)x393_testbench03.simul_axi_hp1_wr_i.wresp_num_in_fifo[5:0]
@1401200
-group_end
@28
x393_testbench03.simul_axi_hp1_wr_i.wresp_i.we
@c00022
x393_testbench03.simul_axi_hp1_wr_i.wresp_i.fill[5:0]
@28
(0)x393_testbench03.simul_axi_hp1_wr_i.wresp_i.fill[5:0]
(1)x393_testbench03.simul_axi_hp1_wr_i.wresp_i.fill[5:0]
(2)x393_testbench03.simul_axi_hp1_wr_i.wresp_i.fill[5:0]
(3)x393_testbench03.simul_axi_hp1_wr_i.wresp_i.fill[5:0]
(4)x393_testbench03.simul_axi_hp1_wr_i.wresp_i.fill[5:0]
(5)x393_testbench03.simul_axi_hp1_wr_i.wresp_i.fill[5:0]
@1401200
-group_end
@28
x393_testbench03.simul_axi_hp1_wr_i.wresp_i.re
x393_testbench03.simul_axi_hp1_wr_i.wresp_i.rem
@200
-
@28
x393_testbench03.simul_axi_hp1_wr_i.wresp_i.nempty
@22
x393_testbench03.simul_axi_hp1_wr_i.bid[5:0]
@200
-
@22
x393_testbench03.simul_axi_hp1_wr_i.wresp_ext_i.wa[4:0]
x393_testbench03.simul_axi_hp1_wr_i.wresp_ext_i.data_in[7:0]
@28
x393_testbench03.simul_axi_hp1_wr_i.wresp_ext_i.re
x393_testbench03.simul_axi_hp1_wr_i.wresp_ext_i.rem
@22
x393_testbench03.simul_axi_hp1_wr_i.wresp_i.wa[4:0]
@28
x393_testbench03.simul_axi_hp1_wr_i.wresp_i.we
@200
-
@1000200
-simulate_hp
[pattern_trace] 1 [pattern_trace] 1
[pattern_trace] 0 [pattern_trace] 0
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment