merged with framepars, version 0xca, fixed JPEG flush data (tail)

cocotb/x393_dut.v

@@ -40,6 +40,7 @@
  */
 `timescale 1ns/1ps
 `define COCOTB
+//`define DISABLE_SENSOR_2
 `include "system_defines.vh"
 module  x393_dut#(
 `include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - not used
@@ -1613,7 +1614,11 @@ simul_axi_hp_wr #(
         .new_bayer (0) //SENSOR12BITS_NEW_BAYER) was 1
     ) simul_sensor12bits_2_i (
         .MCLK  (PX2_MCLK), // input
+`ifdef DISABLE_SENSOR_2
         .MRST  (PX2_MRST & 0), // input // force reset !!!
+`else 
+        .MRST  (PX2_MRST), // input // force reset !!!
+`endif 
         .ARO   (PX2_ARO),  // input 
         .ARST  (PX2_ARST), // input 
         .OE    (1'b0),     // input output enable active low

compressor_jp/bit_stuffer_27_32.v

@@ -61,24 +61,30 @@ module  bit_stuffer_27_32#(
     
     reg         [5:0] early_length; // number of bits in the last word (mod 32)
     reg         [5:0] dlen1; // use for the stage 2, MSB - carry out
-    reg         [5:0] dlen2; // use for the stege 3
+    reg         [5:0] dlen2; // use for the stage 3
     
     reg        [31:0] dmask2_rom; // data mask (sync with data2) - 1 use new data, 0 - use old data. Use small ROM?
     
     reg         [1:0] stage; // delayed ds or flush
-    reg         [1:0] ds_stage;
+    //reg         [1:0] ds_stage;
     reg         [2:0] flush_stage;
+//    reg               flush_pend;
+//    wire              flush_ackn = flush_pend && !flush_stage[0] && !stage[0];
+    // probably just a single unconditional flush_in delay (not to appear next after ds) will work
     wire        [4:0] pre_bits_out_w = dlen2[4:0] + 5'h7; 
 
     assign d_out = data3[DATA3_LEN-1 -: 32];
     
     always @ (posedge xclk) begin
     
+//        if (rst) flush_pend <= 0;
+//        else     flush_pend <= flush_in || (flush_pend && !stage[0]);
+    
         if (rst) stage <= 0;
         else     stage <= {stage[0], ds | flush_in};
 
-        if (rst) ds_stage <= 0;
-        else     ds_stage <= {ds_stage[0], ds};
+//        if (rst) ds_stage <= 0;
+//        else     ds_stage <= {ds_stage[0], ds};
 
         if (rst) flush_stage <= 0;
         else     flush_stage <= {flush_stage[1:0], flush_in};
@@ -87,7 +93,8 @@ module  bit_stuffer_27_32#(
         else if (ds)         early_length <= early_length[4:0] + dlen; // early_length[5] is not used in calculations, it is just carry out
         
         if     (rst)              dlen1 <= 0;
-        else if (ds)       dlen1 <= early_length; // previous value
+//        else if (ds)       dlen1 <= early_length; // previous value
+        else if (ds || flush_in)  dlen1 <= early_length; // previous value
 
         if      (rst)        dlen2 <= 0;
         else if (stage[0])   dlen2 <= dlen1; // previous value (position)
@@ -95,6 +102,7 @@ module  bit_stuffer_27_32#(
 
         // barrel shifter stage 1 (0/8/16/24)
         if (rst) data1 <= 'bx;
+//        else if (flush_in) data1 <= 51'b0; // is it needed?
         else if (ds) case (early_length[4:3])
             2'h0: data1 <= {      din, 24'b0};
             2'h1: data1 <= { 8'b0,din, 16'b0};
@@ -104,6 +112,7 @@ module  bit_stuffer_27_32#(
     
         // barrel shifter stage 2 (0/2/4/6)
         if (rst) data2 <= 'bx;
+        else if (flush_stage[0]) data2 <= 0; // flush_stage[0] - equivalent of "if (flush_in) data1 <= 0;"
         else if (stage[0]) case (dlen1[2:1])
             2'h0: data2 <= {      data1, 6'b0};
             2'h1: data2 <= { 2'b0,data1, 4'b0};
@@ -148,20 +157,23 @@ module  bit_stuffer_27_32#(
         endcase
         // barrel shifter stage 3 (0/1), combined with output/hold register
         if (rst) data3 <= 'bx;
-        else if (ds_stage[1]) begin
+//        else if (ds_stage[1]) begin
+        else if (stage[1]) begin // flush causes shift too
             data3[DATA3_LEN-1 -: 32] <= (~dmask2_rom & (dlen2[5] ? {data3[DATA3_LEN-1-32 : 0],6'b0}: data3[DATA3_LEN-1 -: 32])) |
                                ( dmask2_rom & (dlen2[0] ? {1'b0,data2[DATA2_LEN-1 -: 31]} : data2[DATA2_LEN-1 -: 32]));
             data3[DATA3_LEN-1-32: 0] <= dlen2[0] ? data2[DATA2_LEN-31-1 : 0] : {data2[DATA2_LEN-32-1 : 0], 1'b0};
             
         end
-//        dv <= (ds_stage[1] && dlen2[5]) || (flush_stage[1] && !(|data3[DATA3_LEN-1 -: 32]));
-//        dv <= (ds_stage[1] && dlen1[5]) || (flush_stage[1] && !(|data3[DATA3_LEN-1 -: 32]));
-//        dv <= (ds_stage[0] && dlen1[5]) || (flush_stage[1] && !(|data3[DATA3_LEN-1 -: 32]));
-        dv <= (ds_stage[0] && dlen1[5]) || (flush_stage[1] && (|data3[DATA3_LEN-1 -: 32]));
+
+//        dv <= (ds_stage[0] && dlen1[5]) || (flush_stage[1] && (|data3[DATA3_LEN-1 -: 32]));
+        dv <= (stage[0] && dlen1[5]) || (flush_stage[1] && (|data3[DATA3_LEN-1 -: 32])); // both ds and flush-caused (full 32-bit out if available)
 // no difference in number of cells
 //        if      (rst )                bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes
 //        else if (ds_stage[1])         bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes
-        if  (rst || ds_stage[1]) bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes
+//        if  (rst || ds_stage[1]) bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes
+
+// bytes_out valid with dv
+        if      (rst || stage[0])     bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes
         else if (flush_stage[1])      bytes_out <= pre_bits_out_w[4:3];
     
         flush_out <= flush_stage[2];

fpga_version.vh

@@ -35,7 +35,10 @@
  * contains all the components and scripts required to completely simulate it
  * with at least one of the Free Software programs.
  */
-        parameter FPGA_VERSION =          32'h039300c7;      //parallel - disable SoF when channel disabled
+        parameter FPGA_VERSION =          32'h039300ca;      //parallel - and more ... -0.267/46, 80.42%
+//      parameter FPGA_VERSION =          32'h039300c9;      //parallel - trying more ...-0.123/32 79.82%
+//      parameter FPGA_VERSION =          32'h039300c8;      //parallel - trying to fix "premature..." -0.121/21, 80.2%
+//      parameter FPGA_VERSION =          32'h039300c7;      //parallel - disable SoF when channel disabled: met, 80.32%
 //      parameter FPGA_VERSION =          32'h039300c6;      //parallel - same -0.132 /31, 80.73%
 //      parameter FPGA_VERSION =          32'h039300c5;      //parallel - made i2c ahead of system frame number for eof -0.027/12 , 82.08%
 //      parameter FPGA_VERSION =          32'h039300c4;      //parallel - option to use EOF for i2c sequencer timing met, 79.66%

includes/x393_simulation_parameters.vh

@@ -61,10 +61,23 @@
 //    parameter SENSOR12BITS_NROWA   =     1,   // number of "blank rows" from last hact to end of vact
 //    parameter nAV   =      24,   //240;   // clocks from ARO to VACT (actually from en_dclkd)
 //    parameter SENSOR12BITS_NBPF =       20,   //16; // bpf length
-    parameter SENSOR_IMAGE_TYPE0 =       "RUN1", //"NORM", // "RUN1", "HIST_TEST"
-    parameter SENSOR_IMAGE_TYPE1 =       "RUN1",
-    parameter SENSOR_IMAGE_TYPE2 =       "RUN1", // "NORM", // "RUN1",
-    parameter SENSOR_IMAGE_TYPE3 =       "RUN1",
+
+
+
+//    parameter SENSOR_IMAGE_TYPE0 =       "RUN1", //"NORM", // "RUN1", "HIST_TEST"
+//    parameter SENSOR_IMAGE_TYPE1 =       "RUN1",
+//    parameter SENSOR_IMAGE_TYPE2 =       "NORM", // "RUN1", // "NORM", // "RUN1",
+//    parameter SENSOR_IMAGE_TYPE3 =       "NORM", // "RUN1",
+
+//    parameter SENSOR_IMAGE_TYPE0 =       "NORM1",
+//    parameter SENSOR_IMAGE_TYPE1 =       "NORM2",
+//    parameter SENSOR_IMAGE_TYPE2 =       "NORM3",
+//    parameter SENSOR_IMAGE_TYPE3 =       "NORM4",
+
+    parameter SENSOR_IMAGE_TYPE0 =       "NORM1",
+    parameter SENSOR_IMAGE_TYPE1 =       "NORM2",
+    parameter SENSOR_IMAGE_TYPE2 =       "NORM3", // 4",
+    parameter SENSOR_IMAGE_TYPE3 =       "NORM3",
     
     parameter SIMULATE_CMPRS_CMODE0 =     CMPRS_CBIT_CMODE_JPEG18,
     parameter SIMULATE_CMPRS_CMODE1 =     CMPRS_CBIT_CMODE_JPEG18,

py393/x393_jpeg.py

@@ -2293,7 +2293,7 @@ set_logger_params_file "/home/eyesis/git/x393-neon/attic/imu_config.bin"
 
 
 
-write_control_register 0x480  0x400 # disable sensor chn 2
+##### write_control_register 0x480  0x400 # disable sensor chn 2
 
 
 

simulation_modules/simul_sensor12bits.v

@@ -173,6 +173,14 @@ initial begin
     if      (SENSOR_IMAGE_TYPE == "NORM")      $readmemh({`ROOTPATH,"/input_data/sensor.dat"},sensor_data);
     else if (SENSOR_IMAGE_TYPE == "RUN1")      $readmemh({`ROOTPATH,"/input_data/sensor_run1.dat"},sensor_data);
     else if (SENSOR_IMAGE_TYPE == "HIST_TEST") $readmemh({`ROOTPATH,"/input_data/sensor_hist_test.dat"},sensor_data);
+    else if (SENSOR_IMAGE_TYPE == "NORM1")     $readmemh({`ROOTPATH,"/input_data/sensor_01.dat"},sensor_data);
+    else if (SENSOR_IMAGE_TYPE == "NORM2")     $readmemh({`ROOTPATH,"/input_data/sensor_02.dat"},sensor_data);
+    else if (SENSOR_IMAGE_TYPE == "NORM3")     $readmemh({`ROOTPATH,"/input_data/sensor_03.dat"},sensor_data);
+    else if (SENSOR_IMAGE_TYPE == "NORM4")     $readmemh({`ROOTPATH,"/input_data/sensor_04.dat"},sensor_data);
+    else if (SENSOR_IMAGE_TYPE == "NORM5")     $readmemh({`ROOTPATH,"/input_data/sensor_05.dat"},sensor_data);
+    else if (SENSOR_IMAGE_TYPE == "NORM6")     $readmemh({`ROOTPATH,"/input_data/sensor_06.dat"},sensor_data);
+    else if (SENSOR_IMAGE_TYPE == "NORM7")     $readmemh({`ROOTPATH,"/input_data/sensor_07.dat"},sensor_data);
+    else if (SENSOR_IMAGE_TYPE == "NORM8")     $readmemh({`ROOTPATH,"/input_data/sensor_08.dat"},sensor_data);
     else begin
        $display ("WARNING: Unrecognized sensor image :'%s', using default 'NORM': input_data/sensor.dat",SENSOR_IMAGE_TYPE);
        $readmemh({`ROOTPATH,"/input_data/sensor.dat"},sensor_data);