Commit 210ed954 authored by Andrey Filippov's avatar Andrey Filippov

removed most async resets

parent b721ae66
......@@ -404,10 +404,11 @@ module membridge#(
if (!rw_in_progress) buf_in_line64 <= 0;
else if (buf_rdwr) buf_in_line64 <= is_last_in_line? {(FRAME_WIDTH_BITS+1){1'b0}} : (buf_in_line64 +1);
next_page_rd <= next_page_rd_w;
next_page_wr <= next_page_wr_w;
if (hrst) next_page_rd <= 0;
else next_page_rd <= next_page_rd_w;
if (hrst) next_page_wr <= 0;
else next_page_wr <= next_page_wr_w;
end
......
......@@ -21,7 +21,7 @@
`timescale 1ns/1ps
module cmd_encod_4mux(
input rst,
input mrst,
input clk,
input start0, // this channel was started
......@@ -51,11 +51,11 @@ module cmd_encod_4mux(
);
reg [3:0] select;
wire start_w= start0 | start1 |start2 | start3;
always @ (posedge rst or posedge clk) begin
if (rst) start <= 0;
always @ (posedge clk) begin
if (mrst) start <= 0;
else start <= start_w;
if (rst) select <= 0;
if (mrst) select <= 0;
else if (start_w) select <={ // normally should be no simultaneous starts, so priority is not needed
start3 & ~start2 & ~start1 & ~start0,
start2 & ~start1 & ~start0,
......
......@@ -50,7 +50,7 @@ module cmd_encod_tiled_32_rd #(
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter RSEL= 1'b1 // Late/early READ commands
) (
input rst,
input mrst,
input clk,
// programming interface
input [2:0] start_bank, // bank address
......@@ -157,56 +157,57 @@ module cmd_encod_tiled_32_rd #(
assign pre_read= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command
always @ (posedge rst or posedge clk) begin
if (rst) gen_run <= 0;
always @ (posedge clk) begin
if (mrst) gen_run <= 0;
else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) num_rows_m1 <= 0;
if (mrst) num_rows_m1 <= 0;
else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
if (rst) num_cols128_m2 <= 0;
if (mrst) num_cols128_m2 <= 0;
else if (start) num_cols128_m2 <= num_cols_in_m1 & ~1; // number of r32-byte columns
if (rst) start_d <=0;
if (mrst) start_d <=0;
else start_d <= start;
if (rst) top_rc <= 0;
if (mrst) top_rc <= 0;
else if (start_d) top_rc <= {row,col}+2;
else if (pre_act && last_row) top_rc <= top_rc+2; // may increment RA
if (rst) row_col_bank <= 0;
if (mrst) row_col_bank <= 0;
else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?
else if (pre_act) row_col_bank <= row_col_bank_next_w;
if (rst) scan_row <= 0;
if (mrst) scan_row <= 0;
else if (start_d) scan_row <= 0;
else if (pre_act) scan_row <= last_row?0:scan_row+1;
if (rst) scan_col <= 0;
if (mrst) scan_col <= 0;
else if (start_d) scan_col <= 0;
else if (pre_act && last_row) scan_col <= scan_col+2; // for ACTIVATE, not for READ
if (rst) first_col <= 0;
if (mrst) first_col <= 0;
else if (start_d) first_col <= 1;
else if (pre_act && last_row) first_col <= 0;
if (rst) last_col <= 0;
if (mrst) last_col <= 0;
else if (start_d) last_col <= num_cols128_m2==0; // if single column - will start with 1'b1;
else if (pre_act) last_col <= (scan_col==num_cols128_m2); // too early for READ ?
if (rst) enable_autopre <= 0;
if (mrst) enable_autopre <= 0;
else if (start_d) enable_autopre <= 0;
else if (pre_act) enable_autopre <= last_col || !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column
if (rst) loop_continue<=0;
if (mrst) loop_continue<=0;
else loop_continue <= (scan_col==num_cols128_m2) && last_row;
if (rst) gen_addr <= 0;
if (mrst) gen_addr <= 0;
else if (!start_d && !gen_run) gen_addr <= 0;
else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter
else gen_addr <= gen_addr+1; // not in a loop
......@@ -222,8 +223,8 @@ module cmd_encod_tiled_32_rd #(
end
// ROM-based (registered output) encoded sequence
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
always @ (posedge clk) begin
if (mrst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_PAUSE_SHIFT); // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
......@@ -246,17 +247,15 @@ module cmd_encod_tiled_32_rd #(
default:rom_r <= 0;
endcase
end
always @ (posedge rst or posedge clk) begin
// if (rst) done <= 0;
// else done <= pre_done;
always @ (posedge clk) begin
if (rst) enc_wr <= 0;
if (mrst) enc_wr <= 0;
else enc_wr <= gen_run; // || gen_run_d;
if (rst) enc_done <= 0;
if (mrst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run; // !gen_run_d;
if (rst) enc_cmd <= 0;
if (mrst) enc_cmd <= 0;
// else if ((rom_cmd==0) || (rom_cmd[1] && !enable_act)) enc_cmd <= func_encode_skip ( // encode pause
else if (gen_run) begin
if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
......@@ -300,13 +299,13 @@ module cmd_encod_tiled_32_rd #(
fifo_2regs #(
.WIDTH(COLADDR_NUMBER)
) fifo_2regs_i (
.rst (rst), // input
.mrst (mrst), // input
.clk (clk), // input
.din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0]
.wr(pre_act), // input
.rd(pre_read && !rom_r[ENC_NOP]), // input - update only after the second READ
.srst(start_d), // input
.dout(col_bank) // output[15:0]
.wr (pre_act), // input
.rd (pre_read && !rom_r[ENC_NOP]), // input - update only after the second READ
.srst (start_d), // input
.dout (col_bank) // output[15:0]
);
`include "includes/x393_mcontr_encode_cmd.vh"
......
......@@ -30,7 +30,7 @@ module cmd_encod_tiled_32_rw #(
parameter WSEL= 1'b0 // late/early WRITE commands (to adjust timing by 1 SDCLK period)
) (
input rst,
input mrst,
input clk,
// programming interface
input [2:0] start_bank, // bank address
......@@ -63,7 +63,7 @@ module cmd_encod_tiled_32_rw #(
.CMD_DONE_BIT (CMD_DONE_BIT),
.RSEL (RSEL)
) cmd_encod_tiled_rd_i (
.rst (rst), // input
.mrst (mrst), // input
.clk (clk), // input
.start_bank (start_bank), // input[2:0]
.start_row (start_row), // input[14:0]
......@@ -87,7 +87,7 @@ module cmd_encod_tiled_32_rw #(
.CMD_DONE_BIT (CMD_DONE_BIT),
.WSEL (WSEL)
) cmd_encod_tiled_wr_i (
.rst (rst), // input
.mrst (mrst), // input
.clk (clk), // input
.start_bank (start_bank), // input[2:0]
.start_row (start_row), // input[14:0]
......@@ -104,11 +104,11 @@ module cmd_encod_tiled_32_rw #(
.enc_done (enc_done_wr) // output reg
);
always @(posedge rst or posedge clk) begin
if (rst) start <= 0;
always @(posedge clk) begin
if (mrst) start <= 0;
else start <= start_rd || start_wr;
if (rst) select_wr <= 0;
if (mrst) select_wr <= 0;
else if (start_rd) select_wr <= 0;
else if (start_wr) select_wr <= 1;
end
......
......@@ -50,7 +50,7 @@ module cmd_encod_tiled_32_wr #(
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter WSEL= 1'b0
) (
input rst,
input mrst,
input clk,
// programming interface
input [2:0] start_bank, // bank address
......@@ -164,57 +164,54 @@ module cmd_encod_tiled_32_wr #(
assign pre_write= rom_r[ENC_CMD_SHIFT]; //1 cycle before READ command
always @ (posedge rst or posedge clk) begin
if (rst) gen_run <= 0;
always @ (posedge clk) begin
if (mrst) gen_run <= 0;
else if (start_d) gen_run<= 1; // delaying
else if (pre_done) gen_run<= 0;
// if (rst) gen_run_d <= 0;
// else gen_run_d <= gen_run;
if (rst) num_rows_m1 <= 0;
if (mrst) num_rows_m1 <= 0;
else if (start) num_rows_m1 <= num_rows_in_m1; // number of rows
if (rst) num_cols128_m1 <= 0;
if (mrst) num_cols128_m1 <= 0;
else if (start) num_cols128_m1 <= num_cols_in_m1 & ~1; // number of r16-byte columns (without LSB - number of 32-byte columns)
if (rst) start_d <=0;
if (mrst) start_d <=0;
else start_d <= start;
if (rst) top_rc <= 0;
if (mrst) top_rc <= 0;
else if (start_d) top_rc <= {row,col}+2;
else if (pre_act && last_row) top_rc <= top_rc+2; // may increment RA
if (rst) row_col_bank <= 0;
if (mrst) row_col_bank <= 0;
else if (start_d) row_col_bank <= {row,col,bank}; // TODO: Use start_col,... and start, not start_d?
else if (pre_act) row_col_bank <= row_col_bank_next_w;
if (rst) scan_row <= 0;
if (mrst) scan_row <= 0;
else if (start_d) scan_row <= 0;
else if (pre_act) scan_row <= last_row?0:scan_row+1;
if (rst) scan_col <= 0;
if (mrst) scan_col <= 0;
else if (start_d) scan_col <= 0;
else if (pre_act && last_row) scan_col <= scan_col+2; // for ACTIVATE, not for READ
if (rst) first_col <= 0;
if (mrst) first_col <= 0;
else if (start_d) first_col <= 1;
else if (pre_act && last_row) first_col <= 0;
if (rst) last_col <= 0;
if (mrst) last_col <= 0;
else if (start_d) last_col <= num_cols128_m1==0; // if single column - will start with 1'b1;
else if (pre_act) last_col <= (scan_col==num_cols128_m1); // too early for READ ?
if (rst) enable_autopre <= 0;
if (mrst) enable_autopre <= 0;
else if (start_d) enable_autopre <= 0;
else if (pre_act) enable_autopre <= last_col || !keep_open; // delayed by 2 pre_act tacts form last_col, OK with a single column
if (rst) loop_continue<=0;
if (mrst) loop_continue<=0;
else loop_continue <= (scan_col==num_cols128_m1) && last_row;
if (rst) gen_addr <= 0;
if (mrst) gen_addr <= 0;
else if (!start_d && !gen_run) gen_addr <= 0;
else if ((gen_addr==LOOP_LAST) && !loop_continue) gen_addr <= LOOP_FIRST; // skip loop alltogeter
else gen_addr <= gen_addr+1; // not in a loop
......@@ -230,8 +227,8 @@ module cmd_encod_tiled_32_wr #(
end
// ROM-based (registered output) encoded sequence
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
always @ (posedge clk) begin
if (mrst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ; // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) ;
......@@ -256,17 +253,15 @@ module cmd_encod_tiled_32_wr #(
endcase
end
always @ (posedge rst or posedge clk) begin
// if (rst) done <= 0;
// else done <= pre_done;
always @ (posedge clk) begin
if (rst) enc_wr <= 0;
if (mrst) enc_wr <= 0;
else enc_wr <= gen_run; // || gen_run_d; *****
if (rst) enc_done <= 0;
if (mrst) enc_done <= 0;
else enc_done <= enc_wr && !gen_run; // !gen_run_d; *****
if (rst) enc_cmd <= 0;
if (mrst) enc_cmd <= 0;
else if (gen_run) begin
if (rom_cmd[0] || (rom_cmd[1] && enable_act)) enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]? // activate
......@@ -311,7 +306,7 @@ module cmd_encod_tiled_32_wr #(
fifo_2regs #(
.WIDTH(COLADDR_NUMBER)
) fifo_2regs_i (
.rst (rst), // input
.mrst (mrst), // input
.clk (clk), // input
.din (row_col_bank[COLADDR_NUMBER-1:0]), // input[15:0]
.wr(pre_act), // input
......
......@@ -389,19 +389,6 @@ module mcntrl393 #(
localparam COL_WDTH = COLADDR_NUMBER-3; // number of column address bits in bursts
localparam FRAME_WBP1 = FRAME_WIDTH_BITS + 1;
wire rrst=rst_in;
wire axi_rst=rst_in;
// Not yet connected
// wire [7:0] status_other_ad; // Other status byte-wide address/data
// wire status_other_rq; // Other status request
// wire status_other_start; // Other status packet transfer start (currently with 0 latency from status_root_rq)
//cmd_ps_pio_stb
// command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ...
// TODO: move to internal !
// Interface to channels to read/write memory (including 4 page BRAM buffers)
wire want_rq0;
......@@ -767,37 +754,33 @@ module mcntrl393 #(
assign select_buf4rd_w = ((axird_pre_araddr ^ MCONTR_BUF4_RD_ADDR) & MCONTR_RD_MASK)==0;
assign select_buf4wr_w = ((axiwr_pre_awaddr ^ MCONTR_BUF4_WR_ADDR) & MCONTR_WR_MASK)==0;
always @ (posedge axi_rst or posedge axi_clk) begin
if (axi_rst) select_cmd0 <= 0;
always @ (posedge axi_clk) begin
if (mrst) select_cmd0 <= 0;
else if (axiwr_start_burst) select_cmd0 <= select_cmd0_w;
if (axi_rst) select_buf0rd <= 0;
if (mrst) select_buf0rd <= 0;
else if (axird_start_burst) select_buf0rd <= select_buf0rd_w;
if (axi_rst) select_buf0wr <= 0;
else if (axiwr_start_burst) select_buf0wr <= select_buf0wr_w;
// if (axi_rst) select_buf1rd <= 0; // not used - replaced with membridge
// else if (axird_start_burst) select_buf1rd <= select_buf1rd_w; // not used - replaced with membridge
// if (axi_rst) select_buf1wr <= 0; // not used - replaced with membridge
// else if (axiwr_start_burst) select_buf1wr <= select_buf1wr_w; // not used - replaced with membridge
if (mrst) select_buf0wr <= 0;
else if (axiwr_start_burst) select_buf0wr <= select_buf0wr_w;
if (axi_rst) select_buf2rd <= 0;
if (mrst) select_buf2rd <= 0;
else if (axird_start_burst) select_buf2rd <= select_buf2rd_w;
if (axi_rst) select_buf2wr <= 0;
if (mrst) select_buf2wr <= 0;
else if (axiwr_start_burst) select_buf2wr <= select_buf2wr_w;
if (axi_rst) select_buf3rd <= 0;
if (mrst) select_buf3rd <= 0;
else if (axird_start_burst) select_buf3rd <= select_buf3rd_w;
if (axi_rst) select_buf3wr <= 0;
if (mrst) select_buf3wr <= 0;
else if (axiwr_start_burst) select_buf3wr <= select_buf3wr_w;
if (axi_rst) select_buf4rd <= 0;
if (mrst) select_buf4rd <= 0;
else if (axird_start_burst) select_buf4rd <= select_buf4rd_w;
if (axi_rst) select_buf4wr <= 0;
if (mrst) select_buf4wr <= 0;
else if (axiwr_start_burst) select_buf4wr <= select_buf4wr_w;
if (axi_rst) axird_selected_r <= 0;
if (mrst) axird_selected_r <= 0;
else if (axird_start_burst) axird_selected_r <= select_buf0rd_w || //select_buf1rd_w || // not used - replaced with membridge
select_buf2rd_w || select_buf3rd_w || select_buf4rd_w;
end
......@@ -1618,7 +1601,7 @@ module mcntrl393 #(
.RSEL (RSEL),
.WSEL (WSEL)
) cmd_encod_tiled_32_rw_i (
.rst (rst), // input
.mrst (mrst), // input
.clk (mclk), // input
.start_bank (tiled_rw_bank), // input[2:0]
.start_row (tiled_rw_row), // input[14:0]
......@@ -1638,7 +1621,7 @@ module mcntrl393 #(
// Combine sequencer data from multiple sources
cmd_encod_4mux cmd_encod_4mux_i (
.rst (rst), // input
.mrst (mrst), // input
.clk (mclk), // input
// from ps pio
.start0 (channel_pgm_en0), // start_seq_ps_pio), // input
......@@ -1646,7 +1629,7 @@ module mcntrl393 #(
.enc_wr0 (1'b0), // input
.enc_done0 (seq_set0), // input
// from encod_linear_rw
.start1 (encod_linear_start_out), // input
.start1 (encod_linear_start_out) , // input
.enc_cmd1 (encod_linear_cmd), // input[31:0]
.enc_wr1 (encod_linear_wr), // input
.enc_done1 (encod_linear_done), // input
......@@ -1766,11 +1749,11 @@ module mcntrl393 #(
.channel_pgm_en0 (channel_pgm_en0), // output reg
.seq_done0 (seq_done0), // output
.page_nxt_chn0 (), //rpage_nxt_chn0), not used
.buf_run0 (buf_run0),
.buf_run0 (buf_run0), // output
.buf_wr_chn0 (buf_wr_chn0), // output
.buf_wpage_nxt_chn0 (buf_wpage_nxt_chn0), // output
.buf_wdata_chn0 (buf_wdata_chn0), // output[63:0]
.buf_wrun0 (buf_wrun0),
.buf_wrun0 (buf_wrun0), // output
.buf_rd_chn0 (buf_rd_chn0), // output
.buf_rpage_nxt_chn0 (buf_rpage_nxt_chn0), // output
.buf_rdata_chn0 (buf_rdata_chn0), // input[63:0]
......@@ -1780,26 +1763,25 @@ module mcntrl393 #(
.channel_pgm_en1 (channel_pgm_en1), // output reg
.seq_done1 (seq_done1), // output
.page_nxt_chn1 (page_ready_chn1), //rpage_nxt_chn0), not used
.buf_run1 (), //buf_run1),
.buf_run1 (), // output
.buf_wr_chn1 (buf_wr_chn1), // output
.buf_wpage_nxt_chn1 (buf_wpage_nxt_chn1), // output
.buf_wdata_chn1 (buf_wdata_chn1), // output[63:0]
.buf_wrun1 (), //buf_wrun1),
.buf_wrun1 (), // output//buf_wrun1),
.buf_rd_chn1 (buf_rd_chn1), // output
.buf_rpage_nxt_chn1 (rpage_nxt_chn1), // buf_rpage_nxt_chn1), // output
.buf_rdata_chn1 (buf_rdata_chn1), // input[63:0]
.want_rq2 (want_rq2), // input
.need_rq2 (need_rq2), // input
.channel_pgm_en2 (channel_pgm_en2), // output reg
.seq_done2 (seq_done2), // output
.page_nxt_chn2 (page_ready_chn2), //rpage_nxt_chn0), not used
.buf_run2 (), //buf_run2),
.buf_run2 (), // output //buf_run2),
.buf_wr_chn2 (buf_wr_chn2), // output
.buf_wpage_nxt_chn2 (buf_wpage_nxt_chn2), // output
.buf_wdata_chn2 (buf_wdata_chn2), // output[63:0]
.buf_wrun2 (), //buf_wrun2),
.buf_wrun2 (), // output//buf_wrun2),
.buf_rd_chn2 (buf_rd_chn2), // output
.buf_rpage_nxt_chn2 (rpage_nxt_chn2), // buf_rpage_nxt_chn2), // output
.buf_rdata_chn2 (buf_rdata_chn2), // input[63:0]
......@@ -1809,11 +1791,11 @@ module mcntrl393 #(
.channel_pgm_en3 (channel_pgm_en3), // output reg
.seq_done3 (seq_done3), // output
.page_nxt_chn3 (page_ready_chn3), //rpage_nxt_chn0), not used
.buf_run3 (), //buf_run3),
.buf_run3 (), // output//buf_run3),
.buf_wr_chn3 (buf_wr_chn3), // output
.buf_wpage_nxt_chn3 (buf_wpage_nxt_chn3), // output
.buf_wdata_chn3 (buf_wdata_chn3), // output[63:0]
.buf_wrun3 (), //buf_wrun3),
.buf_wrun3 (), // output //buf_wrun3),
.buf_rd_chn3 (buf_rd_chn3), // output
.buf_rpage_nxt_chn3 (rpage_nxt_chn3), // buf_rpage_nxt_chn3), // output
.buf_rdata_chn3 (buf_rdata_chn3), // input[63:0]
......@@ -1823,11 +1805,11 @@ module mcntrl393 #(
.channel_pgm_en4 (channel_pgm_en4), // output reg
.seq_done4 (seq_done4), // output
.page_nxt_chn4 (page_ready_chn4), //rpage_nxt_chn0), not used
.buf_run4 (), //buf_run4),
.buf_run4 (), // output //buf_run4),
.buf_wr_chn4 (buf_wr_chn4), // output
.buf_wpage_nxt_chn4 (buf_wpage_nxt_chn4), // output
.buf_wdata_chn4 (buf_wdata_chn4), // output[63:0]
.buf_wrun4 (), //buf_wrun4),
.buf_wrun4 (), // output//buf_wrun4),
.buf_rd_chn4 (buf_rd_chn4), // output
.buf_rpage_nxt_chn4 (rpage_nxt_chn4), // buf_rpage_nxt_chn4), // output
.buf_rdata_chn4 (buf_rdata_chn4), // input[63:0]
......
......@@ -529,19 +529,16 @@ module memctrl16 #(
// temporary debug data
,output [11:0] tmp_debug // add some signals generated here?
);
//wire rst=rst_in; // TODO: decide where to generate
wire ext_buf_rd;
wire ext_buf_rpage_nxt;
wire ext_buf_page_nxt;
// wire [6:0] ext_buf_raddr;
wire [3:0] ext_buf_rchn;
wire ext_buf_rrefresh;
wire ext_buf_rrun; // run read sequence (to be used with external buffer to set initial address
reg [63:0] ext_buf_rdata;
wire ext_buf_wr;
wire ext_buf_wpage_nxt;
// wire [6:0] ext_buf_waddr;
wire [3:0] ext_buf_wchn;
wire ext_buf_wrefresh;
wire ext_buf_wrun; // @negedge,first cycle of sequencer run matching write delay
......
......@@ -224,22 +224,16 @@ module mcontr_sequencer #(
wire [31:0] phy_cmd1_word; // cmd1 buffer output
reg buf_raddr_reset;
reg buf_addr_reset; // generated regardless of read/write
// reg [ 6:0] buf_raddr;
reg buf_waddr_reset_negedge;
// reg [ 6:0] buf_waddr_negedge;
reg buf_wr_negedge;
wire [63:0] buf_wdata; // output[63:0]
reg [63:0] buf_wdata_negedge; // output[63:0]
wire [63:0] buf_rdata; // multiplexed input from one of the write channels buffer
// wire [63:0] buf1_rdata;
wire buf_wr; // delayed by specified number of clock cycles
wire buf_wr_ndly; // before dealy
wire buf_rd; // read next 64 bits from the buffer, need one extra pre-read
wire buf_rst; // reset buffer address to
wire buf_rst_d; //buf_rst delayed to match buf_wr
// wire rst=rst_in;
// wire [ 9:0] next_cmd_addr;
reg [ 9:0] cmd_addr; // command word address
reg cmd_sel;
reg [ 2:0] cmd_busy; // bit 0 - immediately,
......@@ -252,8 +246,6 @@ module mcontr_sequencer #(
wire pause; // do not register new data from the command memory
reg [CMD_PAUSE_BITS-1:0] pause_cntr;
// reg [1:0] buf_page; // one of 4 pages in the channel buffer to use for R/W
// reg [15:0] buf_sel_1hot; // 1 hot channel buffer select
wire [3:0] run_chn_w_d; // run chn delayed to match buf_wr delay
wire run_refresh_w_d; // run refresh delayed to match buf_wr delay
wire run_w_d;
......
......@@ -27,6 +27,9 @@ module clocks393#(
parameter CLK_CNTRL = 0,
parameter CLK_STATUS = 1,
parameter CLK_RESET = 'h0, // which clocks should stay reset after release of masrter reset {ff1,ff0,mem,sync,xclk,pclk,xclk}
parameter CLK_PWDWN = 'h0, // which clocks should stay powered down after release of masrter reset {sync,xclk,pclk,xclk}
parameter CLKIN_PERIOD_AXIHP = 20, //ns >1.25, 600<Fvco<1200
parameter DIVCLK_DIVIDE_AXIHP = 1,
parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
......@@ -80,7 +83,7 @@ module clocks393#(
parameter FFCLK1_IOSTANDARD = "DEFAULT"
)(
// input rst,
input async_rst, // always reset MMCM/PLL
input mclk, // global clock, comes from the memory controller (uses aclk generated here)
input mrst,
// command/status interface
......@@ -103,7 +106,11 @@ module clocks393#(
output xclk2x, // global clock for compressor, 2x frequency (now 200MHz)
output sync_clk, // global clock for camsync module (96 MHz for 353 compatibility - switch to 100MHz)?
output time_ref, // non-global, just RTC (currently just mclk/8 = 25 MHz)
input [1:0] extra_status // just extra two status bits from the top module
input [1:0] extra_status, // just extra two status bits from the top module
output locked_sync_clk,
output locked_xclk,
output locked_pclk,
output locked_hclk
);
wire memclk;
wire ffclk0;
......@@ -116,23 +123,29 @@ module clocks393#(
wire set_ctrl_w = cmd_we & ((cmd_a && CLK_MASK) == CLK_CNTRL);
wire set_status_w = cmd_we & ((cmd_a && CLK_MASK) == CLK_STATUS);
wire [3:0] locked;
reg [6:0] reset_clk = 0;
reg [3:0] pwrdwn_clk = 0;
reg [6:0] reset_clk = CLK_RESET;
reg [3:0] pwrdwn_clk = CLK_PWDWN;
reg [2:0] test_clk; // FF to test input clocks are running
wire memclk_rst = reset_clk[4];
wire ffclk0_rst = reset_clk[5];
wire ffclk1_rst = reset_clk[6];
assign locked_sync_clk = locked[3];
assign locked_xclk = locked[2];
assign locked_pclk = locked[1];
assign locked_hclk = locked[0];
always @ (posedge mclk) begin
if (mrst) reset_clk <= 0;
if (mrst) reset_clk <= CLK_RESET;
else if (set_ctrl_w) reset_clk <= {cmd_data[10:8], cmd_data[3:0]};
if (mrst) pwrdwn_clk <= 0;
if (mrst) pwrdwn_clk <= CLK_PWDWN;
else if (set_ctrl_w) pwrdwn_clk <= cmd_data[7:4];
end
assign status_data = {test_clk, locked, extra_status};
always @ (posedge memclk or posedge memclk_rst) if (memclk_rst) test_clk[0] <= 0; else test_clk[0] <= ~test_clk[0];
always @ (posedge ffclk0 or posedge ffclk0_rst) if (ffclk0_rst) test_clk[1] <= 0; else test_clk[1] <= ~test_clk[1];
always @ (posedge ffclk1 or posedge ffclk1_rst) if (ffclk1_rst) test_clk[2] <= 0; else test_clk[2] <= ~test_clk[2];
always @ (posedge memclk or posedge memclk_rst) if (async_rst || memclk_rst) test_clk[0] <= 0; else test_clk[0] <= ~test_clk[0];
always @ (posedge ffclk0 or posedge ffclk0_rst) if (async_rst || ffclk0_rst) test_clk[1] <= 0; else test_clk[1] <= ~test_clk[1];
always @ (posedge ffclk1 or posedge ffclk1_rst) if (async_rst || ffclk1_rst) test_clk[2] <= 0; else test_clk[2] <= ~test_clk[2];
cmd_deser #(
.ADDR (CLK_ADDR),
......@@ -177,7 +190,7 @@ module clocks393#(
.BUF_CLK1X (BUF_CLK1X_AXIHP),
.BUF_CLK2X ("NONE")
) dual_clock_axihp_i (
.rst (reset_clk[0]), // input
.rst (async_rst || reset_clk[0]), // input
.clk_in (aclk), // input
.pwrdwn (pwrdwn_clk[0]), // input
.clk1x (hclk), // output
......@@ -195,7 +208,7 @@ module clocks393#(
.BUF_CLK1X (BUF_CLK1X_PCLK),
.BUF_CLK2X (BUF_CLK1X_PCLK2X)
) dual_clock_pclk_i (
.rst (reset_clk[1]), // input
.rst (async_rst || reset_clk[1]), // input
.clk_in (ffclk0), // input
.pwrdwn (pwrdwn_clk[1]), // input
.clk1x (pclk), // output
......@@ -213,7 +226,7 @@ module clocks393#(
.BUF_CLK1X (BUF_CLK1X_XCLK),
.BUF_CLK2X (BUF_CLK1X_XCLK2X)
) dual_clock_xclk_i (
.rst (reset_clk[2]), // input
.rst (async_rst || reset_clk[2]), // input
.clk_in (aclk), // input
.pwrdwn (pwrdwn_clk[2]), // input
.clk1x (xclk), // output
......@@ -229,7 +242,7 @@ module clocks393#(
.BUF_CLK1X (BUF_CLK1X_SYNC),
.BUF_CLK2X ("NONE")
) dual_clock_sync_clk_i (
.rst (reset_clk[3]), // input
.rst (async_rst || reset_clk[3]), // input
.clk_in (aclk), // input
.pwrdwn (pwrdwn_clk[3]), // input
.clk1x (sync_clk), // output
......@@ -280,7 +293,7 @@ module clocks393#(
// RTC reference: integer number of microseconds, less than mclk/2. Not a global clock
// temporary:
reg [2:0] time_ref_r;
always @ (posedge mclk or posedge rst) if (rst) time_ref_r <= 0; else time_ref_r <= time_ref_r + 1;
always @ (posedge mclk) if (mrst) time_ref_r <= 0; else time_ref_r <= time_ref_r + 1;
assign time_ref = time_ref_r[2];
endmodule
......
/*******************************************************************************
* Module: sync_resets
* Date:2015-07-20
* Author: Aandrey Filippov
* Description: Generate synchronous resets for several clocks, leaving room
* for generous register duplication
*
* Copyright (c) 2015 Elphel, Inc .
* sync_resets.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sync_resets.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module sync_resets#(
parameter WIDTH = 1,
parameter REGISTER = 4 // number of registers used at crossing clocks >1
)(
input arst, // async reset
input [WIDTH-1:0] locked, // clk[i] MMCM/PLL is locked
input [WIDTH-1:0] clk, // clk[0] - master clock generation should not depend on resets)
output [WIDTH-1:0] rst // resets matching input clocks
);
wire [WIDTH-1:0] rst_w; // resets matching input clocks
wire rst_early_master;
assign rst = rst_w;
reg mrst = 1;
always @ (posedge arst or posedge clk[0]) begin
if (arst) mrst <= 1;
else mrst <= ~locked[0];
end