co-debugging simulation with hardware tests to make them match (1e313eb7) · Commits · Elphel / x393

includes/x393_localparams.vh

+5 −41

Original line number	Diff line number	Diff line
		@@ -27,44 +27,9 @@
		localparam LD_DLY_CMDA = DLY_LD+'h40; // 0x10c0
		localparam LD_DLY_PHASE = DLY_LD+'h60; // 0x10e0
		localparam DLY_SET = MCONTR_PHY_0BIT_ADDR + MCONTR_PHY_0BIT_DLY_SET; //0x1020
		// different sets of settings for the functional simulation and the actual hardware
		`ifdef TARGET_MODE
		// different sets of settings for the functional simulation and the actual hardware - should not be needed anymore
		localparam T_RFC=50; // t_rfc=50 for tCK=2.5ns
		localparam T_REFI=48; // t_refi; # 48/97 for normal, 8 - for simulation (7.8us <85C, 3.9us >85C)
		`ifdef use200Mhz
		// localparam DLY_LANE0_ODELAY= 80'hd8a0d8d4dae0d4dcdbd9; // odelay dqm, odelay dqs, odelay dq[7:0]
		// localparam DLY_LANE0_IDELAY= 72'h40989c9aa4949898a4; // idelay dqs, idelay dq[7:0]
		// localparam DLY_LANE1_ODELAY= 80'hd8a0dcdcdce0dcf1e0dc; // odelay dqm, odelay dqs, odelay dq[7:0]
		// localparam DLY_LANE1_IDELAY= 72'h40aca8aaa8b4acb1ac; // idelay dqs, idelay dq[7:0]
		// localparam DLY_CMDA= 256'h8080808080808080808080808080808080808080808080808080808080808080; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
		// localparam DLY_PHASE= 8'h4c; // mmcm fine phase shift, 1/4 tCK
		`else
		// localparam DLY_LANE0_ODELAY= 80'h7474737271706c6b6a69; // odelay dqm, odelay ddqs, odelay dq[7:0]
		// localparam DLY_LANE0_IDELAY= 72'hd8737271706c6b6a69; // idelay dqs, idelay dq[7:0
		// localparam DLY_LANE1_ODELAY= 80'h7474737271706c6b6a69; // odelay dqm, odelay ddqs, odelay dq[7:0]
		// localparam DLY_LANE1_IDELAY= 72'hd8737271706c6b6a69; // idelay dqs, idelay dq[7:0
		// localparam DLY_CMDA= 256'h5c5c5c5c5b5a59585454545453525150004c4c4c4b4a49484444444443424140; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
		// localparam DLY_PHASE= 8'h4c; // mmcm fine phase shift, 1/4 tCK
		`endif
		`else
		localparam T_RFC=50; // t_rfc=50 for tCK=2.5ns
		localparam T_REFI=16; // t_refi; # 48/97 for normal, 8 - for simulation (7.8us <85C, 3.9us >85C)
		`ifdef use200Mhz
		// localparam DLY_LANE0_ODELAY= 80'h4c784b4a494844434241; // odelay dqm, odelay ddqs, odelay dq[7:0]
		// localparam DLY_LANE0_IDELAY= 72'ha0636261605c5b5a59; // idelay dqs, idelay dq[7:0
		// localparam DLY_LANE1_ODELAY= 80'h4c784b4a494844434241; // odelay dqm, odelay ddqs, odelay dq[7:0]
		// localparam DLY_LANE1_IDELAY= 72'ha0636261605c5b5a59; // idelay dqs, idelay dq[7:0
		// localparam DLY_CMDA= 256'h3c3c3c3c3b3a39383434343433323130002c2c2c2b2a29282424242423222120; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
		// localparam DLY_PHASE= 8'h1c; // mmcm fine phase shift, 1/4 tCK
		`else
		// localparam DLY_LANE0_ODELAY= 80'h7474737271706c6b6a69; // odelay dqm, odelay ddqs, odelay dq[7:0]
		// localparam DLY_LANE0_IDELAY= 72'hd8737271706c6b6a69; // idelay dqs, idelay dq[7:0
		// localparam DLY_LANE1_ODELAY= 80'h7474737271706c6b6a69; // odelay dqm, odelay ddqs, odelay dq[7:0]
		// localparam DLY_LANE1_IDELAY= 72'hd8737271706c6b6a69; // idelay dqs, idelay dq[7:0
		// localparam DLY_CMDA= 256'h5c5c5c5c5b5a59585454545453525150004c4c4c4b4a49484444444443424140; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
		// localparam DLY_PHASE= 8'h1c; // mmcm fine phase shift, 1/4 tCK
		`endif
		`endif

		// alternative to set same type delays to the same value
		localparam DLY_DQ_IDELAY = ( (DLY_LANE0_IDELAY & 8'hff)+
		@@ -131,14 +96,13 @@
		localparam DLY_LANE0_DQS_WLV_IDELAY = DLY_DQS_IDELAY; // b0; // idelay dqs
		localparam DLY_LANE1_DQS_WLV_IDELAY = DLY_DQS_IDELAY; // b0; idelay dqs

		localparam DQSTRI_FIRST= 4'h3; // DQS tri-state control word, first when enabling output
		localparam DQSTRI_FIRST= 4'h1; // 3; // DQS tri-state control word, first when enabling output
		localparam DQSTRI_LAST= 4'hc; // DQS tri-state control word, first after disabling output
		localparam DQTRI_FIRST= 4'h7; // DQ tri-state control word, first when enabling output
		localparam DQTRI_FIRST= 4'h3; // 7; // DQ tri-state control word, first when enabling output
		localparam DQTRI_LAST= 4'he; // DQ tri-state control word, first after disabling output
		localparam WBUF_DLY_DFLT= DFLT_WBUF_DELAY; // 4'h8; // 4'h6; // extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
		localparam WBUF_DLY_WLV= DFLT_WBUF_DELAY; // 4'h7; // write leveling mode: extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)

		// localparam DLY_PHASE= 8'hdb; // mmcm fine phase shift
		localparam INITIALIZE_OFFSET= 'h00; // moemory initialization start address (in words) ..`h0c
		localparam REFRESH_OFFSET= 'h10; // refresh start address (in words) ..`h13
		localparam WRITELEV_OFFSET= 'h20; // write leveling start address (in words) ..`h2a

includes/x393_tasks_pio_sequences.vh

+15 −12

Original line number	Diff line number	Diff line
		@@ -31,6 +31,7 @@ task set_read_block;
		input [ 2:0] ba;
		input [14:0] ra;
		input [ 9:0] ca;
		input sel;
		reg [29:0] cmd_addr;
		reg [31:0] data;
		integer i;
		@@ -47,11 +48,11 @@ task set_read_block;
		// first read
		// read
		// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
		data <= func_encode_cmd( {5'b0,ca[9:0]}, ba[2:0], 2, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0);
		data <= func_encode_cmd( {5'b0,ca[9:0]}, ba[2:0], 2, 0, 0, sel, 0, 0, 0, 1, 1, 0, 0, 0);
		@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
		// nop
		// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
		data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 1, 0, 0);
		data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, sel, 0, 0, 0, 1, 1, 0, 0);
		@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
		//repeat remaining reads
		for (i=1;i<64;i=i+1) begin
		@@ -62,15 +63,15 @@ task set_read_block;
		end
		// nop - all 3 below are the same? - just repeat?
		// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
		data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
		data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, sel, 0, 0, 0, 1, 0, 0, 0);
		@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
		// nop
		// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
		data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
		data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, sel, 0, 0, 0, 1, 0, 0, 0);
		@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
		// nop
		// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
		data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
		data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, sel, 0, 0, 0, 1, 0, 0, 0);
		@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
		// tRTP = 4*tCK is already satisfied, no skip here
		// precharge, end of a page (B_RST)
		@@ -91,6 +92,7 @@ task set_write_block;
		input[2:0]ba;
		input[14:0]ra;
		input[9:0]ca;
		input sel;
		reg[29:0] cmd_addr;
		reg[31:0] data;
		integer i;
		@@ -107,31 +109,32 @@ task set_write_block;
		// first write, 3 rd_buf
		// write
		// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
		data <= func_encode_cmd( {5'b0,ca[9:0]}, ba[2:0], 3, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0); // B_RD moved 1 cycle earlier
		data <= func_encode_cmd( {5'b0,ca[9:0]}, ba[2:0], 3, 1, 0, sel, 0, 0, 0, 0, 0, 1, 0, 0); // B_RD moved 1 cycle earlier
		@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
		// nop 4-th rd_buf
		// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
		// data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 1, 1, 1, 0, 1, 0, 1, 0);
		data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 0, 1, 1, 0, 0, 0, 1, 0);
		// data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 0, 1, 1, 0, 0, 0, 1, 0);
		data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 0, 0, 0, 0, 0, 0, 1, 0);
		@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
		//repeat remaining writes
		for (i = 1; i < 62; i = i + 1) begin
		// write
		// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
		data <= func_encode_cmd( {5'b0,ca[9:0]}+(i<<3),ba[2:0],3, 1, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0);
		data <= func_encode_cmd( {5'b0,ca[9:0]}+(i<<3),ba[2:0],3, 1, 0, sel, 1, 1, 1, 0, 0, 1, 1, 0);
		@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
		end
		// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
		data <= func_encode_cmd( {5'b0,ca[9:0]}+(62<<3),ba[2:0], 3, 1, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0); // write w/o nop
		data <= func_encode_cmd( {5'b0,ca[9:0]}+(62<<3),ba[2:0], 3, 1, 0, sel, 1, 1, 1, 0, 0, 1, 0, 0); // write w/o nop
		@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
		// nop
		// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
		data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 1, 1, 1, 1, 0, 0, 0, 0); // nop with buffer read off
		data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, sel, 1, 1, 1, 0, 0, 0, 0); // nop with buffer read off
		@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;

		// One last write pair w/o buffer
		// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
		data <= func_encode_cmd( {5'b0,ca[9:0]}+(63<<3),ba[2:0], 3, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0); // write with nop
		data <= func_encode_cmd( {5'b0,ca[9:0]}+(63<<3),ba[2:0], 3, 1, 0, sel, 1, 1, 1, 0, 0, 0, 1, 0); // write with nop
		@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;

		// nop

py393/test_mcntrl.py

+2 −2

Original line number	Diff line number	Diff line
		@@ -67,6 +67,7 @@ TESTRUN = 0
		PROFILE = 0
		QUIET=1 # more try/excepts
		callableTasks={}

		class CLIError(Exception):
		#Generic exception to raise and log different fatal errors.
		def __init__(self, msg):
		@@ -320,7 +321,6 @@ USAGE
		print("vrlg.VERBOSE__TYPE="+str(vrlg.VERBOSE__TYPE))
		print("vrlg.VERBOSE__RAW="+str(vrlg.VERBOSE__RAW))


		x393mem= x393_mem.X393Mem(verbose,args.simulated) #add dry run parameter
		x393utils= x393_utils.X393Utils(verbose,args.simulated,args.localparams)
		x393tasks= x393_axi_control_status.X393AxiControlStatus(verbose,args.simulated)
		@@ -329,7 +329,7 @@ USAGE
		x393Buffers= x393_mcntrl_buffers.X393McntrlBuffers(verbose,args.simulated)
		x393Tests= x393_mcntrl_tests.X393McntrlTests(verbose,args.simulated)
		x393Eyepatterns= x393_mcntrl_eyepatterns.X393McntrlEyepattern(verbose,args.simulated)
		x393Adjust= x393_mcntrl_adjust.X393McntrlAdjust(verbose,args.simulated)
		x393Adjust= x393_mcntrl_adjust.X393McntrlAdjust(verbose,args.simulated,args.localparams)

		'''
		print ("----------------------")

py393/vrlg.py

+1 −1

Original line number	Diff line number	Diff line
		@@ -99,7 +99,7 @@ def save_default(vname=None):
		<vname> Verilog parameter name string (as listen in 'parameters')
		"""
		global DEFAULTS
		if vname:
		if vname and vname in DEFAULTS:
		DEFAULTS[vname] = globals()[vname]
		else:
		for vname in DEFAULTS:

py393/x393_mcntrl_adjust.py

+15 −10

Original line number	Diff line number	Diff line
		@@ -40,7 +40,8 @@ from x393_pio_sequences import X393PIOSequences
		from x393_mcntrl_timing import X393McntrlTiming
		from x393_mcntrl_buffers import X393McntrlBuffers
		from verilog_utils import split_delay,combine_delay,NUM_FINE_STEPS, convert_w32_to_mem16,convert_mem16_to_w32
		from x393_utils import X393Utils
		#from x393_utils import X393Utils
		import x393_utils

		import get_test_dq_dqs_data # temporary to test processing
		import x393_lma
		@@ -68,7 +69,7 @@ class X393McntrlAdjust(object):
		x393_utils=None
		verbose=1
		adjustment_state={}
		def __init__(self, debug_mode=1,dry_mode=True):
		def __init__(self, debug_mode=1,dry_mode=True, saveFileName=None):
		self.DEBUG_MODE= debug_mode
		self.DRY_MODE= dry_mode
		self.x393_mem= X393Mem(debug_mode,dry_mode)
		@@ -77,7 +78,8 @@ class X393McntrlAdjust(object):
		self.x393_pio_sequences= X393PIOSequences(debug_mode,dry_mode)
		self.x393_mcntrl_timing= X393McntrlTiming(debug_mode,dry_mode)
		self.x393_mcntrl_buffers= X393McntrlBuffers(debug_mode,dry_mode)
		self.x393_utils= X393Utils(debug_mode,dry_mode)
		# print("x393_utils.SAVE_FILE_NAME=",x393_utils.SAVE_FILE_NAME)
		self.x393_utils= x393_utils.X393Utils(debug_mode,dry_mode, saveFileName) # should not overwrite save file path
		# self.__dict__.update(VerilogParameters.__dict__["_VerilogParameters__shared_state"]) # Add verilog parameters to the class namespace
		try:
		self.verbose=vrlg.VERBOSE
		@@ -4367,6 +4369,7 @@ class X393McntrlAdjust(object):

		def set_write_branch(self,
		dqs_pattern=None,
		extraTgl=1, # just in case
		quiet=1):
		"""
		Try write mode branches and find sel (early/late write command), even if it does not match read settings
		@@ -4388,7 +4391,6 @@ class X393McntrlAdjust(object):
		ca=0
		ra=0
		ba=0
		extraTgl=1 # just in case
		wsel=1
		rslt={}

		@@ -4684,7 +4686,7 @@ write_settings= {
		if odd_list:
		rslt[ODD_KEY]=odd_list
		self.adjustment_state['write_variants']=rslt
		if quiet < 3:
		if quiet < 4:
		print ('write_variants=',rslt)
		return rslt

		@@ -4874,7 +4876,7 @@ write_settings= {
		refresh = True,
		forgive_missing = False,
		maxPhaseErrorsPS= None,
		quiet = quiet+1)
		quiet = quiet+0)
		if used_delays is None:
		print ("sorted result=",rslt)
		raise Exception("get_phase_range(): failed to set phase = %d"%(optimal['phase'])) #
		@@ -4889,7 +4891,7 @@ write_settings= {
		filter_dqo = filters[DQO_KEY],
		quiet = quiet+0)
		if quiet < 4:
		print ("Best Range:")
		print ("\nBest Range:",end=" ")
		self.show_all_delays(filter_variants = [(optimal['cmda'],optimal['dqo'],optimal['dqi'])],
		filter_cmda = filters[CMDA_KEY],
		filter_dqsi = filters[DQSI_KEY],
		@@ -4946,8 +4948,9 @@ write_settings= {
		primary_set_in=2,
		primary_set_out=2,
		dqs_pattern=0x55,
		rsel=1, # None (any) or 0/1
		wsel=1, # None (any) or 0/1 # Seems wsel=0 has a better fit - consider changing
		rsel=None, # None (any) or 0/1
		wsel=None, # None (any) or 0/1 # Seems wsel=0 has a better fit - consider changing
		extraTgl=0,
		quiet=3):
		"""
		@param tasks - "*" - load bitfile
		@@ -4959,6 +4962,7 @@ write_settings= {
		@param primary_set_in - which of the primary sets to use when processing DQi/DQSi results (2 - normal, 0 - other DQS phase)
		@param primary_set_out - which of the primary sets to use when processing DQo/DQSo results (2 - normal, 0 - other DQS phase)
		@param dqs_pattern - 0x55/0xaa - DQS output toggle pattern. When it is 0x55 primary_set_out is reversed ?
		@param extraTgl - add extra dqs toggle (2 clock cycles)
		@param quiet reduce output
		"""
		# dqs_pattern=0x55 # 0xaa
		@@ -4985,7 +4989,7 @@ write_settings= {
		wbuf_dly=9 # just a hint, start value can be different
		# primary_set_in=2
		# primary_set_out=2
		write_sel=1 # set DDR3 command in the second cycle of two (0 - during the first omne)
		write_sel=1 # set DDR3 command in the second cycle of two (0 - during the first one)
		safe_phase=0.25 # 0: strictly follow cmda_odelay, >0 -program with this fraction of clk period from the margin
		measure_addr_odelay_dqsi_safe_phase=0.125 # > 0 - allow DQSI with DQI simultaneously deviate +/- this fraction of a period
		commonFine=True, # use same values for fine delay for address/bank lines
		@@ -5137,6 +5141,7 @@ write_settings= {
		'func':self.set_write_branch,
		'comment':'Try write mode branches and find sel (early/late read command) and wbuf delay, if possible.',
		'params':{'dqs_pattern':dqs_pattern,
		'extraTgl':extraTgl,
		'quiet':quiet+1}},
		{'key':'B',
		'func':self.get_phase_range,

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