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Commit 1e313eb7 authored by Andrey Filippov's avatar Andrey Filippov
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co-debugging simulation with hardware tests to make them match

parent ea23bda4
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includes/x393_localparams.vh
View file @ 1e313eb7
......@@ -27,44 +27,9 @@
localparam LD_DLY_CMDA = DLY_LD+'h40; // 0x10c0
localparam LD_DLY_PHASE = DLY_LD+'h60; // 0x10e0
localparam DLY_SET = MCONTR_PHY_0BIT_ADDR + MCONTR_PHY_0BIT_DLY_SET; //0x1020
// different sets of settings for the functional simulation and the actual hardware
`ifdef TARGET_MODE
localparam T_RFC=50; // t_rfc=50 for tCK=2.5ns
localparam T_REFI=48; // t_refi; # 48/97 for normal, 8 - for simulation (7.8us <85C, 3.9us >85C)
`ifdef use200Mhz
// localparam DLY_LANE0_ODELAY= 80'hd8a0d8d4dae0d4dcdbd9; // odelay dqm, odelay dqs, odelay dq[7:0]
// localparam DLY_LANE0_IDELAY= 72'h40989c9aa4949898a4; // idelay dqs, idelay dq[7:0]
// localparam DLY_LANE1_ODELAY= 80'hd8a0dcdcdce0dcf1e0dc; // odelay dqm, odelay dqs, odelay dq[7:0]
// localparam DLY_LANE1_IDELAY= 72'h40aca8aaa8b4acb1ac; // idelay dqs, idelay dq[7:0]
// localparam DLY_CMDA= 256'h8080808080808080808080808080808080808080808080808080808080808080; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
// localparam DLY_PHASE= 8'h4c; // mmcm fine phase shift, 1/4 tCK
`else
// localparam DLY_LANE0_ODELAY= 80'h7474737271706c6b6a69; // odelay dqm, odelay ddqs, odelay dq[7:0]
// localparam DLY_LANE0_IDELAY= 72'hd8737271706c6b6a69; // idelay dqs, idelay dq[7:0
// localparam DLY_LANE1_ODELAY= 80'h7474737271706c6b6a69; // odelay dqm, odelay ddqs, odelay dq[7:0]
// localparam DLY_LANE1_IDELAY= 72'hd8737271706c6b6a69; // idelay dqs, idelay dq[7:0
// localparam DLY_CMDA= 256'h5c5c5c5c5b5a59585454545453525150004c4c4c4b4a49484444444443424140; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
// localparam DLY_PHASE= 8'h4c; // mmcm fine phase shift, 1/4 tCK
`endif
`else
localparam T_RFC=50; // t_rfc=50 for tCK=2.5ns
localparam T_REFI=16; // t_refi; # 48/97 for normal, 8 - for simulation (7.8us <85C, 3.9us >85C)
`ifdef use200Mhz
// localparam DLY_LANE0_ODELAY= 80'h4c784b4a494844434241; // odelay dqm, odelay ddqs, odelay dq[7:0]
// localparam DLY_LANE0_IDELAY= 72'ha0636261605c5b5a59; // idelay dqs, idelay dq[7:0
// localparam DLY_LANE1_ODELAY= 80'h4c784b4a494844434241; // odelay dqm, odelay ddqs, odelay dq[7:0]
// localparam DLY_LANE1_IDELAY= 72'ha0636261605c5b5a59; // idelay dqs, idelay dq[7:0
// localparam DLY_CMDA= 256'h3c3c3c3c3b3a39383434343433323130002c2c2c2b2a29282424242423222120; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
// localparam DLY_PHASE= 8'h1c; // mmcm fine phase shift, 1/4 tCK
`else
// localparam DLY_LANE0_ODELAY= 80'h7474737271706c6b6a69; // odelay dqm, odelay ddqs, odelay dq[7:0]
// localparam DLY_LANE0_IDELAY= 72'hd8737271706c6b6a69; // idelay dqs, idelay dq[7:0
// localparam DLY_LANE1_ODELAY= 80'h7474737271706c6b6a69; // odelay dqm, odelay ddqs, odelay dq[7:0]
// localparam DLY_LANE1_IDELAY= 72'hd8737271706c6b6a69; // idelay dqs, idelay dq[7:0
// localparam DLY_CMDA= 256'h5c5c5c5c5b5a59585454545453525150004c4c4c4b4a49484444444443424140; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
// localparam DLY_PHASE= 8'h1c; // mmcm fine phase shift, 1/4 tCK
`endif
`endif
// different sets of settings for the functional simulation and the actual hardware - should not be needed anymore
localparam T_RFC=50; // t_rfc=50 for tCK=2.5ns
localparam T_REFI=48; // t_refi; # 48/97 for normal, 8 - for simulation (7.8us <85C, 3.9us >85C)
// alternative to set same type delays to the same value
localparam DLY_DQ_IDELAY = ( (DLY_LANE0_IDELAY & 8'hff)+
......@@ -131,14 +96,13 @@
localparam DLY_LANE0_DQS_WLV_IDELAY = DLY_DQS_IDELAY; // b0; // idelay dqs
localparam DLY_LANE1_DQS_WLV_IDELAY = DLY_DQS_IDELAY; // b0; idelay dqs
localparam DQSTRI_FIRST= 4'h3; // DQS tri-state control word, first when enabling output
localparam DQSTRI_FIRST= 4'h1; // 3; // DQS tri-state control word, first when enabling output
localparam DQSTRI_LAST= 4'hc; // DQS tri-state control word, first after disabling output
localparam DQTRI_FIRST= 4'h7; // DQ tri-state control word, first when enabling output
localparam DQTRI_FIRST= 4'h3; // 7; // DQ tri-state control word, first when enabling output
localparam DQTRI_LAST= 4'he; // DQ tri-state control word, first after disabling output
localparam WBUF_DLY_DFLT= DFLT_WBUF_DELAY; // 4'h8; // 4'h6; // extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
localparam WBUF_DLY_WLV= DFLT_WBUF_DELAY; // 4'h7; // write leveling mode: extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
// localparam DLY_PHASE= 8'hdb; // mmcm fine phase shift
localparam INITIALIZE_OFFSET= 'h00; // moemory initialization start address (in words) ..`h0c
localparam REFRESH_OFFSET= 'h10; // refresh start address (in words) ..`h13
localparam WRITELEV_OFFSET= 'h20; // write leveling start address (in words) ..`h2a
......
includes/x393_tasks_pio_sequences.vh
View file @ 1e313eb7
......@@ -31,6 +31,7 @@ task set_read_block;
input [ 2:0] ba;
input [14:0] ra;
input [ 9:0] ca;
input sel;
reg [29:0] cmd_addr;
reg [31:0] data;
integer i;
......@@ -47,11 +48,11 @@ task set_read_block;
// first read
// read
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( {5'b0,ca[9:0]}, ba[2:0], 2, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0);
data <= func_encode_cmd( {5'b0,ca[9:0]}, ba[2:0], 2, 0, 0, sel, 0, 0, 0, 1, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 1, 0, 0);
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, sel, 0, 0, 0, 1, 1, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
//repeat remaining reads
for (i=1;i<64;i=i+1) begin
......@@ -62,15 +63,15 @@ task set_read_block;
end
// nop - all 3 below are the same? - just repeat?
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, sel, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, sel, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, sel, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// tRTP = 4*tCK is already satisfied, no skip here
// precharge, end of a page (B_RST)
......@@ -91,6 +92,7 @@ task set_write_block;
input[2:0]ba;
input[14:0]ra;
input[9:0]ca;
input sel;
reg[29:0] cmd_addr;
reg[31:0] data;
integer i;
......@@ -107,31 +109,32 @@ task set_write_block;
// first write, 3 rd_buf
// write
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( {5'b0,ca[9:0]}, ba[2:0], 3, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0); // B_RD moved 1 cycle earlier
data <= func_encode_cmd( {5'b0,ca[9:0]}, ba[2:0], 3, 1, 0, sel, 0, 0, 0, 0, 0, 1, 0, 0); // B_RD moved 1 cycle earlier
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop 4-th rd_buf
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
// data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 1, 1, 1, 0, 1, 0, 1, 0);
data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 0, 1, 1, 0, 0, 0, 1, 0);
// data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 1, 1, 1, 0, 1, 0, 1, 0);
// data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 0, 1, 1, 0, 0, 0, 1, 0);
data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 0, 0, 0, 0, 0, 0, 1, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
//repeat remaining writes
for (i = 1; i < 62; i = i + 1) begin
// write
// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( {5'b0,ca[9:0]}+(i<<3),ba[2:0],3, 1, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0);
data <= func_encode_cmd( {5'b0,ca[9:0]}+(i<<3),ba[2:0],3, 1, 0, sel, 1, 1, 1, 0, 0, 1, 1, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
end
// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( {5'b0,ca[9:0]}+(62<<3),ba[2:0], 3, 1, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0); // write w/o nop
data <= func_encode_cmd( {5'b0,ca[9:0]}+(62<<3),ba[2:0], 3, 1, 0, sel, 1, 1, 1, 0, 0, 1, 0, 0); // write w/o nop
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 1, 1, 1, 1, 0, 0, 0, 0); // nop with buffer read off
data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, sel, 1, 1, 1, 0, 0, 0, 0); // nop with buffer read off
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// One last write pair w/o buffer
// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( {5'b0,ca[9:0]}+(63<<3),ba[2:0], 3, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0); // write with nop
data <= func_encode_cmd( {5'b0,ca[9:0]}+(63<<3),ba[2:0], 3, 1, 0, sel, 1, 1, 1, 0, 0, 0, 1, 0); // write with nop
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
......
py393/test_mcntrl.py
View file @ 1e313eb7
......@@ -67,6 +67,7 @@ TESTRUN = 0
PROFILE = 0
QUIET=1 # more try/excepts
callableTasks={}
class CLIError(Exception):
#Generic exception to raise and log different fatal errors.
def __init__(self, msg):
......@@ -320,7 +321,6 @@ USAGE
print("vrlg.VERBOSE__TYPE="+str(vrlg.VERBOSE__TYPE))
print("vrlg.VERBOSE__RAW="+str(vrlg.VERBOSE__RAW))
x393mem= x393_mem.X393Mem(verbose,args.simulated) #add dry run parameter
x393utils= x393_utils.X393Utils(verbose,args.simulated,args.localparams)
x393tasks= x393_axi_control_status.X393AxiControlStatus(verbose,args.simulated)
......@@ -329,7 +329,7 @@ USAGE
x393Buffers= x393_mcntrl_buffers.X393McntrlBuffers(verbose,args.simulated)
x393Tests= x393_mcntrl_tests.X393McntrlTests(verbose,args.simulated)
x393Eyepatterns= x393_mcntrl_eyepatterns.X393McntrlEyepattern(verbose,args.simulated)
x393Adjust= x393_mcntrl_adjust.X393McntrlAdjust(verbose,args.simulated)
x393Adjust= x393_mcntrl_adjust.X393McntrlAdjust(verbose,args.simulated,args.localparams)
'''
print ("----------------------")
......
py393/vrlg.py
View file @ 1e313eb7
......@@ -99,7 +99,7 @@ def save_default(vname=None):
<vname> Verilog parameter name string (as listen in 'parameters')
"""
global DEFAULTS
if vname:
if vname and vname in DEFAULTS:
DEFAULTS[vname] = globals()[vname]
else:
for vname in DEFAULTS:
......
py393/x393_mcntrl_adjust.py
View file @ 1e313eb7
......@@ -40,7 +40,8 @@ from x393_pio_sequences import X393PIOSequences
from x393_mcntrl_timing import X393McntrlTiming
from x393_mcntrl_buffers import X393McntrlBuffers
from verilog_utils import split_delay,combine_delay,NUM_FINE_STEPS, convert_w32_to_mem16,convert_mem16_to_w32
from x393_utils import X393Utils
#from x393_utils import X393Utils
import x393_utils
import get_test_dq_dqs_data # temporary to test processing
import x393_lma
......@@ -68,7 +69,7 @@ class X393McntrlAdjust(object):
x393_utils=None
verbose=1
adjustment_state={}
def __init__(self, debug_mode=1,dry_mode=True):
def __init__(self, debug_mode=1,dry_mode=True, saveFileName=None):
self.DEBUG_MODE= debug_mode
self.DRY_MODE= dry_mode
self.x393_mem= X393Mem(debug_mode,dry_mode)
......@@ -77,7 +78,8 @@ class X393McntrlAdjust(object):
self.x393_pio_sequences= X393PIOSequences(debug_mode,dry_mode)
self.x393_mcntrl_timing= X393McntrlTiming(debug_mode,dry_mode)
self.x393_mcntrl_buffers= X393McntrlBuffers(debug_mode,dry_mode)
self.x393_utils= X393Utils(debug_mode,dry_mode)
# print("x393_utils.SAVE_FILE_NAME=",x393_utils.SAVE_FILE_NAME)
self.x393_utils= x393_utils.X393Utils(debug_mode,dry_mode, saveFileName) # should not overwrite save file path
# self.__dict__.update(VerilogParameters.__dict__["_VerilogParameters__shared_state"]) # Add verilog parameters to the class namespace
try:
self.verbose=vrlg.VERBOSE
......@@ -4367,6 +4369,7 @@ class X393McntrlAdjust(object):
def set_write_branch(self,
dqs_pattern=None,
extraTgl=1, # just in case
quiet=1):
"""
Try write mode branches and find sel (early/late write command), even if it does not match read settings
......@@ -4388,7 +4391,6 @@ class X393McntrlAdjust(object):
ca=0
ra=0
ba=0
extraTgl=1 # just in case
wsel=1
rslt={}
......@@ -4684,7 +4686,7 @@ write_settings= {
if odd_list:
rslt[ODD_KEY]=odd_list
self.adjustment_state['write_variants']=rslt
if quiet < 3:
if quiet < 4:
print ('write_variants=',rslt)
return rslt
......@@ -4874,7 +4876,7 @@ write_settings= {
refresh = True,
forgive_missing = False,
maxPhaseErrorsPS= None,
quiet = quiet+1)
quiet = quiet+0)
if used_delays is None:
print ("sorted result=",rslt)
raise Exception("get_phase_range(): failed to set phase = %d"%(optimal['phase'])) #
......@@ -4889,7 +4891,7 @@ write_settings= {
filter_dqo = filters[DQO_KEY],
quiet = quiet+0)
if quiet < 4:
print ("Best Range:")
print ("\nBest Range:",end=" ")
self.show_all_delays(filter_variants = [(optimal['cmda'],optimal['dqo'],optimal['dqi'])],
filter_cmda = filters[CMDA_KEY],
filter_dqsi = filters[DQSI_KEY],
......@@ -4946,8 +4948,9 @@ write_settings= {
primary_set_in=2,
primary_set_out=2,
dqs_pattern=0x55,
rsel=1, # None (any) or 0/1
wsel=1, # None (any) or 0/1 # Seems wsel=0 has a better fit - consider changing
rsel=None, # None (any) or 0/1
wsel=None, # None (any) or 0/1 # Seems wsel=0 has a better fit - consider changing
extraTgl=0,
quiet=3):
"""
@param tasks - "*" - load bitfile
......@@ -4959,6 +4962,7 @@ write_settings= {
@param primary_set_in - which of the primary sets to use when processing DQi/DQSi results (2 - normal, 0 - other DQS phase)
@param primary_set_out - which of the primary sets to use when processing DQo/DQSo results (2 - normal, 0 - other DQS phase)
@param dqs_pattern - 0x55/0xaa - DQS output toggle pattern. When it is 0x55 primary_set_out is reversed ?
@param extraTgl - add extra dqs toggle (2 clock cycles)
@param quiet reduce output
"""
# dqs_pattern=0x55 # 0xaa
......@@ -4985,7 +4989,7 @@ write_settings= {
wbuf_dly=9 # just a hint, start value can be different
# primary_set_in=2
# primary_set_out=2
write_sel=1 # set DDR3 command in the second cycle of two (0 - during the first omne)
write_sel=1 # set DDR3 command in the second cycle of two (0 - during the first one)
safe_phase=0.25 # 0: strictly follow cmda_odelay, >0 -program with this fraction of clk period from the margin
measure_addr_odelay_dqsi_safe_phase=0.125 # > 0 - allow DQSI with DQI simultaneously deviate +/- this fraction of a period
commonFine=True, # use same values for fine delay for address/bank lines
......@@ -5137,6 +5141,7 @@ write_settings= {
'func':self.set_write_branch,
'comment':'Try write mode branches and find sel (early/late read command) and wbuf delay, if possible.',
'params':{'dqs_pattern':dqs_pattern,
'extraTgl':extraTgl,
'quiet':quiet+1}},
{'key':'B',
'func':self.get_phase_range,
......
py393/x393_utils.py
View file @ 1e313eb7
......@@ -44,7 +44,9 @@ FPGA_RST_CTRL= 0xf8000240
FPGA0_THR_CTRL=0xf8000178
FPGA_LOAD_BITSTREAM="/dev/xdevcfg"
INT_STS= 0xf800700c
#SAVE_FILE_NAME="Some_name"# None
class X393Utils(object):
# global SAVE_FILE_NAME
DRY_MODE= True # True
DEBUG_MODE=1
# vpars=None
......@@ -53,7 +55,7 @@ class X393Utils(object):
saveFileName=None
x393_axi_tasks=None
# verbose=1
def __init__(self, debug_mode=1,dry_mode=True,saveFileName=None):
def __init__(self, debug_mode=1,dry_mode=True ,saveFileName=None):
self.DEBUG_MODE=debug_mode
self.DRY_MODE=dry_mode
if saveFileName:
......@@ -193,15 +195,15 @@ class X393Utils(object):
return d
def getParTmpl(self):
return ({"name":"DLY_LANE0_ODELAY", "width": 80, "decl_width":""}, # decl_width can be "[7:0]", "integer", etc
{"name":"DLY_LANE0_IDELAY", "width": 72, "decl_width":""},
{"name":"DLY_LANE1_ODELAY", "width": 80, "decl_width":""},
{"name":"DLY_LANE1_IDELAY", "width": 72, "decl_width":""},
{"name":"DLY_CMDA", "width":256, "decl_width":""},
{"name":"DLY_PHASE", "width": 8, "decl_width":""},
{"name":"DFLT_WBUF_DELAY", "width": 4, "decl_width":""},
{"name":"DFLT_WSEL", "width": 1, "decl_width":""},
{"name":"DFLT_RSEL", "width": 1, "decl_width":""},
return ({"name":"DLY_LANE0_ODELAY", "width": 80, "decl_width":"","disable":False}, # decl_width can be "[7:0]", "integer", etc
{"name":"DLY_LANE0_IDELAY", "width": 72, "decl_width":"","disable":False},
{"name":"DLY_LANE1_ODELAY", "width": 80, "decl_width":"","disable":False},
{"name":"DLY_LANE1_IDELAY", "width": 72, "decl_width":"","disable":False},
{"name":"DLY_CMDA", "width":256, "decl_width":"","disable":False},
{"name":"DLY_PHASE", "width": 8, "decl_width":"","disable":False},
{"name":"DFLT_WBUF_DELAY", "width": 4, "decl_width":"","disable":True},
{"name":"DFLT_WSEL", "width": 1, "decl_width":"","disable":True},
{"name":"DFLT_RSEL", "width": 1, "decl_width":"","disable":True},
)
def localparams(self,
......@@ -219,7 +221,13 @@ class X393Utils(object):
for p in self.getParTmpl(): # parTmpl:
numDigits = (p["width"]+3)/4
frmt="localparam %%%ds %%%ds %3d'h%%0%dx;\n"%(declWidth,nameLen+2,p["width"],numDigits)
txt+=frmt%(p['decl_width'],p['name']+" =",vrlg.__dict__[p['name']])
try:
pv=vrlg.__dict__[p['name']]
if p['disable']:
txt += '// '
txt+=frmt%(p['decl_width'],p['name']+" =",pv)
except: # parameter does not exist
pass
if not quiet:
print (txt)
return txt
......
x393_testbench01.sav
View file @ 1e313eb7
[*]
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
[*] Tue Mar 17 07:18:15 2015
[*] Tue Apr 21 01:47:19 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150316202414190.lxt"
[dumpfile_mtime] "Tue Mar 17 02:39:38 2015"
[dumpfile_size] 982556355
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150420193910060.lxt"
[dumpfile_mtime] "Tue Apr 21 01:44:01 2015"
[dumpfile_size] 252436540
[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
[timestart] 47475610
[size] 1823 1180
[pos] 2062 0
*-11.698502 47485628 157271875 157546875 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 41564660
[size] 1823 1173
[pos] 2065 0
*-12.595797 41576250 157271875 157546875 43667500 43655000 44285000 44297500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01.
[treeopen] x393_testbench01.ddr3_i.
[treeopen] x393_testbench01.x393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.
......@@ -38,17 +39,19 @@
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.
[sst_width] 264
[signals_width] 310
[sst_width] 347
[signals_width] 369
[sst_expanded] 1
[sst_vpaned_height] 631
@800200
[sst_vpaned_height] 635
@c00200
-top_simulation
@28
x393_testbench01.RST[0]
......@@ -245,9 +248,8 @@ x393_testbench01.wait_status_condition.status_control_address[29:0]
x393_testbench01.wait_status_condition.status_mode[1:0]
@1401200
-WAIT_STATUS_CONDITION
@1000200
-top_simulation
@800200
@c00200
-mem_clocks
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk_in[0]
......@@ -258,9 +260,9 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.iclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.iclk[0]
@1000200
@1401200
-mem_clocks
@800200
@c00200
-write_delays
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din[31:0]
......@@ -278,14 +280,14 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dq_data_dly[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.d_ser[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs_data_dly[0]
@1000200
@1401200
-write_delays
@800200
@c00200
-read_delays
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs_di[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs_received_dly[0]
@201
@200
-
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.iclk[0]
......@@ -296,7 +298,7 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dout[3:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dout[3:0]
@1000200
@1401200
-read_delays
@c00200
-axi
......@@ -1002,6 +1004,53 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.want[0]
@1401200
-refresh
@800200
-DDR3_wrap
@28
x393_testbench01.x393_i.mclk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_tri[7:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_tri[7:0]
@28
x393_testbench01.ddr3_i.en_dq[1:0]
x393_testbench01.ddr3_i.en_dqs[1:0]
x393_testbench01.ddr3_i.SDCLK_D[0]
@22
x393_testbench01.ddr3_i.SDA_D[14:0]
@28
x393_testbench01.ddr3_i.SDBA_D[2:0]
x393_testbench01.ddr3_i.SDRAS_D[0]
x393_testbench01.ddr3_i.SDCAS_D[0]
x393_testbench01.ddr3_i.SDWE_D[0]
x393_testbench01.ddr3_i.DQSL_D[0]
x393_testbench01.ddr3_i.DQSU_D[0]
@22
x393_testbench01.ddr3_i.SDD_D[15:0]
@29
x393_testbench01.ddr3_i.SDODT_D[0]
@1000200
-DDR3_wrap
@200
-
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.din_dqs[7:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.din[63:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.tin_dqs[7:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.tin_dq[7:0]
@200
-
@800200
-dqs0_dq0_out
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs_out_dly_i.data_in[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs_out_dly_i.data_out[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.d_ser[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dq_data_dly[0]
@1000200
-dqs0_dq0_out
@200
-
-
@800200
-DDR3
@28
x393_testbench01.x393_i.SDRST[0]
......
x393_testbench01.tf
View file @ 1e313eb7
......@@ -27,23 +27,20 @@
`define SET_PER_PIN_DELAYS 1 // set individual (including per-DQ pin delays)
`define PS_PIO_WAIT_COMPLETE 0 // wait until PS PIO module finished transaction before starting a new one
// Disabled already passed test to speedup simulation
`define TEST_WRITE_LEVELLING 1
`define TEST_READ_PATTERN 1
//`define TEST_WRITE_LEVELLING 1
//`define TEST_READ_PATTERN 1
`define TEST_WRITE_BLOCK 1
`define TEST_READ_BLOCK 1
//`define TESTL_SHORT_SCANLINE 1
//`define TEST_SCANLINE_WRITE 1
//`define TEST_SCANLINE_WRITE
`define TEST_SCANLINE_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
//`define TEST_SCANLINE_READ 1
`define TEST_READ_SHOW 1
`define TEST_TILED_WRITE 1
//`define TEST_TILED_WRITE 0
`define TEST_TILED_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
`define TEST_TILED_READ 1
//`define TEST_TILED_READ 0
`define TEST_TILED_WRITE32 1
`define TEST_TILED_READ32 1
//`define TEST_TILED_WRITE32 0
//`define TEST_TILED_READ32 0
module x393_testbench01 #(
`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - not used
......@@ -59,7 +56,8 @@ module x393_testbench01 #(
`endif
`define DEBUG_WR_SINGLE 1
`define DEBUG_RD_DATA 1
`include "includes/x393_cur_params_sim.vh" // parameters that may need adjustment, should be before x393_localparams.vh
//`include "includes/x393_cur_params_sim.vh" // parameters that may need adjustment, should be before x393_localparams.vh
`include "includes/x393_cur_params_target.vh" // SuppressThisWarning VEditor - not used parameters that may need adjustment, should be before x393_localparams.vh
`include "includes/x393_localparams.vh" // SuppressThisWarning VEditor - not used
// DDR3 signals
wire SDRST;
......@@ -298,18 +296,23 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
axi_set_dqs_odelay_nominal;
`ifdef TEST_WRITE_LEVELLING
$display("===================== TEST_WRITE_LEVELLING =========================");
test_write_levelling;
`endif
`ifdef TEST_READ_PATTERN
$display("===================== TEST_READ_PATTERN =========================");
test_read_pattern;
`endif
`ifdef TEST_WRITE_BLOCK
$display("===================== TEST_WRITE_BLOCK =========================");
test_write_block;
`endif
`ifdef TEST_READ_BLOCK
$display("===================== TEST_READ_BLOCK =========================");
test_read_block;
`endif
`ifdef TESTL_SHORT_SCANLINE
$display("===================== TESTL_SHORT_SCANLINE =========================");
test_scanline_write(
1, // valid: 1 or 3 input [3:0] channel;
SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages;
......@@ -366,6 +369,7 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
`endif
`ifdef TEST_SCANLINE_WRITE
$display("===================== TEST_SCANLINE_WRITE =========================");
test_scanline_write(
1, // valid: 1 or 3 input [3:0] channel;
SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages;
......@@ -377,6 +381,7 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
`endif
`ifdef TEST_SCANLINE_READ
$display("===================== TEST_SCANLINE_READ =========================");
test_scanline_read (
1, // valid: 1 or 3 input [3:0] channel;
SCANLINE_EXTRA_PAGES, // input [1:0] extra_pages;
......@@ -389,6 +394,7 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
`endif
`ifdef TEST_TILED_WRITE
$display("===================== TEST_TILED_WRITE =========================");
test_tiled_write (
2, // [3:0] channel;
0, // byte32;
......@@ -405,6 +411,7 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
`endif
`ifdef TEST_TILED_READ
$display("===================== TEST_TILED_READ =========================");
test_tiled_read (
2, // [3:0] channel;
0, // byte32;
......@@ -422,6 +429,7 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
`endif
`ifdef TEST_TILED_WRITE32
$display("===================== TEST_TILED_WRITE32 =========================");
test_tiled_write (
4, // 2, // [3:0] channel;
1, // byte32;
......@@ -438,6 +446,7 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
`endif
`ifdef TEST_TILED_READ32
$display("===================== TEST_TILED_READ32 =========================");
test_tiled_read (
4, //2, // [3:0] channel;
1, // byte32;
......@@ -702,8 +711,47 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.DUMMY_TO_KEEP(DUMMY_TO_KEEP) // to keep PS7 signals from "optimization"
// ,.MEMCLK (MEMCLK)
);
// Micron DDR3 memory model
/* Instance of Micron DDR3 memory model */
// just to simplify extra delays in tri-state memory bus - provide output enable
wire WRAP_MCLK=x393_i.mclk;
wire [7:0] WRAP_PHY_DQ_TRI=x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_tri[7:0] ;
wire [7:0] WRAP_PHY_DQS_TRI=x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_tri[7:0] ;
//x393_i.mcntrl393_i.mcntrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_tri
//x393_i.mcntrl393_i.mcntrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_tri
`define USE_DDR3_WRAP 1
`ifdef USE_DDR3_WRAP
ddr3_wrap #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.TRISTATE_DELAY_CLK (1), // total 2
.TRISTATE_DELAY (0),
.CLK_DELAY (0),
.CMDA_DELAY (0),
.DQS_IN_DELAY (0),
.DQ_IN_DELAY (0),
.DQS_OUT_DELAY (0),
.DQ_OUT_DELAY (0)
) ddr3_i (
.mclk (WRAP_MCLK), // input
.dq_tri ({WRAP_PHY_DQ_TRI[4],WRAP_PHY_DQ_TRI[0]}), // input[1:0]
.dqs_tri ({WRAP_PHY_DQS_TRI[4],WRAP_PHY_DQS_TRI[0]}), // input[1:0]
.SDRST (SDRST),
.SDCLK (SDCLK),
.SDNCLK (SDNCLK),
.SDCKE (SDCKE),
.SDRAS (SDRAS),
.SDCAS (SDCAS),
.SDWE (SDWE),
.SDDMU (SDDMU),
.SDDML (SDDML),
.SDBA (SDBA[2:0]),
.SDA (SDA[ADDRESS_NUMBER-1:0]),
.SDD (SDD[15:0]),
.DQSU (DQSU),
.NDQSU (NDQSU),
.DQSL (DQSL),
.NDQSL (NDQSL),
.SDODT (SDODT) // input
);
`else
ddr3 #(
.TCK_MIN (2500),
.TJIT_PER (100),
......@@ -890,7 +938,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.tdqs_n (), // output[1:0]
.odt (SDODT) // input
);
`endif
// Simulation modules
simul_axi_master_rdaddr
......@@ -1046,7 +1094,7 @@ simul_axi_read #(
// set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)
axi_set_dqs_dqm_patterns;
// prepare all sequences
set_all_sequences;
set_all_sequences (1,0); // rsel = 1, wsel=0
// prepare write buffer
write_block_buf_chn(0,0,256); // fill block memory (channel, page, number)
// set all delays
......@@ -1598,6 +1646,8 @@ endtask
task set_all_sequences;
input rsel;
input wsel;
begin
$display("SET MRS @ %t",$time);
set_mrs(1);
......@@ -1613,14 +1663,16 @@ task set_all_sequences;
set_write_block(
3'h5, // bank
15'h1234, // row address
10'h100 // column address
10'h100, // column address
wsel
);
$display("SET READ BLOCK @ %t",$time);
set_read_block(
3'h5, // bank
15'h1234, // row address
10'h100 // column address
10'h100, // column address
rsel // sel
);
end
endtask
......
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