Working on HiSPi decoder (1b4f3f2c) · Commits · Elphel / x393

includes/x393_parameters.vh

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	@@ -760,12 +760,19 @@
	parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE		parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
	parameter CLKOUT_DIV_AXIHP = 6, // To get 150MHz for the reference clock		parameter CLKOUT_DIV_AXIHP = 6, // To get 150MHz for the reference clock
	parameter BUF_CLK1X_AXIHP = "BUFG", // "BUFG", "BUFH", "BUFR", "NONE"		parameter BUF_CLK1X_AXIHP = "BUFG", // "BUFG", "BUFH", "BUFR", "NONE"
			`ifdef HISPI
			parameter CLKIN_PERIOD_PCLK = 42, // 24MHz (actually needed is 24.4444
			parameter DIVCLK_DIVIDE_PCLK = 1,
			parameter CLKFBOUT_MULT_PCLK = 36, // 880 MHz
			parameter CLKOUT_DIV_PCLK = 4, // 220 MHz
			parameter CLKOUT_DIV_PCLK2X = 2, // 440 MHz
			`else
	parameter CLKIN_PERIOD_PCLK = 42, // 24MHz		parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
	parameter DIVCLK_DIVIDE_PCLK = 1,		parameter DIVCLK_DIVIDE_PCLK = 1,
	parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz		parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
	parameter CLKOUT_DIV_PCLK = 10, // 96MHz		parameter CLKOUT_DIV_PCLK = 10, // 96MHz
	parameter CLKOUT_DIV_PCLK2X = 5, // 192 MHz		parameter CLKOUT_DIV_PCLK2X = 5, // 192 MHz
			`endif
	parameter PHASE_CLK2X_PCLK = 0.000,		parameter PHASE_CLK2X_PCLK = 0.000,
	parameter BUF_CLK1X_PCLK = "BUFG",		parameter BUF_CLK1X_PCLK = "BUFG",
	parameter BUF_CLK1X_PCLK2X = "BUFG",		parameter BUF_CLK1X_PCLK2X = "BUFG",

sensor/pxd_single.v

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	@@ -38,8 +38,8 @@ module pxd_single#(
	output pxd_in, // data output (@posedge ipclk?)		output pxd_in, // data output (@posedge ipclk?)
	input ipclk, // restored clock from the sensor, phase-shifted		input ipclk, // restored clock from the sensor, phase-shifted
	input ipclk2x, // restored clock from the sensor, phase-shifted, twice frequency		input ipclk2x, // restored clock from the sensor, phase-shifted, twice frequency
	input mrst, // reset @ posxedge mclk		input mrst, // reset @ posedge mclk
	input irst, // reset @ posxedge iclk		input irst, // reset @ posedge iclk
	input mclk, // clock for setting delay values		input mclk, // clock for setting delay values
	input [7:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk		input [7:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
	input set_idelay, // mclk synchronous load idelay value		input set_idelay, // mclk synchronous load idelay value

sensor/sens_hispi12l4.v

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			/*******************************************************************************
			* Module: sens_hispi12l4
			* Date:2015-10-13
			* Author: andrey
			* Description: Decode HiSPi 4-lane, 12 bits Packetized-SP data from the sensor
			*
			* Copyright (c) 2015 Elphel, Inc .
			* sens_hispi12l4.v is free software; you can redistribute it and/or modify
			* it under the terms of the GNU General Public License as published by
			* the Free Software Foundation, either version 3 of the License, or
			* (at your option) any later version.
			*
			* sens_hispi12l4.v is distributed in the hope that it will be useful,
			* but WITHOUT ANY WARRANTY; without even the implied warranty of
			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
			* GNU General Public License for more details.
			*
			* You should have received a copy of the GNU General Public License
			* along with this program. If not, see <http://www.gnu.org/licenses/> .
			*******************************************************************************/
			`timescale 1ns/1ps

			module sens_hispi12l4#(
			parameter IODELAY_GRP = "IODELAY_SENSOR",
			parameter integer IDELAY_VALUE = 0,
			parameter real REFCLK_FREQUENCY = 200.0,
			parameter HIGH_PERFORMANCE_MODE = "FALSE",
			parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
			parameter SENS_PCLK_PERIOD = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
			parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"

			parameter CLKFBOUT_MULT_SENSOR = 4, // 220 MHz --> 880 MHz
			parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
			parameter IPCLK_PHASE = 0.000,
			parameter IPCLK2X_PHASE = 0.000,
			parameter BUF_IPCLK = "BUFR",
			parameter BUF_IPCLK2X = "BUFR",

			parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
			parameter SENS_REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
			parameter SENS_REF_JITTER2 = 0.010,
			parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
			parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
			parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns

			parameter HISPI_NUMLANES = 4,
			parameter HISPI_CAPACITANCE = "DONT_CARE",
			parameter HISPI_DIFF_TERM = "TRUE",
			parameter HISPI_DQS_BIAS = "TRUE",
			parameter HISPI_IBUF_DELAY_VALUE = "0",
			parameter HISPI_IBUF_LOW_PWR = "TRUE",
			parameter HISPI_IFD_DELAY_VALUE = "AUTO",
			parameter HISPI_IOSTANDARD = "DEFAULT"
			)(
			input pclk, // global clock input, pixel rate (220MHz for MT9F002)
			input prst,
			output irst,

			input trigger_mode, // running in triggered mode (0 - free running mode)
			input trig, // per-sensor trigger input
			// I/O pads
			input [HISPI_NUMLANES-1:0] sns_dp,
			input [HISPI_NUMLANES-1:0] sns_dn,
			input sns_clkp,
			input sns_clkn,
			// output
			output reg [11:0] pxd_out,
			output reg vact_out,
			output hact_out,

			// delay control inputs
			input mclk,
			input mrst,
			input [HISPI_NUMLANES * 8-1:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
			input [HISPI_NUMLANES-1:0] set_idelay, // mclk synchronous load idelay value
			input ld_idelay, // mclk synchronous set idealy value
			input set_clk_phase, // mclk synchronous set idealy value
			input rst_mmcm,
			// MMCP output status
			output ps_rdy, // output
			output [7:0] ps_out, // output[7:0] reg
			output locked_pxd_mmcm,
			output clkin_pxd_stopped_mmcm, // output
			output clkfb_pxd_stopped_mmcm // output

			);
			wire ipclk; // re-generated half HiSPi clock (165 MHz)
			wire ipclk2x;// re-generated HiSPi clock (330 MHz)
			wire [HISPI_NUMLANES * 4-1:0] sns_d;
			sens_hispi_clock #(
			.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
			.SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
			.SENS_BANDWIDTH (SENS_BANDWIDTH),
			.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
			.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
			.IPCLK_PHASE (IPCLK_PHASE),
			.IPCLK2X_PHASE (IPCLK2X_PHASE),
			.BUF_IPCLK (BUF_IPCLK),
			.BUF_IPCLK2X (BUF_IPCLK2X),
			.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
			.SENS_REF_JITTER1 (SENS_REF_JITTER1),
			.SENS_REF_JITTER2 (SENS_REF_JITTER2),
			.SENS_SS_EN (SENS_SS_EN),
			.SENS_SS_MODE (SENS_SS_MODE),
			.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
			.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
			.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
			.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
			.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
			.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
			.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
			.HISPI_IOSTANDARD (HISPI_IOSTANDARD)
			) sens_hispi_clock_i (
			.mclk (mclk), // input
			.mrst (mrst), // input
			.phase (dly_data[7:0]), // input[7:0]
			.set_phase (set_clk_phase), // input
			.rst_mmcm (rst_mmcm), // input
			.clp_p (sns_clkp), // input
			.clk_n (sns_clkn), // input
			.ipclk (ipclk), // output
			.ipclk2x (ipclk2x), // output
			.ps_rdy (ps_rdy), // output
			.ps_out (ps_out), // output[7:0]
			.locked_pxd_mmcm (locked_pxd_mmcm), // output
			.clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output
			.clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm) // output
			);

			sens_hispi_din #(
			.IODELAY_GRP (IODELAY_GRP),
			.IDELAY_VALUE (IDELAY_VALUE),
			.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
			.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
			.HISPI_NUMLANES (HISPI_NUMLANES),
			.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
			.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
			.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
			.HISPI_IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
			.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
			.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
			.HISPI_IOSTANDARD (HISPI_IOSTANDARD)
			) sens_hispi_din_i (
			.mclk (mclk), // input
			.mrst (mrst), // input
			.dly_data (dly_data), // input[31:0]
			.set_idelay (set_idelay), // input[3:0]
			.ld_idelay (ld_idelay), // input
			.ipclk (ipclk), // input
			.ipclk2x (ipclk2x), // input
			.irst (irst), // input
			.din_p (sns_dp), // input[3:0]
			.din_n (sns_dn), // input[3:0]
			.dout (sns_d) // output[15:0]
			);



			endmodule

sensor/sens_hispi_clock.v

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			/*******************************************************************************
			* Module: sens_hispi_clock
			* Date:2015-10-13
			* Author: andrey
			* Description: Recover iclk/iclk2x from the HiSPi differntial clock
			*
			* Copyright (c) 2015 Elphel, Inc .
			* sens_hispi_clock.v is free software; you can redistribute it and/or modify
			* it under the terms of the GNU General Public License as published by
			* the Free Software Foundation, either version 3 of the License, or
			* (at your option) any later version.
			*
			* sens_hispi_clock.v is distributed in the hope that it will be useful,
			* but WITHOUT ANY WARRANTY; without even the implied warranty of
			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
			* GNU General Public License for more details.
			*
			* You should have received a copy of the GNU General Public License
			* along with this program. If not, see <http://www.gnu.org/licenses/> .
			*******************************************************************************/
			`timescale 1ns/1ps

			module sens_hispi_clock#(

			parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
			parameter SENS_PCLK_PERIOD = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
			parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"

			parameter CLKFBOUT_MULT_SENSOR = 4, // 220 MHz --> 880 MHz
			parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
			parameter IPCLK_PHASE = 0.000,
			parameter IPCLK2X_PHASE = 0.000,
			parameter BUF_IPCLK = "BUFR",
			parameter BUF_IPCLK2X = "BUFR",

			parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
			parameter SENS_REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
			parameter SENS_REF_JITTER2 = 0.010,
			parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
			parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
			parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns

			parameter HISPI_CAPACITANCE = "DONT_CARE",
			parameter HISPI_DIFF_TERM = "TRUE",
			parameter HISPI_DQS_BIAS = "TRUE",
			parameter HISPI_IBUF_DELAY_VALUE = "0",
			parameter HISPI_IBUF_LOW_PWR = "TRUE",
			parameter HISPI_IFD_DELAY_VALUE = "AUTO",
			parameter HISPI_IOSTANDARD = "DEFAULT"



			)(
			input mclk,
			input mrst,
			input [7:0] phase,
			input set_phase,
			input rst_mmcm,
			input clp_p,
			input clk_n,
			output ipclk, // 165 MHz
			output ipclk2x, // 330 MHz
			output ps_rdy, // output
			output [7:0] ps_out, // output[7:0] reg
			output locked_pxd_mmcm,
			output clkin_pxd_stopped_mmcm, // output
			output clkfb_pxd_stopped_mmcm // output
			);
			wire ipclk_pre;
			wire ipclk2x_pre; // output
			wire clk_fb;
			wire prst = mrst;
			wire clk_in;
			ibufds_ibufgds #(
			.CAPACITANCE (HISPI_CAPACITANCE),
			.DIFF_TERM (HISPI_DIFF_TERM),
			.DQS_BIAS (HISPI_DQS_BIAS),
			.IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
			.IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
			.IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
			.IOSTANDARD (HISPI_IOSTANDARD)
			) ibufds_ibufgds0_i (
			.O (clk_in), // output
			.I (clp_p), // input
			.IB (clk_n) // input
			);



			// generate phase-shifterd pixel clock (and 2x version) from either the internal clock (that is output to the sensor) or from the clock
			// received from the sensor (may need to reset MMCM after resetting sensor)
			mmcm_phase_cntr #(
			.PHASE_WIDTH (SENS_PHASE_WIDTH),
			.CLKIN_PERIOD (SENS_PCLK_PERIOD),
			.BANDWIDTH (SENS_BANDWIDTH),
			.CLKFBOUT_MULT_F (CLKFBOUT_MULT_SENSOR), // 4
			.DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
			.CLKFBOUT_PHASE (CLKFBOUT_PHASE_SENSOR),
			.CLKOUT0_PHASE (IPCLK_PHASE),
			.CLKOUT1_PHASE (IPCLK2X_PHASE),
			.CLKFBOUT_USE_FINE_PS("FALSE"),
			.CLKOUT0_USE_FINE_PS ("TRUE"),
			.CLKOUT1_USE_FINE_PS ("TRUE"),
			.CLKOUT0_DIVIDE_F (CLKFBOUT_MULT_SENSOR), // 4 // 8.000),
			.CLKOUT1_DIVIDE (CLKFBOUT_MULT_SENSOR / 2), //2 // 4),
			.COMPENSATION ("ZHOLD"),
			.REF_JITTER1 (SENS_REF_JITTER1),
			.REF_JITTER2 (SENS_REF_JITTER2),
			.SS_EN (SENS_SS_EN),
			.SS_MODE (SENS_SS_MODE),
			.SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
			.STARTUP_WAIT ("FALSE")

			) mmcm_phase_cntr_i (
			.clkin1 (clk_in), // input
			.clkin2 (1'b0), // input
			.sel_clk2 (1'b0), // input
			.clkfbin (clk_fb), // input
			.rst (rst_mmcm), // input
			.pwrdwn (1'b0), // input
			.psclk (mclk), // input
			.ps_we (set_phase), // input
			.ps_din (phase), // input[7:0]
			.ps_ready (ps_rdy), // output
			.ps_dout (ps_out), // output[7:0] reg
			.clkout0 (ipclk_pre), // output
			.clkout1 (ipclk2x_pre), // output
			.clkout2(), // output
			.clkout3(), // output
			.clkout4(), // output
			.clkout5(), // output
			.clkout6(), // output
			.clkout0b(), // output
			.clkout1b(), // output
			.clkout2b(), // output
			.clkout3b(), // output
			.clkfbout (clk_fb), // output
			.clkfboutb(), // output
			.locked (locked_pxd_mmcm),
			.clkin_stopped (clkin_pxd_stopped_mmcm), // output
			.clkfb_stopped (clkfb_pxd_stopped_mmcm) // output
			// output
			);
			generate
			if (BUF_IPCLK == "BUFG") BUFG clk1x_i (.O(ipclk), .I(ipclk_pre));
			else if (BUF_IPCLK == "BUFH") BUFH clk1x_i (.O(ipclk), .I(ipclk_pre));
			else if (BUF_IPCLK == "BUFR") BUFR clk1x_i (.O(ipclk), .I(ipclk_pre), .CE(1'b1), .CLR(prst));
			else if (BUF_IPCLK == "BUFMR") BUFMR clk1x_i (.O(ipclk), .I(ipclk_pre));
			else if (BUF_IPCLK == "BUFIO") BUFIO clk1x_i (.O(ipclk), .I(ipclk_pre));
			else assign ipclk = ipclk_pre;
			endgenerate

			generate
			if (BUF_IPCLK2X == "BUFG") BUFG clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
			else if (BUF_IPCLK2X == "BUFH") BUFH clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
			else if (BUF_IPCLK2X == "BUFR") BUFR clk2x_i (.O(ipclk2x), .I(ipclk2x_pre), .CE(1'b1), .CLR(prst));
			else if (BUF_IPCLK2X == "BUFMR") BUFMR clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
			else if (BUF_IPCLK2X == "BUFIO") BUFIO clk2x_i (.O(ipclk2x), .I(ipclk2x_pre));
			else assign ipclk2x = ipclk2x_pre;
			endgenerate





			endmodule

sensor/sens_hispi_din.v

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			/*******************************************************************************
			* Module: sens_hispi_din
			* Date:2015-10-13
			* Author: andrey
			* Description: Input differential receivers for HiSPi lanes
			*
			* Copyright (c) 2015 Elphel, Inc .
			* sens_hispi_din.v is free software; you can redistribute it and/or modify
			* it under the terms of the GNU General Public License as published by
			* the Free Software Foundation, either version 3 of the License, or
			* (at your option) any later version.
			*
			* sens_hispi_din.v is distributed in the hope that it will be useful,
			* but WITHOUT ANY WARRANTY; without even the implied warranty of
			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
			* GNU General Public License for more details.
			*
			* You should have received a copy of the GNU General Public License
			* along with this program. If not, see <http://www.gnu.org/licenses/> .
			*******************************************************************************/
			`timescale 1ns/1ps

			module sens_hispi_din #(
			parameter IODELAY_GRP = "IODELAY_SENSOR", // may need different for different channels?
			parameter integer IDELAY_VALUE = 0,
			parameter real REFCLK_FREQUENCY = 200.0,
			parameter HIGH_PERFORMANCE_MODE = "FALSE",

			parameter HISPI_NUMLANES = 4,
			parameter HISPI_CAPACITANCE = "DONT_CARE",
			parameter HISPI_DIFF_TERM = "TRUE",
			parameter HISPI_DQS_BIAS = "TRUE",
			parameter HISPI_IBUF_DELAY_VALUE = "0",
			parameter HISPI_IBUF_LOW_PWR = "TRUE",
			parameter HISPI_IFD_DELAY_VALUE = "AUTO",
			parameter HISPI_IOSTANDARD = "DEFAULT"
			)(
			input mclk,
			input mrst,
			input [HISPI_NUMLANES * 8-1:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
			input [HISPI_NUMLANES-1:0] set_idelay, // mclk synchronous load idelay value
			input ld_idelay, // mclk synchronous set idealy value
			input ipclk, // 165 MHz
			input ipclk2x, // 330 MHz
			input irst, // reset @posedge iclk
			input [HISPI_NUMLANES-1:0] din_p,
			input [HISPI_NUMLANES-1:0] din_n,
			output [HISPI_NUMLANES * 4-1:0] dout

			);
			wire [HISPI_NUMLANES-1:0] din;
			wire [HISPI_NUMLANES-1:0] din_dly;

			generate
			genvar i;
			for (i=1; i < HISPI_NUMLANES; i=i+1) begin: din_block
			ibufds_ibufgds #(
			.CAPACITANCE (HISPI_CAPACITANCE),
			.DIFF_TERM (HISPI_DIFF_TERM),
			.DQS_BIAS (HISPI_DQS_BIAS),
			.IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
			.IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
			.IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
			.IOSTANDARD (HISPI_IOSTANDARD)
			) ibufds_ibufgds0_i (
			.O (din[i]), // output
			.I (din_p[i]), // input
			.IB (din_n[i]) // input
			);

			idelay_nofine # (
			.IODELAY_GRP (IODELAY_GRP),
			.DELAY_VALUE (IDELAY_VALUE),
			.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
			.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
			) pxd_dly_i(
			.clk (mclk),
			.rst (mrst),
			.set (set_idelay[i]),
			.ld (ld_idelay),
			.delay (dly_data[3 + 8*i +: 5]),
			.data_in (din[i]),
			.data_out (din_dly[i])
			);

			iserdes_mem #(
			.DYN_CLKDIV_INV_EN("FALSE")
			) iserdes_pxd_i (
			.iclk(ipclk2x), // source-synchronous clock
			.oclk(ipclk2x), // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
			.oclk_div(ipclk), // oclk divided by 2, front aligned
			.inv_clk_div(1'b0), // invert oclk_div (this clock is shared between iserdes and oserdes. Works only in MEMORY_DDR3 mode?
			.rst(irst), // reset
			.d_direct(1'b0), // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
			.ddly(din_dly[i]), // serial input from idelay
			.dout(dout[4*i +:4]), // parallel data out
			.comb_out() // output
			);

			end
			endgenerate


			endmodule

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