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Commit 1ad303e0 authored by Andrey Filippov's avatar Andrey Filippov
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improving HiSPi decoding

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.project
View file @ 1ad303e0
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151115001220264.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151115151104872.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151115001220264.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151115151104872.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151115001220264.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151115151104872.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151115001220264.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151115151104872.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151115001220264.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151115151104872.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151115001220264.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151115151104872.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151115000630414.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151115150613168.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151115001220264.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151115151104872.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......
fpga_version.vh
View file @ 1ad303e0
......@@ -31,7 +31,8 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xcl -0.002 -0.004 2, utilization 15144 (77.07 %)
parameter FPGA_VERSION = 32'h03930070; // Fixing HiSPi xclk -0.049 -0.291 17, utilization 15139 (77.04%)
// parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xcl -0.002 -0.004 2, utilization 15144 (77.07 %)
// parameter FPGA_VERSION = 32'h0393006f; // Fixing JP4 mode - xclk -0.209/-2.744/23, utilization 15127 (76.98%)
// parameter FPGA_VERSION = 32'h0393006e; // Trying lane switch again after bug fix, failing 1 in ddr3_mclk -> ddr3_clk_div by -0.023
// parameter FPGA_VERSION = 32'h0393006d; // -1 with lane switch - does not work
......
includes/x393_parameters.vh
View file @ 1ad303e0
......@@ -598,7 +598,10 @@
parameter HISPI_MMCM1 = "FALSE",
parameter HISPI_MMCM2 = "TRUE",
parameter HISPI_MMCM3 = "FALSE",
parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
parameter HISPI_FIFO_DEPTH = 4,
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "FALSE", // Only possible with 2.5 power LVDS, not with 1.8V "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
......
py393/dbg/x393_mcntrl.pickle
View file @ 1ad303e0
This diff is collapsed.
py393/x393_jpeg.py
View file @ 1ad303e0
......@@ -857,6 +857,8 @@ write_sensor_i2c 0 1 0 0x30700002
#test pattern - fading color bars
write_sensor_i2c 0 1 0 0x30700003
print_sensor_i2c 0 0x3070 0xff 0x10 0
#test - running 8, 8-bit
write_sensor_i2c 0 1 0 0x30700101
#Exposure 0x800 lines
write_sensor_i2c 0 1 0 0x30120800
......@@ -878,6 +880,10 @@ print_sensor_i2c 0 0x31c6 0xff 0x10 0
compressor_control 0 2
jpeg_write "img.jpeg" 0
#setup JP4
setup_compressor 0 5 2 0 1 1 0 0 None None None None 1 384 364 2
#setup JPEG
setup_compressor 0 0 2 0 1 1 0 0 None None None None 1 384 364 2
#default gain = 0xa, set red and blue (outdoors)
write_sensor_i2c 0 1 0 0x30280014
......
py393/x393_sensor.py
View file @ 1ad303e0
......@@ -682,6 +682,17 @@ class X393Sensor(object):
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_DELAYS;
self.x393_axi_tasks.write_control_register(reg_addr + 1, data)
def set_sensor_fifo_lag(self,
num_sensor,
fifo_lag = 7):
"""
Set HiSPi sensor FIFO lag (when to start line output, ~= 1/2 FIFO size)
@param num_sensor - sensor port number (0..3)
@param fifo_lag - number of pixels to write to FIFO before starting output
"""
reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + vrlg.SENSIO_RADDR + vrlg.SENSIO_DELAYS;
self.x393_axi_tasks.write_control_register(reg_addr + 0, fifo_lag)
def set_sensor_io_jtag (self,
num_sensor,
pgmen = None, # <2: keep PGMEN, 2 - PGMEN low (inactive), 3 - high (active) enable JTAG control
......
sensor/sens_10398.v
View file @ 1ad303e0
......@@ -91,6 +91,10 @@ module sens_10398 #(
parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
parameter HISPI_FIFO_DEPTH = 4,
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
......@@ -158,6 +162,7 @@ module sens_10398 #(
reg [31:0] data_r;
// reg [3:0] set_idelay;
reg set_lanes_map; // set sequence of lanes im the composite pixel line
reg set_fifo_dly; // set how long to wait after strating to fill FIFOs (in items) ~= 1/2 2^FIFO_DEPTH
reg set_idelays;
reg set_iclk_phase;
reg set_ctrl_r;
......@@ -213,6 +218,9 @@ module sens_10398 #(
if (mrst) data_r <= 0;
else if (cmd_we) data_r <= cmd_data;
if (mrst) set_fifo_dly <= 0;
else set_fifo_dly <= cmd_we & (cmd_a==(SENSIO_DELAYS+0)); // TODO - add Symbolic names
if (mrst) set_lanes_map <= 0;
else set_lanes_map <= cmd_we & (cmd_a==(SENSIO_DELAYS+1));
......@@ -345,6 +353,10 @@ module sens_10398 #(
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK (HISPI_DELAY_CLK),
.HISPI_MMCM (HISPI_MMCM),
.HISPI_KEEP_IRST (HISPI_KEEP_IRST),
.HISPI_WAIT_ALL_LANES (HISPI_WAIT_ALL_LANES),
.HISPI_FIFO_DEPTH (HISPI_FIFO_DEPTH),
.HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
......@@ -352,6 +364,7 @@ module sens_10398 #(
.HISPI_IBUF_LOW_PWR (HISPI_IBUF_LOW_PWR),
.HISPI_IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.HISPI_IOSTANDARD (HISPI_IOSTANDARD)
) sens_hispi12l4_i (
.pclk (pclk), // input
.prst (prsts), //prst), // input
......@@ -366,7 +379,8 @@ module sens_10398 #(
.mclk (mclk), // input
.mrst (mrst), // input
.dly_data (data_r), // input[31:0]
.set_lanes_map (set_lanes_map), // input[3:0]
.set_lanes_map (set_lanes_map), // input
.set_fifo_dly (set_fifo_dly), // input
.set_idelay ({4{set_idelays}}), // input[3:0]
.ld_idelay (ld_idelay), // input
.set_clk_phase (set_iclk_phase), // input
......
sensor/sens_hispi12l4.v
View file @ 1ad303e0
......@@ -62,14 +62,17 @@ module sens_hispi12l4#(
parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
parameter HISPI_FIFO_DEPTH = 4,
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA),
parameter HISPI_KEEP_IRST = 5 // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA),
)(
input pclk, // global clock input, pixel rate (220MHz for MT9F002)
input prst, // reset @pclk (add sensor reset here)
......@@ -91,6 +94,7 @@ module sens_hispi12l4#(
input mrst,
input [HISPI_NUMLANES * 8-1:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
input set_lanes_map, // set number of physical lane for each logical one
input set_fifo_dly,
input [HISPI_NUMLANES-1:0] set_idelay, // mclk synchronous load idelay value
input ld_idelay, // mclk synchronous set idealy value
input set_clk_phase, // mclk synchronous set idealy value
......@@ -108,15 +112,20 @@ module sens_hispi12l4#(
wire ipclk; // re-generated half HiSPi clock (165 MHz)
wire ipclk2x;// re-generated HiSPi clock (330 MHz)
wire [HISPI_NUMLANES * 4-1:0] sns_d;
localparam WAIT_ALL_LANES = 4'h8; // number of output pixel cycles to wait after the earliest lane
localparam FIFO_DEPTH = 4;
// localparam WAIT_ALL_LANES = 4'h8; // number of output pixel cycles to wait after the earliest lane
// localparam FIFO_DEPTH = 4;
reg [HISPI_KEEP_IRST-1:0] irst_r;
wire irst = irst_r[0];
reg [HISPI_NUMLANES * 2-1:0] lanes_map;
reg [HISPI_NUMLANES * 4-1:0] logical_lanes4;
reg [HISPI_FIFO_DEPTH-1:0] fifo_out_dly_mclk;
reg [HISPI_FIFO_DEPTH-1:0] fifo_out_dly;
always @ (posedge mclk) begin
if (mrst) lanes_map <= DEFAULT_LANE_MAP; //{2'h3,2'h2,2'h1,2'h0}; // 1-to-1 default map
else if (set_lanes_map) lanes_map <= dly_data[HISPI_NUMLANES * 2-1:0];
if (mrst) fifo_out_dly_mclk <= HISPI_FIFO_START;
else if (set_fifo_dly) fifo_out_dly_mclk <= dly_data[HISPI_FIFO_DEPTH-1:0];
end
//non-parametrized lane switch (4x4)
......@@ -127,6 +136,9 @@ module sens_hispi12l4#(
logical_lanes4[15:12] <= sns_d[{lanes_map[7:6],2'b0} +:4];
end
always @(posedge ipclk) begin
fifo_out_dly <= fifo_out_dly_mclk;
end
sens_hispi_clock #(
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
......@@ -231,6 +243,7 @@ module sens_hispi12l4#(
reg sof_pclk;
// wire [HISPI_NUMLANES-1:0] sol_pclk = rd_run & ~rd_run_d;
wire sol_pclk = |(rd_run & ~rd_run_d); // possibly multi-cycle
reg start_fifo_re; // start reading FIFO - single-cycle
reg [HISPI_NUMLANES-1:0] good_lanes; // lanes that started active line OK
reg [HISPI_NUMLANES-1:0] fifo_re;
reg [HISPI_NUMLANES-1:0] fifo_re_r;
......@@ -247,6 +260,7 @@ module sens_hispi12l4#(
assign hact_out = hact_r;
assign sof = sof_pclk;
......@@ -273,6 +287,8 @@ module sens_hispi12l4#(
rd_run_d <= rd_run;
start_fifo_re <= sol_pclk && !rd_line; // sol_pclk may be multi-cycle
sof_pclk <= vact_pclk_strt[0] && ! vact_pclk_strt[1];
if (prst || sof_pclk) rd_line <= 0;
......@@ -293,7 +309,8 @@ module sens_hispi12l4#(
({12 {fifo_re_r[3] & rd_run[3]}} & fifo_out[3 * 12 +:12]); */
if (prst) fifo_re <= 0;
else if (sol_pclk || (rd_line && fifo_re[HISPI_NUMLANES - 1])) fifo_re <= 1;
// else if (sol_pclk || (rd_line && fifo_re[HISPI_NUMLANES - 1])) fifo_re <= 1;
else if (start_fifo_re || (rd_line && fifo_re[HISPI_NUMLANES - 1])) fifo_re <= 1;
else fifo_re <= fifo_re << 1;
// if (prst || (hact_off && (|(good_lanes & ~rd_run)))) hact_r <= 0;
......@@ -310,7 +327,7 @@ module sens_hispi12l4#(
) dly_16_start_line_i (
.clk (pclk), // input
.rst (1'b0), // input
.dly (WAIT_ALL_LANES), // input[3:0]
.dly (HISPI_WAIT_ALL_LANES), // input[3:0]
.din (rd_line && !rd_line_r), // input[0:0]
.dout (sol_all_dly) // output[0:0]
);
......@@ -371,9 +388,9 @@ module sens_hispi12l4#(
.eol (hispi_eol[i]) // output reg
);
sens_hispi_fifo #(
.COUNT_START (7),
// .COUNT_START (HISPI_FIFO_START),
.DATA_WIDTH (12),
.DATA_DEPTH (FIFO_DEPTH)
.DATA_DEPTH (HISPI_FIFO_DEPTH)
) sens_hispi_fifo_i (
.ipclk (ipclk), // input
.irst (irst), // input
......@@ -381,6 +398,7 @@ module sens_hispi12l4#(
.sol (hispi_sol[i] && !(hispi_embed[i] && ignore_embedded_ipclk)), // input
.eol (hispi_eol[i]), // input
.din (hispi_aligned[12*i +: 12]), // input[11:0]
.out_dly (fifo_out_dly), // input[3:0]
.pclk (pclk), // input
.prst (prst), // input
.re (fifo_re[i]), // input
......
sensor/sens_hispi_fifo.v
View file @ 1ad303e0
......@@ -34,7 +34,7 @@
`timescale 1ns/1ps
module sens_hispi_fifo#(
parameter COUNT_START = 7, // wait these many samples input before starting output
// parameter COUNT_START = 7, // wait these many samples input before starting output
parameter DATA_WIDTH = 12,
parameter DATA_DEPTH = 4 // >=3
) (
......@@ -44,6 +44,7 @@ module sens_hispi_fifo#(
input sol, // start of line - 1 cycle before dv
input eol, // end of line - last dv
input [DATA_WIDTH-1:0] din,
input [DATA_DEPTH-1:0] out_dly, // wait these many samples input before starting output
input pclk,
input prst,
input re,
......@@ -55,8 +56,11 @@ module sens_hispi_fifo#(
reg [DATA_DEPTH:0] ra;
wire line_start_pclk;
reg line_run_ipclk;
reg line_run_ipclk_d; // to generate start for very short lines (may just use small out_dly value)
reg line_run_pclk;
reg run_r;
reg start_sent;
reg start_out_ipclk;
assign run = run_r;
// TODO: generate early done by comparing ra with (wa-1) - separate counter
......@@ -69,6 +73,15 @@ module sens_hispi_fifo#(
if (irst || eol) line_run_ipclk <= 0;
else if (sol) line_run_ipclk <= 1;
if (!line_run_ipclk) start_sent <= 0;
else if (start_out_ipclk) start_sent <= 1;
line_run_ipclk_d <= line_run_ipclk;
if (irst) start_out_ipclk <= 0;
else start_out_ipclk <= line_run_ipclk? (!start_sent && we && (wa[DATA_DEPTH-1:0] == out_dly)) : (line_run_ipclk_d && !start_sent);
end
always @(posedge pclk) begin
......@@ -91,7 +104,8 @@ module sens_hispi_fifo#(
.rst (irst), // input
.src_clk (ipclk), // input
.dst_clk (pclk), // input
.in_pulse (we && (wa == COUNT_START)), // input
// .in_pulse (we && (wa == COUNT_START)), // input
.in_pulse (start_out_ipclk), // input
.out_pulse (line_start_pclk), // output
.busy() // output
);
......
sensor/sensor_channel.v
View file @ 1ad303e0
......@@ -257,6 +257,10 @@ module sensor_channel#(
parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
parameter HISPI_FIFO_DEPTH = 4,
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
......@@ -778,6 +782,10 @@ module sensor_channel#(
.HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK (HISPI_DELAY_CLK),
.HISPI_MMCM (HISPI_MMCM),
.HISPI_KEEP_IRST (HISPI_KEEP_IRST),
.HISPI_WAIT_ALL_LANES (HISPI_WAIT_ALL_LANES),
.HISPI_FIFO_DEPTH (HISPI_FIFO_DEPTH),
.HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
......
sensor/sensors393.v
View file @ 1ad303e0
......@@ -289,6 +289,10 @@ module sensors393 #(
parameter HISPI_MMCM1 = "TRUE",
parameter HISPI_MMCM2 = "TRUE",
parameter HISPI_MMCM3 = "TRUE",
parameter HISPI_KEEP_IRST = 5, // number of cycles to keep irst on after release of prst (small number - use 1 hot)
parameter HISPI_WAIT_ALL_LANES = 4'h8, // number of output pixel cycles to wait after the earliest lane
parameter HISPI_FIFO_DEPTH = 4,
parameter HISPI_FIFO_START = 7,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
......@@ -610,7 +614,10 @@ module sensors393 #(
.HISPI_DELAY_CLK ((i & 2) ? ((i & 1) ? HISPI_DELAY_CLK3 : HISPI_DELAY_CLK2) : ((i & 1) ?HISPI_DELAY_CLK1 : HISPI_DELAY_CLK0 )),
.HISPI_MMCM ((i & 2) ? ((i & 1) ? HISPI_MMCM3 : HISPI_MMCM2) : ((i & 1) ?HISPI_MMCM1 : HISPI_MMCM0 )),
.HISPI_KEEP_IRST (HISPI_KEEP_IRST),
.HISPI_WAIT_ALL_LANES (HISPI_WAIT_ALL_LANES),
.HISPI_FIFO_DEPTH (HISPI_FIFO_DEPTH),
.HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
......
x393.v
View file @ 1ad303e0
......@@ -1647,7 +1647,10 @@ assign axi_grst = axi_rst_pre;
.HISPI_MMCM1 (HISPI_MMCM1),
.HISPI_MMCM2 (HISPI_MMCM2),
.HISPI_MMCM3 (HISPI_MMCM3),
.HISPI_KEEP_IRST (HISPI_KEEP_IRST),
.HISPI_WAIT_ALL_LANES (HISPI_WAIT_ALL_LANES),
.HISPI_FIFO_DEPTH (HISPI_FIFO_DEPTH),
.HISPI_FIFO_START (HISPI_FIFO_START),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS),
......
x393_testbench03.sav
View file @ 1ad303e0
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Sun Nov 15 06:56:54 2015
[*] Sun Nov 15 22:03:05 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151114232724798.fst"
[dumpfile_mtime] "Sun Nov 15 06:56:52 2015"
[dumpfile_size] 200323649
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151115142219571.fst"
[dumpfile_mtime] "Sun Nov 15 22:02:48 2015"
[dumpfile_size] 287600988
[savefile] "/home/andrey/git/x393/x393_testbench03.sav"
[timestart] 111246500
[timestart] 69077000
[size] 1823 1180
[pos] 0 0
*-15.001225 111341667 107947388 109212388 108561548 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-18.688070 69667459 107947388 109212388 108561548 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].
......@@ -75,7 +75,7 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
[sst_width] 298
[sst_width] 340
[signals_width] 321
[sst_expanded] 1
[sst_vpaned_height] 514
......@@ -1114,9 +1114,9 @@ x393_testbench03.par12_hispi_psp4l0_i.simul_clk_div_mult_i.en
@1401200
-clk_mult_div
-par_hispi_sel
@c00200
-sens_hispi_12l4
@800200
-sens_hispi_12l4
@c00201
-lane0
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.ipclk
......@@ -1183,11 +1183,81 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.shift_val[1:0]
@1001200
-group_end
@1401201
-lane0
@800200
-fifo0
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.out_dly[3:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.we
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.wa[4:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.din[11:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.start_out_ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.start_sent
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.line_run_ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.line_run_ipclk_d
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.re
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.run
@200
-
@1000200
-fifo0
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.set_lanes_map
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.set_fifo_dly
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.lanes_map[7:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_out_dly_mclk[3:0]
@200
-other
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_line
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_line_r
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sol_all_dly
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.rd_run[3:0]
@1001200
-group_end
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.good_lanes[3:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sol_pclk
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re[3:0]
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re_r[3:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re_r[3:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re_r[3:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re_r[3:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.fifo_re_r[3:0]
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.pxd_out_pre[11:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.pxd_out[11:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hact_out
@1001200
-group_end
-group_end
@200
-
@1000200
-lane0
@1401200
-sens_hispi_12l4
@c00200
-par_hspi_0
......@@ -2476,9 +2546,7 @@ x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmpr
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.col_inc[9:4]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.macroblock_x[6:0]
@23
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.extra_start_addr_w[9:0]
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.extra_start_addr_r[5:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.mb_start_addr[9:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_pixel_buf_iface_i.mb_col_number[2:0]
......
x393_testbench03.tf
View file @ 1ad303e0
......@@ -2812,8 +2812,11 @@ task setup_sensor_channel;
set_sensor_io_dly (
num_sensor, // input [1:0] num_sensor;
`ifdef HISPI
128'h33404850_58606870_000000e4_00000007); // input [127:0] dly; // {delays_delays_lane-map_fifo-start_delay]
`else
128'h33404850_58606870_78808890_98a0a8b0 ); //input [127:0] dly; // {mmsm_phase, bpf, vact, hact, pxd11,...,pxd0]
`endif
TEST_TITLE = "IO_SETUP";
$display("===================== TEST_%s =========================",TEST_TITLE);
set_sensor_io_width(
......
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