Commit 1902d5ce authored by Andrey Filippov's avatar Andrey Filippov

chaneged handling of the shared parameters, added defaults and saving modified...

chaneged handling of the shared parameters, added defaults and saving modified parameters as Verilog include file
parent e6b5bfc1
This diff is collapsed.
...@@ -105,13 +105,13 @@ ...@@ -105,13 +105,13 @@
parameter CHNBUF_READ_LATENCY = 2, //1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data)) parameter CHNBUF_READ_LATENCY = 2, //1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter DFLT_DQS_PATTERN= 8'h55, parameter DFLT_DQS_PATTERN= 8'haa, // TODO: make work for the simulator too 8'h55,
parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00 parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00
parameter DFLT_DQ_TRI_ON_PATTERN= 4'h7, // DQ tri-state control word, first when enabling output parameter DFLT_DQ_TRI_ON_PATTERN= 4'h7, // DQ tri-state control word, first when enabling output
parameter DFLT_DQ_TRI_OFF_PATTERN= 4'he, // DQ tri-state control word, first after disabling output parameter DFLT_DQ_TRI_OFF_PATTERN= 4'he, // DQ tri-state control word, first after disabling output
parameter DFLT_DQS_TRI_ON_PATTERN= 4'h3, // DQS tri-state control word, first when enabling output parameter DFLT_DQS_TRI_ON_PATTERN= 4'h3, // DQS tri-state control word, first when enabling output
parameter DFLT_DQS_TRI_OFF_PATTERN=4'hc, // DQS tri-state control word, first after disabling output parameter DFLT_DQS_TRI_OFF_PATTERN=4'hc, // DQS tri-state control word, first after disabling output
parameter DFLT_WBUF_DELAY= 4'h8, // write levelling - 7! parameter DFLT_WBUF_DELAY= 4'h9, // TODO: Find the reason - simulation needs 8, target - 9
parameter DFLT_INV_CLK_DIV= 1'b0, parameter DFLT_INV_CLK_DIV= 1'b0,
parameter DFLT_CHN_EN= 16'h0, // channel mask to be enabled at reset parameter DFLT_CHN_EN= 16'h0, // channel mask to be enabled at reset
......
-v -v
-d TARGET_MODE=1 -d TARGET_MODE=1
-f ../system_defines.vh -f ../system_defines.vh
-f ../includes/x393_parameters.vh ../includes/x393_localparams.vh -f ../includes/x393_parameters.vh ../includes/x393_cur_params_target.vh ../includes/x393_localparams.vh
-l ../includes/x393_cur_params_target_gen.vh
-p NEWPAR='h3ff -p NEWPAR='h3ff
-c write_mem 0x377 25 -c write_mem 0x377 25
-c read_mem 0x3ff -c read_mem 0x3ff
......
-d TARGET_MODE=1 -d TARGET_MODE=1
-f /usr/local/verilog/system_defines.vh -f /usr/local/verilog/system_defines.vh
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_localparams.vh -f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p NEWPAR='h3ff -p NEWPAR='h3ff
-i -i
\ No newline at end of file
...@@ -31,17 +31,22 @@ import re ...@@ -31,17 +31,22 @@ import re
import os import os
import string import string
from verilog_utils import getParWidth from verilog_utils import getParWidth
#import vrlg
"""
class VerilogParameters(object): #this is Borg class VerilogParameters(object): #this is Borg
__shared_state = {} __shared_state = {}
def __init__(self, parameters=None): def __init__(self, parameters=None):
self.__dict__ = self.__shared_state self.__dict__ = self.__shared_state
if (parameters): if (parameters):
vrlg.init_vars(self.parsToDict(parameters))
def parsToDict(self, parameters=None):
adict={} adict={}
for parName in parameters: for parName in parameters:
adict[parName]= parameters[parName][0] adict[parName]= parameters[parName][0]
adict[parName+"__TYPE"]=parameters[parName][1] adict[parName+"__TYPE"]=parameters[parName][1]
adict[parName+"__RAW"]= parameters[parName][2] adict[parName+"__RAW"]= parameters[parName][2]
self.__dict__.update(adict) return adict
"""
class ImportVerilogParameters(object): class ImportVerilogParameters(object):
''' '''
...@@ -67,6 +72,13 @@ class ImportVerilogParameters(object): ...@@ -67,6 +72,13 @@ class ImportVerilogParameters(object):
self.defines=defines.copy() self.defines=defines.copy()
if rootPath: if rootPath:
self.rootPath=rootPath.rstrip(os.sep) self.rootPath=rootPath.rstrip(os.sep)
def parsToDict(self, parameters=None):
adict={}
for parName in parameters:
adict[parName]= parameters[parName][0]
adict[parName+"__TYPE"]=parameters[parName][1]
adict[parName+"__RAW"]= parameters[parName][2]
return adict
''' '''
http://stackoverflow.com/questions/241327/python-snippet-to-remove-c-and-c-comments http://stackoverflow.com/questions/241327/python-snippet-to-remove-c-and-c-comments
''' '''
...@@ -338,23 +350,19 @@ class ImportVerilogParameters(object): ...@@ -338,23 +350,19 @@ class ImportVerilogParameters(object):
pass pass
def parsePrimary(start=0): def parsePrimary(start=0):
return useBest(useBest(useBest(parseString(start),parseNumber(start)),parseRealNumber(start)),parseParameter(start)) return useBest(useBest(useBest(parseString(start),parseNumber(start)),parseRealNumber(start)),parseParameter(start))
def parsePrimaryOrBinary(start=0):
operand1=parsePrimary(start) def parseBinary(operand1, opStart):
if (self.verbose>2) and (start !=0):
print ("parsePrimaryOrBinary(start=%d), line=%s, result=%s"%(start,line,str(operand1)))
if not operand1: print (line)
opStart=skipWS(operand1[2])
if opStart == len(line): # just primary
return operand1
# Try binary operation
op=getBinOp(opStart) op=getBinOp(opStart)
if not op: if not op:
print("ERROR: Next token in '%s' (starting from %s) is not a binary operation"%(line,line[opStart:])) return None # not a binary operation
return None # if "( (DLY_LANE0_IDELAY & 8'hff)" in line:
# print("parseBinary(): %d(%d): %s"%(opStart,len(line),line[opStart:]))
# if (opStart>530):
# print ("(pre)Last one!")
start2=skipWS(opStart+len(op[0])) start2=skipWS(opStart+len(op[0]))
if (self.verbose>2): if (self.verbose>2):
print ("line=%s"%line) print ("line=%s"%line)
print ("start=%d, opStart=%d, start2=%d"%(start,opStart, start2)) print ("opStart=%d, start2=%d"%(opStart, start2))
operand2=parseExp(start2) operand2=parseExp(start2)
if not operand2: if not operand2:
print("ERROR: Could not get the second operand for '%s' in '%s'"%(op[0],line)) print("ERROR: Could not get the second operand for '%s' in '%s'"%(op[0],line))
...@@ -376,39 +384,91 @@ class ImportVerilogParameters(object): ...@@ -376,39 +384,91 @@ class ImportVerilogParameters(object):
width=32 width=32
return (exp[0],"[%d:0]"%(width-1),operand2[2]) return (exp[0],"[%d:0]"%(width-1),operand2[2])
def parseExp(start=0):
def parsePrimaryOrBinary(start=0):
operand1=parsePrimary(start)
if (self.verbose>2) and (start !=0):
print ("parsePrimaryOrBinary(start=%d), line=%s, result=%s"%(start,line,str(operand1)))
if not operand1: print (line)
# Try binary operation
# repeat until end of line or ')'
while True:
opStart=skipWS(operand1[2])
if (opStart == len(line)) : # or (line[opStart] == ')'): # just primary
return operand1
if line[opStart] == ')': # just primary
return operand1
binRes=parseBinary(operand1, opStart)
if not binRes:
print ("opStart=%d, len(line)=%d, operand1=%s"%(opStart,len(line),str(operand1)))
print()
print(line)
raise Exception("ERROR: Next token in '%s' (starting from '%s') is not a binary operation"%
(line,line[opStart:]))
operand1=binRes
def parseExp(start=0, topExpr=False):
start=skipWS(start) start=skipWS(start)
if start>=len(line): if start>=len(line):
print ("ERROR: EOL reached when expression was expected in '%s'"%line) print ("ERROR: EOL reached when expression was expected in '%s'"%line)
return None return None
if line[start]=='(': # if "( (DLY_LANE0_IDELAY & 8'hff)" in line:
exp=parseExp(start+1) # print (line)
# if (line[0]=='(') and (start==0):
# print("Line starts with '(")
if (line[start]=='(') or topExpr:
# if (line[start]=='('):
if not topExpr:
start+=1
exp=parseExp(start)
if not exp: if not exp:
print ("ERROR: failed to evaluate expression in '%s' (starting from '%s'"%(line,line[start:])) print ("ERROR: failed to evaluate expression in '%s' (starting from '%s'"%(line,line[start:]))
return None return None
while True:
endPos=skipWS(exp[2]) endPos=skipWS(exp[2])
if endPos >= len(line): if (endPos >= len(line)) and (not topExpr):
print ("ERROR: EOL reached when closing ')' was expected in '%s'"%line) print ("ERROR: EOL reached when closing ')' was expected in '%s'"%line)
return None return None
if line[endPos] != ")": if (endPos >= len(line)) or (line[endPos] == ")"): # (endPos >= len(line)) can only be here if topExpr
print ("ERROR: Found '%s'when closing ')' was expected in '%s'"%(line[endPos],line))
return None
endPos=skipWS(endPos+1) endPos=skipWS(endPos+1)
return (exp[0],"[%d:0]"%(exp[1]-1),endPos) if (exp is None) or (exp[1] is None):
print ("line=%s"%(line))
print ()
# print ("exp=%s"%(str(exp)))
if isinstance(exp[0],(int,long)):
width=getParWidth(exp[1])
elif isinstance(exp[0],str):
width=8*len(exp[0])
else:
# width=0
# print ("Unrecognized width in %s"%(str(exp)))
# print ("line=%s"%(line))
return (exp[0],exp[1],endPos)
return (exp[0],"[%d:0]"%(width-1),endPos)
# here may be binOp
binRes=parseBinary(exp, endPos)
if not binRes:
print ("endPos=%d, len(line)=%d, exp=%s"%(endPos,len(line),str(exp)))
raise Exception("ERROR: Next token in '%s' (starting from '%s') is not a binary operation or closing')'"%
(line,line[endPos:]))
exp=binRes
return parsePrimaryOrBinary(start) return parsePrimaryOrBinary(start)
''' '''
parseExpression top level code parseExpression top level code
no support for bit select, &&, ||, ~ ! ? and more... no support for bit select, &&, ||, ~ ! ? and more...
''' '''
return parseExp(0) return parseExp(0,True) # call top level expression that does not need enclosing ()
''' '''
Read parameters defined in parameter port list (inside #(,,,), comma separated (last may have no comma) Read parameters defined in parameter port list (inside #(,,,), comma separated (last may have no comma)
Adds parsed parameters to the dictionary Adds parsed parameters to the dictionary
''' '''
def readParameterPortList(self,path,portMode=True): def readParameterPortList(self,path,portMode=True):
if (self.verbose>2): if (self.verbose>0):
print ("readParameterPortList:Processing %s"%(path)) print ("readParameterPortList:Processing %s"%(os.path.abspath(path)))
with open (path, "r") as myfile: #with will close file when done with open (path, "r") as myfile: #with will close file when done
text=myfile.read() text=myfile.read()
# remove /* */ comments # remove /* */ comments
......
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...@@ -56,7 +56,7 @@ def concat(items): ...@@ -56,7 +56,7 @@ def concat(items):
width=0 width=0
for vw in reversed(items): for vw in reversed(items):
v=vw[0] v=vw[0]
if not isinstance(v,int): if not isinstance(v,(int,long)):
if v: if v:
v=1 # So True/False will also work, not just 0/1 v=1 # So True/False will also work, not just 0/1
else: else:
...@@ -150,7 +150,7 @@ def checkIntArgs(names,var_dict): ...@@ -150,7 +150,7 @@ def checkIntArgs(names,var_dict):
v=var_dict[name] v=var_dict[name]
except: except:
raise Exception("ERROR: '%s' is not among %s"%(name,str(var_dict.keys()))) raise Exception("ERROR: '%s' is not among %s"%(name,str(var_dict.keys())))
if not isinstance(v,int): if not isinstance(v,(int,long)):
print ("Expected an integer for '%s', got '%s"%(name,v)) print ("Expected an integer for '%s', got '%s"%(name,v))
try: try:
d=int(v,16) d=int(v,16)
......
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...@@ -32,7 +32,7 @@ __status__ = "Development" ...@@ -32,7 +32,7 @@ __status__ = "Development"
#import x393_mem #import x393_mem
#x393_pio_sequences #x393_pio_sequences
import random import random
from import_verilog_parameters import VerilogParameters #from import_verilog_parameters import VerilogParameters
from x393_mem import X393Mem from x393_mem import X393Mem
from x393_axi_control_status import X393AxiControlStatus from x393_axi_control_status import X393AxiControlStatus
from x393_pio_sequences import X393PIOSequences from x393_pio_sequences import X393PIOSequences
...@@ -44,6 +44,7 @@ from x393_mcntrl_buffers import X393McntrlBuffers ...@@ -44,6 +44,7 @@ from x393_mcntrl_buffers import X393McntrlBuffers
#from x393_axi_control_status import concat, bits #from x393_axi_control_status import concat, bits
#from time import sleep #from time import sleep
from verilog_utils import checkIntArgs,smooth2d from verilog_utils import checkIntArgs,smooth2d
#import vrlg
NUM_FINE_STEPS= 5 NUM_FINE_STEPS= 5
class X393McntrlAdjust(object): class X393McntrlAdjust(object):
...@@ -63,11 +64,31 @@ class X393McntrlAdjust(object): ...@@ -63,11 +64,31 @@ class X393McntrlAdjust(object):
self.x393_pio_sequences= X393PIOSequences(debug_mode,dry_mode) self.x393_pio_sequences= X393PIOSequences(debug_mode,dry_mode)
self.x393_mcntrl_timing= X393McntrlTiming(debug_mode,dry_mode) self.x393_mcntrl_timing= X393McntrlTiming(debug_mode,dry_mode)
self.x393_mcntrl_buffers= X393McntrlBuffers(debug_mode,dry_mode) self.x393_mcntrl_buffers= X393McntrlBuffers(debug_mode,dry_mode)
self.__dict__.update(VerilogParameters.__dict__["_VerilogParameters__shared_state"]) # Add verilog parameters to the class namespace # self.__dict__.update(VerilogParameters.__dict__["_VerilogParameters__shared_state"]) # Add verilog parameters to the class namespace
try: try:
self.verbose=self.VERBOSE self.verbose=self.VERBOSE
except: except:
pass pass
#//SET DQ ODELAY=[['0xd9', '0xdb', '0xdc', '0xd4', '0xe0', '0xda', '0xd4', '0xd8'], ['0xdc', '0xe0', '0xf1', '0xdc', '0xe0', '0xdc', '0xdc', '0xdc']]
def format_dq_to_verilog(self,
estr):
"""
Convert dq delays list to the form to paste to the Verilog parameters code
<estr> quoted string, such as:
"[['0xd9', '0xdb', '0xdc', '0xd4', '0xe0', '0xda', '0xd4', '0xd8'], ['0xdc', '0xe0', '0xf1', '0xdc', '0xe0', '0xdc', '0xdc', '0xdc']]"
Returns a pair of strings to paste
"""
se=eval(estr) # now a list of list of strings
for l in se:
for i,v in enumerate(l):
l[i]=int(v,16)
for lane in range(2):
print("lane%d = 64'h"%lane,end="")
for i in range(len(se[lane])):
print("%02x"%se[lane][-i-1],end="")
print()
def split_delay(self,dly): def split_delay(self,dly):
""" """
...@@ -970,3 +991,7 @@ class X393McntrlAdjust(object): ...@@ -970,3 +991,7 @@ class X393McntrlAdjust(object):
min_diff, # minimal difference between primary delay steps to process min_diff, # minimal difference between primary delay steps to process
True, #adjust, not scan True, #adjust, not scan
verbose) verbose)
\ No newline at end of file
...@@ -31,13 +31,14 @@ __status__ = "Development" ...@@ -31,13 +31,14 @@ __status__ = "Development"
#import sys #import sys
#import x393_mem #import x393_mem
#x393_pio_sequences #x393_pio_sequences
from import_verilog_parameters import VerilogParameters #from import_verilog_parameters import VerilogParameters
from x393_mem import X393Mem from x393_mem import X393Mem
from x393_axi_control_status import X393AxiControlStatus from x393_axi_control_status import X393AxiControlStatus
#from verilog_utils import * # concat, bits #from verilog_utils import * # concat, bits
#from verilog_utils import hx, concat, bits, getParWidth #from verilog_utils import hx, concat, bits, getParWidth
#from verilog_utils import concat, getParWidth #from verilog_utils import concat, getParWidth
#from x393_axi_control_status import concat, bits #from x393_axi_control_status import concat, bits
import vrlg
class X393McntrlBuffers(object): class X393McntrlBuffers(object):
DRY_MODE= True # True DRY_MODE= True # True
DEBUG_MODE=1 DEBUG_MODE=1
...@@ -50,7 +51,7 @@ class X393McntrlBuffers(object): ...@@ -50,7 +51,7 @@ class X393McntrlBuffers(object):
self.DRY_MODE=dry_mode self.DRY_MODE=dry_mode
self.x393_mem=X393Mem(debug_mode,dry_mode) self.x393_mem=X393Mem(debug_mode,dry_mode)
self.x393_axi_tasks=X393AxiControlStatus(debug_mode,dry_mode) self.x393_axi_tasks=X393AxiControlStatus(debug_mode,dry_mode)
self.__dict__.update(VerilogParameters.__dict__["_VerilogParameters__shared_state"]) # Add verilog parameters to the class namespace # self.__dict__.update(VerilogParameters.__dict__["_VerilogParameters__shared_state"]) # Add verilog parameters to the class namespace
try: try:
self.verbose=self.VERBOSE self.verbose=self.VERBOSE
except: except:
...@@ -71,14 +72,14 @@ class X393McntrlBuffers(object): ...@@ -71,14 +72,14 @@ class X393McntrlBuffers(object):
""" """
if self.DEBUG_MODE > 1: if self.DEBUG_MODE > 1:
print("====== write_block_scanline_chn:%d page: %x X=0x%x Y=0x%x num=%dt"%(chn, page, startX, startY,num_bursts)) print("====== write_block_scanline_chn:%d page: %x X=0x%x Y=0x%x num=%dt"%(chn, page, startX, startY,num_bursts))
if chn == 0: start_addr=self.MCONTR_BUF0_WR_ADDR + (page << 8) if chn == 0: start_addr=vrlg.MCONTR_BUF0_WR_ADDR + (page << 8)
elif chn == 1: start_addr=self.MCONTR_BUF1_WR_ADDR + (page << 8) elif chn == 1: start_addr=vrlg.MCONTR_BUF1_WR_ADDR + (page << 8)
elif chn == 2: start_addr=self.MCONTR_BUF2_WR_ADDR + (page << 8) elif chn == 2: start_addr=vrlg.MCONTR_BUF2_WR_ADDR + (page << 8)
elif chn == 3: start_addr=self.MCONTR_BUF3_WR_ADDR + (page << 8) elif chn == 3: start_addr=vrlg.MCONTR_BUF3_WR_ADDR + (page << 8)
elif chn == 4: start_addr=self.MCONTR_BUF4_WR_ADDR + (page << 8) elif chn == 4: start_addr=vrlg.MCONTR_BUF4_WR_ADDR + (page << 8)
else: else:
print("**** ERROR: Invalid channel for write_block_scanline_chn = %d"% chn) print("**** ERROR: Invalid channel for write_block_scanline_chn = %d"% chn)
start_addr = self.MCONTR_BUF0_WR_ADDR+ (page << 8); start_addr = vrlg.MCONTR_BUF0_WR_ADDR+ (page << 8);
num_words=num_bursts << 2; num_words=num_bursts << 2;
self.write_block_incremtal (start_addr, num_words, (startX<<2) + (startY<<16));# 1 of startX is 8x16 bit, 16 bytes or 4 32-bit words self.write_block_incremtal (start_addr, num_words, (startX<<2) + (startY<<16));# 1 of startX is 8x16 bit, 16 bytes or 4 32-bit words
...@@ -95,7 +96,7 @@ class X393McntrlBuffers(object): ...@@ -95,7 +96,7 @@ class X393McntrlBuffers(object):
xor=num_words_or_data_list[1] xor=num_words_or_data_list[1]
num_words_or_data_list=num_words_or_data_list[0] num_words_or_data_list=num_words_or_data_list[0]
if isinstance (num_words_or_data_list,int): if isinstance (num_words_or_data_list,(int,long)):
data=[] data=[]
for i in range(num_words_or_data_list): for i in range(num_words_or_data_list):
data.append(xor ^(i | (((i + 7) & 0xff) << 8) | (((i + 23) & 0xff) << 16) | (((i + 31) & 0xff) << 24))) data.append(xor ^(i | (((i + 7) & 0xff) << 8) | (((i + 23) & 0xff) << 16) | (((i + 31) & 0xff) << 24)))
...@@ -144,14 +145,14 @@ class X393McntrlBuffers(object): ...@@ -144,14 +145,14 @@ class X393McntrlBuffers(object):
print("=== [%s]"%str(num_words_or_data_list)) print("=== [%s]"%str(num_words_or_data_list))
print("===") print("===")
start_addr=-1 start_addr=-1
if chn==0:start_addr=self.MCONTR_BUF0_WR_ADDR + (page << 8) if chn==0:start_addr=vrlg.MCONTR_BUF0_WR_ADDR + (page << 8)
elif chn==1:start_addr=self.MCONTR_BUF1_WR_ADDR + (page << 8) elif chn==1:start_addr=vrlg.MCONTR_BUF1_WR_ADDR + (page << 8)
elif chn==2:start_addr=self.MCONTR_BUF2_WR_ADDR + (page << 8) elif chn==2:start_addr=vrlg.MCONTR_BUF2_WR_ADDR + (page << 8)
elif chn==3:start_addr=self.MCONTR_BUF3_WR_ADDR + (page << 8) elif chn==3:start_addr=vrlg.MCONTR_BUF3_WR_ADDR + (page << 8)
elif chn==4:start_addr=self.MCONTR_BUF4_WR_ADDR + (page << 8) elif chn==4:start_addr=vrlg.MCONTR_BUF4_WR_ADDR + (page << 8)
else: else:
print("**** ERROR: Invalid channel for write buffer = %d"% chn) print("**** ERROR: Invalid channel for write buffer = %d"% chn)
start_addr = self.MCONTR_BUF0_WR_ADDR+ (page << 8) start_addr = vrlg.MCONTR_BUF0_WR_ADDR+ (page << 8)
self.write_block_buf (start_addr, num_words_or_data_list) self.write_block_buf (start_addr, num_words_or_data_list)
...@@ -189,13 +190,13 @@ class X393McntrlBuffers(object): ...@@ -189,13 +190,13 @@ class X393McntrlBuffers(object):
<show_rslt> print buffer data read <show_rslt> print buffer data read
""" """
start_addr=-1 start_addr=-1
if chn==0: start_addr=self.MCONTR_BUF0_RD_ADDR + (page << 8) if chn==0: start_addr=vrlg.MCONTR_BUF0_RD_ADDR + (page << 8)
elif chn==1: start_addr=self.MCONTR_BUF1_RD_ADDR + (page << 8) elif chn==1: start_addr=vrlg.MCONTR_BUF1_RD_ADDR + (page << 8)
elif chn==2: start_addr=self.MCONTR_BUF2_RD_ADDR + (page << 8) elif chn==2: start_addr=vrlg.MCONTR_BUF2_RD_ADDR + (page << 8)
elif chn==3: start_addr=self.MCONTR_BUF3_RD_ADDR + (page << 8) elif chn==3: start_addr=vrlg.MCONTR_BUF3_RD_ADDR + (page << 8)
elif chn==4: start_addr=self.MCONTR_BUF4_RD_ADDR + (page << 8) elif chn==4: start_addr=vrlg.MCONTR_BUF4_RD_ADDR + (page << 8)
else: else:
print("**** ERROR: Invalid channel for read buffer = %d"%chn) print("**** ERROR: Invalid channel for read buffer = %d"%chn)
start_addr = self.MCONTR_BUF0_RD_ADDR+ (page << 8) start_addr = vrlg.MCONTR_BUF0_RD_ADDR+ (page << 8)
result=self.read_block_buf (start_addr, num_read, show_rslt) result=self.read_block_buf (start_addr, num_read, show_rslt)
return result return result
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...@@ -31,7 +31,6 @@ __status__ = "Development" ...@@ -31,7 +31,6 @@ __status__ = "Development"
import mmap import mmap
#import sys #import sys
import struct import struct
class X393Mem(object): class X393Mem(object):
''' '''
classdocs classdocs
......
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...@@ -29,12 +29,15 @@ __maintainer__ = "Andrey Filippov" ...@@ -29,12 +29,15 @@ __maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com" __email__ = "andrey@elphel.com"
__status__ = "Development" __status__ = "Development"
from import_verilog_parameters import VerilogParameters import os
#from import_verilog_parameters import VerilogParameters
from x393_mem import X393Mem from x393_mem import X393Mem
#from verilog_utils import hx,concat, bits #from verilog_utils import hx,concat, bits
#from verilog_utils import hx #from verilog_utils import hx
#from subprocess import call #from subprocess import call
from time import sleep from time import sleep
import vrlg # global parameters
DEFAULT_BITFILE="/usr/local/verilog/x393.bit" DEFAULT_BITFILE="/usr/local/verilog/x393.bit"
FPGA_RST_CTRL= 0xf8000240 FPGA_RST_CTRL= 0xf8000240
FPGA0_THR_CTRL=0xf8000178 FPGA0_THR_CTRL=0xf8000178
...@@ -46,13 +49,15 @@ class X393Utils(object): ...@@ -46,13 +49,15 @@ class X393Utils(object):
# vpars=None # vpars=None
x393_mem=None x393_mem=None
enabled_channels=0 # currently enable channels enabled_channels=0 # currently enable channels
saveFileName=None
# verbose=1 # verbose=1
def __init__(self, debug_mode=1,dry_mode=True): def __init__(self, debug_mode=1,dry_mode=True,saveFileName=None):
self.DEBUG_MODE=debug_mode self.DEBUG_MODE=debug_mode
self.DRY_MODE=dry_mode self.DRY_MODE=dry_mode
if saveFileName:
self.saveFileName=saveFileName.strip()
self.x393_mem=X393Mem(debug_mode,dry_mode) self.x393_mem=X393Mem(debug_mode,dry_mode)
self.__dict__.update(VerilogParameters.__dict__["_VerilogParameters__shared_state"]) # Add verilog parameters to the class namespace # self.__dict__.update(VerilogParameters.__dict__["_VerilogParameters__shared_state"]) # Add verilog parameters to the class namespace
def reset_get(self): def reset_get(self):
""" """
Get current reset state Get current reset state
...@@ -70,7 +75,7 @@ class X393Utils(object): ...@@ -70,7 +75,7 @@ class X393Utils(object):
data can also be a list/tuple of integers, then it will be applied data can also be a list/tuple of integers, then it will be applied
in sequence (0,0xe) will turn reset on, then off in sequence (0,0xe) will turn reset on, then off
""" """
if isinstance(data,int): if isinstance(data, (int,long)):
self.x393_mem.write_mem(FPGA_RST_CTRL,data) self.x393_mem.write_mem(FPGA_RST_CTRL,data)
else: else:
for d in data: for d in data:
...@@ -173,3 +178,86 @@ class X393Utils(object): ...@@ -173,3 +178,86 @@ class X393Utils(object):
print() print()
return d return d
def getParTmpl(self):
return ({"name":"DLY_LANE0_ODELAY", "width": 80, "decl_width":""}, # decl_width can be "[7:0]", "integer", etc
{"name":"DLY_LANE0_IDELAY", "width": 72, "decl_width":""},
{"name":"DLY_LANE1_ODELAY", "width": 80, "decl_width":""},
{"name":"DLY_LANE1_IDELAY", "width": 72, "decl_width":""},
{"name":"DLY_CMDA", "width":256, "decl_width":""},
{"name":"DLY_PHASE", "width": 8, "decl_width":""})
def localparams(self,
quiet=False):
"""
Generate verilog include file with localparam definitions for the DDR3 timing parameters
Returns definition as a string
"""
nameLen=0
declWidth=0
for p in self.getParTmpl(): #parTmpl:
nameLen=max(nameLen,len(p['name']))
declWidth=max(declWidth,len(p['decl_width']))
txt=""
for p in self.getParTmpl(): # parTmpl:
numDigits = (p["width"]+3)/4
frmt="localparam %%%ds %%%ds %3d'h%%0%dx;\n"%(declWidth,nameLen+2,p["width"],numDigits)
txt+=frmt%(p['decl_width'],p['name']+" =",vrlg.__dict__[p['name']])
if not quiet:
print (txt)
return txt
def save_defaults(self,
allPars=False):
"""
Save current parameter values to defaults (as read at start up)
<allPars> use all parameters, if false - only for the ones used in
'save' file
"""
# global parTmpl
if allPars:
vrlg.save_default()
else:
for par in self.getParTmpl(): # parTmpl:
vrlg.save_default(par['name'])
def restore_defaults(self,
allPars=False):
"""
Restore parameter values from defaults (as read at start up)
<allPars> use all parameters, if false - only for the ones used in
'save' file
"""
global parTmpl
if allPars:
vrlg.restore_default()
else:
for par in parTmpl:
vrlg.restore_default(par['name'])
def save(self,
fileName=None):
"""
Write Verilog include file with localparam definitions for the DDR3 timing parameters
Also copies the same parameter values to defaults
<fileName> - optional path to write, pre-defined name if not specified
"""
header= """/* This is a generated file with the current DDR3 memory timing parameters */
"""
self.save_defaults(False) # copy current parameters to defaults
if not fileName:
fileName=self.saveFileName
txt=self.localparams(True) #quiet
if fileName:
try:
with open(fileName, "w") as text_file:
text_file.write(header)
text_file.write(txt)
print ("Verilog parameters are written to %s"%(os.path.abspath(fileName)))
except:
print ("Failed to write to %s"%(os.path.abspath(fileName)))
else:
print(txt)
...@@ -59,6 +59,7 @@ module x393_testbench01 #( ...@@ -59,6 +59,7 @@ module x393_testbench01 #(
`endif `endif
`define DEBUG_WR_SINGLE 1 `define DEBUG_WR_SINGLE 1
`define DEBUG_RD_DATA 1 `define DEBUG_RD_DATA 1
`include "includes/x393_cur_params_sim.vh" // parameters that may need adjustment, should be before x393_localparams.vh
`include "includes/x393_localparams.vh" // SuppressThisWarning VEditor - not used `include "includes/x393_localparams.vh" // SuppressThisWarning VEditor - not used
// DDR3 signals // DDR3 signals
wire SDRST; wire SDRST;
...@@ -202,35 +203,6 @@ module x393_testbench01 #( ...@@ -202,35 +203,6 @@ module x393_testbench01 #(
// integer SCANLINE_CUR_Y; // integer SCANLINE_CUR_Y;
wire AXI_RD_EMPTY=NUM_WORDS_READ==NUM_WORDS_EXPECTED; //SuppressThisWarning VEditor : may be unused, just for simulation wire AXI_RD_EMPTY=NUM_WORDS_READ==NUM_WORDS_EXPECTED; //SuppressThisWarning VEditor : may be unused, just for simulation
localparam FRAME_START_ADDRESS= 'h1000; // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
localparam FRAME_FULL_WIDTH= 'h0c0; // Padded line length (8-row increment), in 8-bursts (16 bytes)
// localparam SCANLINE_WINDOW_WH= `h079000a2; // 2592*1936: low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
// localparam SCANLINE_WINDOW_WH= 'h0009000b; // 176*9: low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
localparam WINDOW_WIDTH= 'h000b; //'h005b; //'h000b; // 176: 13-bit window width (0->'h4000)
localparam WINDOW_HEIGHT= 'h000a; // 9: 16-bit window height (0->'h10000)
// localparam SCANLINE_X0Y0= 'h00050003; // X0=3*16=48, Y0=5: // low word - 13-bit window left, high word - 16-bit window top
localparam WINDOW_X0= 'h5c; //'h7f; // 'h005c; // 'h7c; // 'h0003; // X0=3*16=48 - 13-bit window left
localparam WINDOW_Y0= 'h0005; // Y0=5: 16-bit window top
// localparam SCANLINE_STARTXY= 'h0; // low word - 13-bit start X (relative to window), high word - 16-bit start y (normally 0)
localparam SCANLINE_STARTX= 'h0; // 13-bit start X (relative to window), high word (normally 0)
localparam SCANLINE_STARTY= 'h0; // 16-bit start y (normally 0)
localparam [1:0] SCANLINE_EXTRA_PAGES= 0; // 0..2 - number of pages in the buffer to keep/not write // SuppressThisWarning VEditor - not used
localparam TILED_STARTX= 'h0; // 13-bit start X (relative to window), high word (normally 0)
localparam TILED_STARTY= 'h0; // 16-bit start y (normally 0)
localparam [1:0] TILED_EXTRA_PAGES= 0; // 0..2 - number of pages in the buffer to keep/not write
localparam TILED_KEEP_OPEN= 1'b1; //1'b1; // 1'b0; // Do not close banks between reads (valid only for tiles <=8 rows, needed if less than 3? rows)
localparam TILE_WIDTH= 'h04; // 6-bit tile width (1..'h40)
localparam TILE_HEIGHT= 'h08; //'h05; // 'h04; //'h06; // 6-bit tile height (1..'h40) // 4 - violation
localparam TILE_VSTEP= 'h04; // 6-bit tile vertical step, with no overlap it is equal to TILE_HEIGHT (1..'h40)
localparam TEST01_START_FRAME= 1;
localparam TEST01_NEXT_PAGE= 2;
localparam TEST01_SUSPEND= 4; // SuppressThisWarning VEditor - not used
//NUM_XFER_BITS=6 //NUM_XFER_BITS=6
...@@ -246,7 +218,6 @@ module x393_testbench01 #( ...@@ -246,7 +218,6 @@ module x393_testbench01 #(
// integer ii; // integer ii;
// integer SCANLINE_XFER_SIZE; // integer SCANLINE_XFER_SIZE;
localparam TEST_INITIAL_BURST= 4; // 3;
always #(CLKIN_PERIOD/2) CLK = ~CLK; always #(CLKIN_PERIOD/2) CLK = ~CLK;
initial begin initial begin
`ifdef IVERILOG `ifdef IVERILOG
......
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