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Commit 16513305 authored by Andrey Filippov's avatar Andrey Filippov
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Implemented clock management, entered pads physical constraints

parent cd95869f
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Showing with 819 additions and 31 deletions
includes/x393_parameters.vh
View file @ 16513305
......@@ -271,10 +271,6 @@
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f, // status/readback register for channel 4
// axi_hp_clk_i parameters
parameter CLKFBOUT_MULT_AXIHP = 18,
parameter CLKFBOUT_DIV_AXIHP = 6,
// membridge module parameters
parameter MEMBRIDGE_ADDR= 'h200,
......@@ -387,7 +383,7 @@
//sensor_i2c_io other parameters
parameter integer SENSI2C_DRIVE= 12,
parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
parameter SENSI2C_IOSTANDARD = "DEFAULT",
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_SLEW = "SLOW",
//sensor_fifo parameters
......@@ -419,7 +415,7 @@
parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "DEFAULT",
parameter PXD_IOSTANDARD = "LVCMOS33",
parameter PXD_SLEW = "SLOW",
parameter real SENS_REFCLK_FREQUENCY = 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
......@@ -536,7 +532,7 @@
parameter GPIO_STATUS_REG_ADDR = 'h30, // address where status can be read out (10 GPIO inputs)
parameter GPIO_IBUF_LOW_PWR = "TRUE",
parameter GPIO_IOSTANDARD = "DEFAULT", // power is 1.5V
parameter GPIO_IOSTANDARD = "LVCMOS15", // power is 1.5V
parameter GPIO_SLEW = "SLOW",
parameter GPIO_SET_PINS = 0, // Set GPIO output state, give control for some bits to other modules
......@@ -630,7 +626,67 @@
parameter MULT_SAXI_CNTRL_MASK = 'h7fe, // mode and status - 2 locations
parameter MULT_SAXI_AWCACHE = 4'h3, //..7 cache mode (4 bits, default 4'h3)
parameter MULT_SAXI_ADV_WR = 4, // number of clock cycles before end of write to genearte adv_wr_done
parameter MULT_SAXI_ADV_RD = 3 // number of clock cycles before end of write to genearte adv_wr_done
parameter MULT_SAXI_ADV_RD = 3, // number of clock cycles before end of write to genearte adv_wr_done
// Clock management (input, generation, buffering)
parameter CLK_ADDR = 'h728, // ..'h729
parameter CLK_MASK = 'h7fe, //
parameter CLK_STATUS_REG_ADDR = 'h3a, //
parameter CLK_CNTRL = 0,
parameter CLK_STATUS = 1,
parameter CLKIN_PERIOD_AXIHP = 20, //ns >1.25, 600<Fvco<1200
parameter DIVCLK_DIVIDE_AXIHP = 1,
parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKOUT_DIV_AXIHP = 6, // To get 150MHz for the reference clock
parameter BUF_CLK1X_AXIHP = "BUFG", // "BUFG", "BUFH", "BUFR", "NONE"
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
parameter CLKOUT_DIV_PCLK = 10, // 96MHz
parameter CLKOUT_DIV_PCLK2X = 5, // 192 MHz
parameter PHASE_CLK2X_PCLK = 0.000,
parameter BUF_CLK1X_PCLK = "BUFG",
parameter BUF_CLK1X_PCLK2X = "BUFG",
parameter CLKIN_PERIOD_XCLK = 20, // 24MHz
parameter DIVCLK_DIVIDE_XCLK = 1,
parameter CLKFBOUT_MULT_XCLK = 50, // 1000 MHz
parameter CLKOUT_DIV_XCLK = 10, // 100 MHz
parameter CLKOUT_DIV_XCLK2X = 5, // 200 MHz
parameter PHASE_CLK2X_XCLK = 0.000,
parameter BUF_CLK1X_XCLK = "BUFG",
parameter BUF_CLK1X_XCLK2X = "BUFG",
parameter CLKIN_PERIOD_SYNC = 20, // 24MHz
parameter DIVCLK_DIVIDE_SYNC = 1,
parameter CLKFBOUT_MULT_SYNC = 50, // 1000 MHz
parameter CLKOUT_DIV_SYNC = 10, // 100 MHz
parameter BUF_CLK1X_SYNC = "BUFG",
parameter MEMCLK_CAPACITANCE = "DONT_CARE",
parameter MEMCLK_IBUF_DELAY_VALUE = "0",
parameter MEMCLK_IBUF_LOW_PWR = "TRUE",
parameter MEMCLK_IFD_DELAY_VALUE = "AUTO",
parameter MEMCLK_IOSTANDARD = "SSTL15",
parameter FFCLK0_CAPACITANCE = "DONT_CARE",
parameter FFCLK0_DIFF_TERM = "FALSE",
parameter FFCLK0_DQS_BIAS = "FALSE",
parameter FFCLK0_IBUF_DELAY_VALUE = "0",
parameter FFCLK0_IBUF_LOW_PWR = "TRUE",
parameter FFCLK0_IFD_DELAY_VALUE = "AUTO",
parameter FFCLK0_IOSTANDARD = "RSDS_25",
parameter FFCLK1_CAPACITANCE = "DONT_CARE",
parameter FFCLK1_DIFF_TERM = "FALSE",
parameter FFCLK1_DQS_BIAS = "FALSE",
parameter FFCLK1_IBUF_DELAY_VALUE = "0",
parameter FFCLK1_IBUF_LOW_PWR = "TRUE",
parameter FFCLK1_IFD_DELAY_VALUE = "AUTO",
parameter FFCLK1_IOSTANDARD = "RSDS_25"
......
timing/rtc393.v
View file @ 16513305
......@@ -23,9 +23,9 @@
`timescale 1ns/1ps
module rtc393 #(
parameter RTC_ADDR = 'h170, //TODO: assign valid address
parameter RTC_STATUS_REG_ADDR = 7, // address where status can be read out (currently just sequence # and alternating bit)
parameter RTC_SEC_USEC_ADDR = 8, // address where seconds of the snapshot can be read (microseconds - next adderss)
parameter RTC_ADDR = 'h704, //..'h707
parameter RTC_STATUS_REG_ADDR = 'h31, // address where status can be read out (currently just sequence # and alternating bit)
parameter RTC_SEC_USEC_ADDR = 'h32, //'h33 address where seconds of the snapshot can be read (microseconds - next adderss)
parameter RTC_MASK = 'h7fc,
parameter RTC_MHZ = 25, // RTC input clock in MHz (should be interger number)
......
util_modules/clocks393.v 0 → 100644
View file @ 16513305
This diff is collapsed.
util_modules/dual_clock_source.v 0 → 100644
View file @ 16513305
/*******************************************************************************
* Module: dual_clock_source
* Date:2015-07-17
* Author: Andrey Filippov
* Description: generate clk and clk2x with configurable output buffers
*
* Copyright (c) 2015 Elphel, Inc .
* dual_clock_source.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dual_clock_source.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module dual_clock_source #(
parameter CLKIN_PERIOD = 20, //ns >1.25, 600<Fvco<1200
// Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter CLKFBOUT_MULT = 20, // integer 2 to 64 . Together with CLKOUT#_DIVIDE and DIVCLK_DIVIDE
parameter CLKOUT_DIV_CLK1X = 10, //
parameter CLKOUT_DIV_CLK2X = 5, //
parameter PHASE_CLK2X = 0.000, // degrees, relative to clk1x (3 significant digits, -360.000...+360.000)
parameter BUF_CLK1X = "BUFG", // "BUFG", "BUFH", "BUFR", "NONE"
parameter BUF_CLK2X = "BUFG" // "BUFG", "BUFH", "BUFR", "NONE"
)(
input rst,
input clk_in,
input pwrdwn,
output clk1x,
output clk2x,
output locked
);
wire clkfb, clk1x_pre, clk2x_pre;
generate
if (BUF_CLK1X == "BUFG") BUFG clk1x_i (.O(clk1x), .I(clk1x_pre));
else if (BUF_CLK1X == "BUFH") BUFH clk1x_i (.O(clk1x), .I(clk1x_pre));
else if (BUF_CLK1X == "BUFR") BUFR clk1x_i (.O(clk1x), .I(clk1x_pre), .CE(1'b1), .CLR(rst));
else assign clk1x = clk1x_pre;
endgenerate
generate
if (BUF_CLK2X == "BUFG") BUFG clk2x_i (.O(clk2x), .I(clk2x_pre));
else if (BUF_CLK2X == "BUFH") BUFH clk2x_i (.O(clk2x), .I(clk2x_pre));
else if (BUF_CLK2X == "BUFR") BUFR clk2x_i (.O(clk2x), .I(clk2x_pre), .CE(1'b1), .CLR(rst));
else assign clk2x = clk2x_pre;
endgenerate
pll_base #(
.CLKIN_PERIOD (CLKIN_PERIOD), // 20
.BANDWIDTH ("OPTIMIZED"),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_MULT (CLKFBOUT_MULT), // 2..64, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
.CLKOUT1_PHASE (PHASE_CLK2X),
.CLKOUT0_DIVIDE (CLKOUT_DIV_CLK1X),
.CLKOUT1_DIVIDE (CLKOUT_DIV_CLK2X),
.REF_JITTER1 (0.010),
.STARTUP_WAIT("FALSE")
) pll_base_i (
.clkin(clk_in), // input
.clkfbin(clkfb), // input
// .rst(rst), // input
.rst(rst), // input
.pwrdwn(pwrdwn), // input
.clkout0(clk1x_pre), // output
.clkout1(clk2x_pre), // output
.clkout2(), // output
.clkout3(), // output
.clkout4(), // output
.clkout5(), // output
.clkfbout(clkfb), // output
.locked(locked) // output
);
endmodule
wrap/ibuf_ibufg.v 0 → 100644
View file @ 16513305
/*******************************************************************************
* Module: ibuf_ibufg
* Date:2015-07-17
* Author: Andrey Filippov
* Description: Wrapper for IBUFG primitive
*
* Copyright (c) 2015 Elphel, Inc .
* ibuf_ibufg.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ibuf_ibufg.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
/*Quote from Xilinx "7 Series FPGA SelectIO Primitives":
The IBUF and IBUFG primitives are the same. IBUFGs are used when an input buffer is
used as a clock input. In the Xilinx software tools, an IBUFG is automatically placed at
clock input sites.
*/
module ibuf_ibufg #(
parameter CAPACITANCE = "DONT_CARE",
parameter IBUF_DELAY_VALUE = "0",
parameter IBUF_LOW_PWR = "TRUE",
parameter IFD_DELAY_VALUE = "AUTO",
parameter IOSTANDARD = "DEFAULT"
)(
output O,
input I
);
IBUF #(
.CAPACITANCE (CAPACITANCE),
.IBUF_DELAY_VALUE (IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.IFD_DELAY_VALUE (IFD_DELAY_VALUE),
.IOSTANDARD (IOSTANDARD)
) IBUF_i (
.O (O), // output
.I (I) // input
);
endmodule
wrap/ibufds_ibufgds.v 0 → 100644
View file @ 16513305
/*******************************************************************************
* Module: ibufds_ibufgds
* Date:2015-07-17
* Author: Andrey Filippov
* Description: Wrapper for IBUFDS primitive
*
* Copyright (c) 2015 Elphel, Inc .
* ibufds_ibufgds.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ibufds_ibufgds.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
/*Quote from Xilinx "7 Series FPGA SelectIO Primitives":
The IBUFDS and IBUFGDS primitives are the same, IBUFGDS is used when an differential
input buffer is used as a clock input.
*/
module ibufds_ibufgds #(
parameter CAPACITANCE = "DONT_CARE",
parameter DIFF_TERM = "FALSE",
parameter DQS_BIAS = "FALSE",
parameter IBUF_DELAY_VALUE = "0",
parameter IBUF_LOW_PWR = "TRUE",
parameter IFD_DELAY_VALUE = "AUTO",
parameter IOSTANDARD = "DEFAULT"
)(
output O,
input I,
input IB
);
IBUFDS #(
.CAPACITANCE (CAPACITANCE),
.DIFF_TERM (DIFF_TERM),
.DQS_BIAS (DQS_BIAS),
.IBUF_DELAY_VALUE (IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.IFD_DELAY_VALUE (IFD_DELAY_VALUE),
.IOSTANDARD (IOSTANDARD)
) IBUFDS_i (
.O (O), // output
.I (I), // input
.IB (IB) // input
);
endmodule
endmodule
wrap/pll_base.v
View file @ 16513305
......@@ -44,7 +44,7 @@ module pll_base#(
parameter CLKOUT4_DIVIDE = 1,
parameter CLKOUT5_DIVIDE = 1,
parameter DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
parameter REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter STARTUP_WAIT = "FALSE" // Delays "DONE" signal until MMCM is locked
)
(
......
x393.v
View file @ 16513305
......@@ -82,8 +82,12 @@ module x393 #(
output SDDMU, // UDM I/O pad (actually only output)
inout DQSU, // UDQS I/O pad
inout NDQSU,
output DUMMY_TO_KEEP // to keep PS7 signals from "optimization"
,input MEMCLK
// Clock inputs
input memclk, // M5
input ffclk0p, // Y12
input ffclk0n, // Y11
input ffclk1p, // W14
input ffclk1n // W13
);
// localparam ADDRESS_NUMBER=15;
......@@ -207,10 +211,6 @@ module x393 #(
assign logger_clk = camsync_clk;
wire time_ref; // RTC reference: integer number of microseconds, less than mclk/2. Not a global clock
// temporary:
reg [2:0] time_ref_r;
always @ (posedge mclk or posedge axi_rst) if (axi_rst) time_ref_r <= 0; else time_ref_r <= time_ref_r + 1;
assign time_ref = time_ref_r[2];
wire [11:0] tmp_debug;
......@@ -293,6 +293,10 @@ module x393 #(
wire status_saxi1wr_rq; // Other status request
wire status_saxi1wr_start; // S uppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_clocks_ad; // saxi1 - logger data Other status byte-wide address/data
wire status_clocks_rq; // Other status request
wire status_clocks_start; // S uppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
// Insert register layer if needed
reg [7:0] cmd_mcontr_ad;
reg cmd_mcontr_stb;
......@@ -324,6 +328,9 @@ module x393 #(
reg [7:0] cmd_saxi1wr_ad;
reg cmd_saxi1wr_stb;
reg [7:0] cmd_clocks_ad;
reg cmd_clocks_stb;
// membridge
wire frame_start_chn1; // input
wire next_page_chn1; // input
......@@ -369,7 +376,7 @@ module x393 #(
reg axi_rst_pre=1'b1;
wire comb_rst; //=~frst[0] | frst[1];
//MEMCLK
wire [63:0] gpio_in;
// signals for sensor393 (in/outs as sseen for the sensor393)
......@@ -509,6 +516,8 @@ module x393 #(
cmd_saxi1wr_ad <= cmd_root_ad;
cmd_saxi1wr_stb <= cmd_root_stb;
cmd_clocks_ad <= cmd_root_ad;
cmd_clocks_stb <= cmd_root_stb;
end
// For now - connect status_test01 to status_other, if needed - increase number of multiplexer inputs)
......@@ -548,9 +557,6 @@ module x393 #(
else axi_rst_pre <= 1'b0;
end
//BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
//BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
`ifdef DEBUG_FIFO
wire waddr_under, wdata_under, wresp_under;
......@@ -583,6 +589,7 @@ module x393 #(
`endif
BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
/*
BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
axi_hp_clk #(
.CLKIN_PERIOD(CLKIN_PERIOD),
......@@ -595,7 +602,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.locked_axihp () // output // not controlled?
);
*/
// channel test module
mcntrl393_test01 #(
.MCNTRL_TEST01_ADDR (MCNTRL_TEST01_ADDR),
......@@ -874,9 +881,9 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.rq_in9 (status_saxi1wr_rq), // input
.start_in9 (status_saxi1wr_start), // output
.db_in10 (8'b0), // input[7:0]
.rq_in10 (1'b0), // input
.start_in10(), // output
.db_in10 (status_clocks_ad), // input[7:0]
.rq_in10 (status_clocks_rq), // input
.start_in10(status_clocks_start), // output
.db_in11 (8'b0), // input[7:0]
.rq_in11 (1'b0), // input
......@@ -1994,6 +2001,80 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.saxi_bresp (saxi1_bresp) // input[1:0]
);
clocks393 #(
.CLK_ADDR (CLK_ADDR),
.CLK_MASK (CLK_MASK),
.CLK_STATUS_REG_ADDR (CLK_STATUS_REG_ADDR),
.CLK_CNTRL (CLK_CNTRL),
.CLK_STATUS (CLK_STATUS),
.CLKIN_PERIOD_AXIHP (CLKIN_PERIOD_AXIHP),
.DIVCLK_DIVIDE_AXIHP (DIVCLK_DIVIDE_AXIHP),
.CLKFBOUT_MULT_AXIHP (CLKFBOUT_MULT_AXIHP),
.CLKOUT_DIV_AXIHP (CLKOUT_DIV_AXIHP),
.BUF_CLK1X_AXIHP (BUF_CLK1X_AXIHP),
.CLKIN_PERIOD_PCLK (CLKIN_PERIOD_PCLK),
.DIVCLK_DIVIDE_PCLK (DIVCLK_DIVIDE_PCLK),
.CLKFBOUT_MULT_PCLK (CLKFBOUT_MULT_PCLK),
.CLKOUT_DIV_PCLK (CLKOUT_DIV_PCLK),
.CLKOUT_DIV_PCLK2X (CLKOUT_DIV_PCLK2X),
.PHASE_CLK2X_PCLK (PHASE_CLK2X_PCLK),
.BUF_CLK1X_PCLK (BUF_CLK1X_PCLK),
.BUF_CLK1X_PCLK2X (BUF_CLK1X_PCLK2X),
.CLKIN_PERIOD_XCLK (CLKIN_PERIOD_XCLK),
.DIVCLK_DIVIDE_XCLK (DIVCLK_DIVIDE_XCLK),
.CLKFBOUT_MULT_XCLK (CLKFBOUT_MULT_XCLK),
.CLKOUT_DIV_XCLK (CLKOUT_DIV_XCLK),
.CLKOUT_DIV_XCLK2X (CLKOUT_DIV_XCLK2X),
.PHASE_CLK2X_XCLK (PHASE_CLK2X_XCLK),
.BUF_CLK1X_XCLK (BUF_CLK1X_XCLK),
.BUF_CLK1X_XCLK2X (BUF_CLK1X_XCLK2X),
.CLKIN_PERIOD_SYNC (CLKIN_PERIOD_SYNC),
.DIVCLK_DIVIDE_SYNC (DIVCLK_DIVIDE_SYNC),
.CLKFBOUT_MULT_SYNC (CLKFBOUT_MULT_SYNC),
.CLKOUT_DIV_SYNC (CLKOUT_DIV_SYNC),
.BUF_CLK1X_SYNC (BUF_CLK1X_SYNC),
.MEMCLK_CAPACITANCE (MEMCLK_CAPACITANCE),
.MEMCLK_IBUF_DELAY_VALUE (MEMCLK_IBUF_DELAY_VALUE),
.MEMCLK_IBUF_LOW_PWR (MEMCLK_IBUF_LOW_PWR),
.MEMCLK_IFD_DELAY_VALUE (MEMCLK_IFD_DELAY_VALUE),
.MEMCLK_IOSTANDARD (MEMCLK_IOSTANDARD),
.FFCLK0_CAPACITANCE (FFCLK0_CAPACITANCE),
.FFCLK0_DIFF_TERM (FFCLK0_DIFF_TERM),
.FFCLK0_DQS_BIAS (FFCLK0_DQS_BIAS),
.FFCLK0_IBUF_DELAY_VALUE (FFCLK0_IBUF_DELAY_VALUE),
.FFCLK0_IBUF_LOW_PWR (FFCLK0_IBUF_LOW_PWR),
.FFCLK0_IFD_DELAY_VALUE (FFCLK0_IFD_DELAY_VALUE),
.FFCLK0_IOSTANDARD (FFCLK0_IOSTANDARD),
.FFCLK1_CAPACITANCE (FFCLK1_CAPACITANCE),
.FFCLK1_DIFF_TERM (FFCLK1_DIFF_TERM),
.FFCLK1_DQS_BIAS (FFCLK1_DQS_BIAS),
.FFCLK1_IBUF_DELAY_VALUE (FFCLK1_IBUF_DELAY_VALUE),
.FFCLK1_IBUF_LOW_PWR (FFCLK1_IBUF_LOW_PWR),
.FFCLK1_IFD_DELAY_VALUE (FFCLK1_IFD_DELAY_VALUE),
.FFCLK1_IOSTANDARD (FFCLK1_IOSTANDARD)
) clocks393_i (
.rst (axi_rst), // input
.mclk (mclk), // input
.cmd_ad (cmd_clocks_ad), // input[7:0]
.cmd_stb (cmd_clocks_stb), // input
.status_ad (status_clocks_ad), // output[7:0]
.status_rq (status_clocks_rq), // output
.status_start (status_clocks_start), // input
.fclk (fclk), // input[3:0]
.memclk_pad (memclk), // input
.ffclk0p_pad (ffclk0p), // input
.ffclk0n_pad (ffclk0n), // input
.ffclk1p_pad (ffclk1p), // input
.ffclk1n_pad (ffclk1n), // input
.aclk (axi_aclk), // output
.hclk (hclk), // output
.pclk (pclk), // output
.pclk2x (pclk2x), // output
.xclk (xclk), // output
.xclk2x (xclk2x), // output
.sync_clk (camsync_clk), // output
.time_ref (time_ref) // output
);
axibram_write #(
.ADDRESS_BITS(AXI_WR_ADDR_BITS)
......@@ -2076,7 +2157,6 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.bram_regen (axird_regen), // output
.bram_rdata (axird_rdata ) // input[31:0] == axi_rdata[31:0], so SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #axibram_read_i:bram_rdata[31:0] to constant 0
);
assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0];
PS7 ps7_i (
// EMIO interface
......
x393.xdc
View file @ 16513305
......@@ -208,10 +208,188 @@ set_property IOSTANDARD SSTL15 [get_ports {DUMMY_TO_KEEP}]
set_property PACKAGE_PIN E3 [get_ports {DUMMY_TO_KEEP}]
#not yet used, just for debugging
# input MEMCLK, // to keep PS7 signals from "optimization"
set_property IOSTANDARD SSTL15 [get_ports {MEMCLK}]
set_property PACKAGE_PIN M5 [get_ports {MEMCLK}]
# input memclk,
#set_property IOSTANDARD SSTL15 [get_ports {memclk}]
set_property PACKAGE_PIN M5 [get_ports {memclk}]
# ================= Sensor port 0 =================
# inout [7:0] sns1_dp,
# inout [7:0] sns1_dn,
set_property PACKAGE_PIN T10 [get_ports {sns1_dp[0]}]
set_property PACKAGE_PIN T9 [get_ports {sns1_dn[0]}]
set_property PACKAGE_PIN U10 [get_ports {sns1_dp[1]}]
set_property PACKAGE_PIN V10 [get_ports {sns1_dn[1]}]
set_property PACKAGE_PIN V8 [get_ports {sns1_dp[2]}]
set_property PACKAGE_PIN W8 [get_ports {sns1_dn[2]}]
set_property PACKAGE_PIN W9 [get_ports {sns1_dp[3]}]
set_property PACKAGE_PIN Y8 [get_ports {sns1_dn[3]}]
set_property PACKAGE_PIN AB9 [get_ports {sns1_dp[4]}]
set_property PACKAGE_PIN AB8 [get_ports {sns1_dn[4]}]
set_property PACKAGE_PIN AB13 [get_ports {sns1_dp[5]}]
set_property PACKAGE_PIN AB12 [get_ports {sns1_dn[5]}]
set_property PACKAGE_PIN AA12 [get_ports {sns1_dp[6]}]
set_property PACKAGE_PIN AA11 [get_ports {sns1_dn[6]}]
set_property PACKAGE_PIN W11 [get_ports {sns1_dp[7]}]
set_property PACKAGE_PIN W10 [get_ports {sns1_dn[7]}]
# inout sns1_clkp,
# inout sns1_clkn,
set_property PACKAGE_PIN AA10 [get_ports {sns1_clkp}]
set_property PACKAGE_PIN AB10 [get_ports {sns1_clkn}]
# inout sns1_scl,
# inout sns1_sda,
set_property PACKAGE_PIN Y9 [get_ports {sns1_scl}]
set_property PACKAGE_PIN AA9 [get_ports {sns1_sda}]
# inout sns1_ctl,
# inout sns1_pg,
set_property PACKAGE_PIN U9 [get_ports {sns1_ctl}]
set_property PACKAGE_PIN U8 [get_ports {sns1_pg}]
# ================= Sensor port 1 =================
# inout [7:0] sns2_dp,
# inout [7:0] sns2_dn,
set_property PACKAGE_PIN U15 [get_ports {sns2_dp[0]}]
set_property PACKAGE_PIN U14 [get_ports {sns2_dn[0]}]
set_property PACKAGE_PIN V15 [get_ports {sns2_dp[1]}]
set_property PACKAGE_PIN W15 [get_ports {sns2_dn[1]}]
set_property PACKAGE_PIN U13 [get_ports {sns2_dp[2]}]
set_property PACKAGE_PIN V13 [get_ports {sns2_dn[2]}]
set_property PACKAGE_PIN V12 [get_ports {sns2_dp[3]}]
set_property PACKAGE_PIN V11 [get_ports {sns2_dn[3]}]
set_property PACKAGE_PIN AA17 [get_ports {sns2_dp[4]}]
set_property PACKAGE_PIN AB17 [get_ports {sns2_dn[4]}]
set_property PACKAGE_PIN AA15 [get_ports {sns2_dp[5]}]
set_property PACKAGE_PIN AB15 [get_ports {sns2_dn[5]}]
set_property PACKAGE_PIN AA14 [get_ports {sns2_dp[6]}]
set_property PACKAGE_PIN AB14 [get_ports {sns2_dn[6]}]
set_property PACKAGE_PIN Y14 [get_ports {sns2_dp[7]}]
set_property PACKAGE_PIN Y13 [get_ports {sns2_dn[7]}]
# inout sns2_clkp,
# inout sns2_clkn,
set_property PACKAGE_PIN Y16 [get_ports {sns2_clkp}]
set_property PACKAGE_PIN AA16 [get_ports {sns2_clkn}]
# inout sns2_scl,
# inout sns2_sda,
set_property PACKAGE_PIN T12 [get_ports {sns2_scl}]
set_property PACKAGE_PIN U12 [get_ports {sns2_sda}]
# inout sns2_ctl,
# inout sns2_pg,
set_property PACKAGE_PIN V16 [get_ports {sns2_ctl}]
set_property PACKAGE_PIN W16 [get_ports {sns2_pg}]
# ================= Sensor port 2 =================
# inout [7:0] sns3_dp,
# inout [7:0] sns3_dn,
set_property PACKAGE_PIN AA22 [get_ports {sns3_dp[0]}]
set_property PACKAGE_PIN AB22 [get_ports {sns3_dn[0]}]
set_property PACKAGE_PIN W21 [get_ports {sns3_dp[1]}]
set_property PACKAGE_PIN Y22 [get_ports {sns3_dn[1]}]
set_property PACKAGE_PIN V21 [get_ports {sns3_dp[2]}]
set_property PACKAGE_PIN V22 [get_ports {sns3_dn[2]}]
set_property PACKAGE_PIN W19 [get_ports {sns3_dp[3]}]
set_property PACKAGE_PIN W20 [get_ports {sns3_dn[3]}]
set_property PACKAGE_PIN N21 [get_ports {sns3_dp[4]}]
set_property PACKAGE_PIN N22 [get_ports {sns3_dn[4]}]
set_property PACKAGE_PIN R22 [get_ports {sns3_dp[5]}]
set_property PACKAGE_PIN T22 [get_ports {sns3_dn[5]}]
set_property PACKAGE_PIN P21 [get_ports {sns3_dp[6]}]
set_property PACKAGE_PIN R21 [get_ports {sns3_dn[6]}]
set_property PACKAGE_PIN T20 [get_ports {sns3_dp[7]}]
set_property PACKAGE_PIN U20 [get_ports {sns3_dn[7]}]
# inout sns3_clkp,
# inout sns3_clkn,
set_property PACKAGE_PIN T21 [get_ports {sns3_clkp}]
set_property PACKAGE_PIN U22 [get_ports {sns3_clkn}]
# inout sns3_scl,
# inout sns3_sda,
set_property PACKAGE_PIN Y21 [get_ports {sns3_scl}]
set_property PACKAGE_PIN AA21 [get_ports {sns3_sda}]
# inout sns3_ctl,
# inout sns3_pg,
set_property PACKAGE_PIN AA20 [get_ports {sns3_ctl}]
set_property PACKAGE_PIN AB20 [get_ports {sns3_pg}]
# ================= Sensor port 3 =================
# inout [7:0] sns4_dp,
# inout [7:0] sns4_dn,
set_property PACKAGE_PIN V17 [get_ports {sns4_dp[0]}]
set_property PACKAGE_PIN W18 [get_ports {sns4_dn[0]}]
set_property PACKAGE_PIN Y19 [get_ports {sns4_dp[1]}]
set_property PACKAGE_PIN AA19 [get_ports {sns4_dn[1]}]
set_property PACKAGE_PIN U19 [get_ports {sns4_dp[2]}]
set_property PACKAGE_PIN V20 [get_ports {sns4_dn[2]}]
set_property PACKAGE_PIN U18 [get_ports {sns4_dp[3]}]
set_property PACKAGE_PIN V18 [get_ports {sns4_dn[3]}]
set_property PACKAGE_PIN P18 [get_ports {sns4_dp[4]}]
set_property PACKAGE_PIN P19 [get_ports {sns4_dn[4]}]
set_property PACKAGE_PIN N17 [get_ports {sns4_dp[5]}]
set_property PACKAGE_PIN N18 [get_ports {sns4_dn[5]}]
set_property PACKAGE_PIN N20 [get_ports {sns4_dp[6]}]
set_property PACKAGE_PIN P20 [get_ports {sns4_dn[6]}]
set_property PACKAGE_PIN R17 [get_ports {sns4_dp[7]}]
set_property PACKAGE_PIN R18 [get_ports {sns4_dn[7]}]
# inout sns4_clkp,
# inout sns4_clkn,
set_property PACKAGE_PIN R16 [get_ports {sns4_clkp}]
set_property PACKAGE_PIN T16 [get_ports {sns4_clkn}]
# inout sns4_scl,
# inout sns4_sda,
set_property PACKAGE_PIN AB18 [get_ports {sns4_scl}]
set_property PACKAGE_PIN AB19 [get_ports {sns4_sda}]
# inout sns4_ctl,
# inout sns4_pg,
set_property PACKAGE_PIN Y17 [get_ports {sns4_ctl}]
set_property PACKAGE_PIN Y18 [get_ports {sns4_pg}]
# ======== GPIO pins ===============
# inout [GPIO_N-1:0] gpio_pins,
set_property PACKAGE_PIN B4 [get_ports {gpio_pins[0]}]
set_property PACKAGE_PIN A4 [get_ports {gpio_pins[1]}]
set_property PACKAGE_PIN A2 [get_ports {gpio_pins[2]}]
set_property PACKAGE_PIN A1 [get_ports {gpio_pins[3]}]
set_property PACKAGE_PIN C3 [get_ports {gpio_pins[4]}]
set_property PACKAGE_PIN D3 [get_ports {gpio_pins[5]}]
set_property PACKAGE_PIN D1 [get_ports {gpio_pins[6]}]
set_property PACKAGE_PIN C1 [get_ports {gpio_pins[7]}]
set_property PACKAGE_PIN C2 [get_ports {gpio_pins[8]}]
set_property PACKAGE_PIN B2 [get_ports {gpio_pins[9]}]
# =========Differential clock inputs ==========
# input ffclk0p, // Y12
# input ffclk0n, // Y11
# input ffclk1p, // W14
# input ffclk1n // W13
set_property PACKAGE_PIN Y12 [get_ports {ffclk0p}]
set_property PACKAGE_PIN Y11 [get_ports {ffclk0n}]
set_property PACKAGE_PIN W14 [get_ports {ffclk1p}]
set_property PACKAGE_PIN W13 [get_ports {ffclk1n}]
# Global constraints
......
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