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Commit 158be190 authored by Andrey Filippov's avatar Andrey Filippov
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working on event logger

parent d925932c
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.settings/com.elphel.vdt.cocotb.prefs
View file @ 158be190
...@@ -4,7 +4,7 @@ cocotb_@_CocotbExtraFiles=glbl.v<-@\#\#@-> ...@@ -4,7 +4,7 @@ cocotb_@_CocotbExtraFiles=glbl.v<-@\#\#@->
cocotb_@_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@-> cocotb_@_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
cocotb_@_CocotbMODULE=x393_cocotb_server<-@\#\#@-> cocotb_@_CocotbMODULE=x393_cocotb_server<-@\#\#@->
cocotb_@_CocotbTESTCASE=run_test<-@\#\#@-> cocotb_@_CocotbTESTCASE=run_test<-@\#\#@->
cocotb_@_GTKWaveSavFile=x393_cocotb_02.sav cocotb_@_GTKWaveSavFile=x393_cocotb_03.sav
cocotb_@_GrepFindErr=error|ERROR cocotb_@_GrepFindErr=error|ERROR
cocotb_@_GrepFindErrWarn=error|warning|ERROR|WARNING cocotb_@_GrepFindErrWarn=error|warning|ERROR|WARNING
cocotb_@_PatternInfo=.*[\\s.](\\w*\\.py)\:([0-9]+)\\s*\\S*\\s*\\S*\\s*(.*) cocotb_@_PatternInfo=.*[\\s.](\\w*\\.py)\:([0-9]+)\\s*\\S*\\s*\\S*\\s*(.*)
......
cocotb/x393_cocotb_03.sav
View file @ 158be190
This diff is collapsed.
cocotb/x393_dut.v
View file @ 158be190
...@@ -679,8 +679,6 @@ module x393_dut#( ...@@ -679,8 +679,6 @@ module x393_dut#(
wire [ 9:0] gpio_pins; // inout[9:0] ([8]-synco0,[7]-syncio0,[6]-synco1,[9]-syncio1) wire [ 9:0] gpio_pins; // inout[9:0] ([8]-synco0,[7]-syncio0,[6]-synco1,[9]-syncio1)
// Connect trigger outs to triggets in (#10 needed for Icarus) // Connect trigger outs to triggets in (#10 needed for Icarus)
assign #10 gpio_pins[7] = gpio_pins[8];
assign #10 gpio_pins[9] = gpio_pins[6];
// DDR3 signals // DDR3 signals
wire SDRST; wire SDRST;
...@@ -1713,6 +1711,220 @@ simul_axi_hp_wr #( ...@@ -1713,6 +1711,220 @@ simul_axi_hp_wr #(
//localparam line = `__LINE__; //localparam line = `__LINE__;
assign x393_i.ps7_i.FCLKCLK= {4{CLK}}; assign x393_i.ps7_i.FCLKCLK= {4{CLK}};
assign x393_i.ps7_i.FCLKRESETN= {RST,~RST,RST,~RST}; assign x393_i.ps7_i.FCLKRESETN= {RST,~RST,RST,~RST};
`define TEST_IMU
assign #10 gpio_pins[7] = gpio_pins[8];
`ifndef TEST_IMU
assign #10 gpio_pins[9] = gpio_pins[6];
`endif
`ifdef TEST_IMU
// localparam X313_WA_IOPINS_EN_IMU_OUT= 'hc0000000;
// localparam X313_WA_IOPINS_DIS_IMU_OUT='h80000000; //SuppressThisWarning Veditor UNUSED
// localparam X313_WA_IMU_CTRL= 'h7f;
// localparam X313_WA_IMU_DATA= 'h7e;
// localparam X313_RA_IMU_DATA= 'h7e; // read fifo word, advance pointer (32 reads w/o ready check)
// localparam X313_RA_IMU_STATUS= 'h7f; // LSB==ready
// localparam IMU_PERIOD= 'h800; // normal period
// localparam IMU_AUTO_PERIOD= 'hffff0000; // period defined by IMU ready
localparam IMU_BIT_DURATION= 'h3; // actual F(scl) will be F(xclk)/2/(IMU_BIT_DURATION+1)
localparam IMU_READY_PERIOD=100000; //100usec
localparam IMU_NREADY_DURATION=10000; //10usec
localparam IMU_GPS_BIT_PERIOD='h18; // 20; // serial communication duration of a bit (in system clocks)
// use start of trigger as a timestamp (in async mode to prevent timestamp jitter)
// parameter X313_WA_DCR1_EARLYTRIGEN='hc; //OBSOLETE!
// parameter X313_WA_DCR1_EARLYTRIGDIS='h8;
`endif
`ifdef TEST_IMU
//wire [11:0] EXT; // bidirectional
//reg TEST_CPU_WR_OK;
//reg TEST_CPU_RD_OK;
reg SERIAL_BIT = 1'b1;
reg GPS1SEC = 1'b0;
reg ODOMETER_PULSE= 1'b0;
integer SERIAL_DATA_FD; // @SuppressThisWarning VEditor
reg IMU_DATA_READY;
wire IMU_SCL=gpio_pins[0];
wire IMU_SDA=gpio_pins[1];
wire IMU_MOSI=gpio_pins[2];
wire IMU_MISO=gpio_pins[3]; // @SuppressThisWarning VEditor just for simulation
reg IMU_EN;
wire IMU_ACTIVE; // @SuppressThisWarning VEditor just for simulation
wire IMU_NMOSI=!IMU_MOSI;
wire [5:1] IMU_TAPS;
reg IMU_LATE_ACKN = 0;
reg IMU_SCLK = 1;
reg IMU_MOSI_REVA;
reg IMU_103695REVA = 1;
wire IMU_MOSI_OUT;
wire IMU_SCLK_OUT;
reg RS232_SENDING_BYTE; // @SuppressThisWarning VEditor just for simulation
reg RS232_SENDING_PAUSE; // @SuppressThisWarning VEditor just for simulation
`endif
`ifdef TEST_IMU
initial begin
SERIAL_DATA_FD=$fopen({`ROOTPATH,"/input_data/gps_data.dat"},"r");
#10000;
while (!$feof (SERIAL_DATA_FD)) begin
repeat (18*IMU_BIT_DURATION) begin wait (axi_hclk); wait (~axi_hclk); end // was 20
send_serial_line;
send_serial_bit('h0a);
send_serial_pause; // was not here
GPS1SEC=1'b1;
send_serial_line;
send_serial_bit('h0a);
GPS1SEC=1'b0;
send_serial_line;
send_serial_bit('h0a);
send_serial_pause;
send_serial_pause;
ODOMETER_PULSE=1'b1;
send_serial_pause;
ODOMETER_PULSE=1'b0;
// repeat (20) send_serial_pause;
end
end
`endif
`ifdef TEST_IMU
assign IMU_MOSI_OUT=IMU_103695REVA? IMU_MOSI_REVA : IMU_MOSI;
assign IMU_SCLK_OUT=IMU_103695REVA?(IMU_SCLK):IMU_SCL;
always @ (posedge IMU_SDA) begin
IMU_EN<=IMU_MOSI;
end
wire IMU_CS=IMU_103695REVA?!IMU_ACTIVE:!(IMU_EN &&IMU_SDA);
reg IMU_MOSI_D;
always @ (posedge IMU_SCLK_OUT) begin
// IMU_MOSI_D<=IMU_MOSI;
IMU_MOSI_D<=IMU_MOSI_OUT;
end
reg [15:0] IMU_LOOPBACK;
always @ (negedge IMU_SCLK_OUT) begin
if (!IMU_CS) IMU_LOOPBACK[15:0]<={IMU_LOOPBACK[14:0],IMU_MOSI_D};
end
assign gpio_pins[3]=IMU_CS?IMU_DATA_READY:IMU_LOOPBACK[15];
PULLUP i_IMU_SDA (.O(IMU_SDA));
PULLUP i_IMU_SCL (.O(IMU_SCL));
initial begin
// SERIAL_DATA_FD=$fopen("gps_data.dat","r");
end
always begin
#(IMU_READY_PERIOD-IMU_NREADY_DURATION) IMU_DATA_READY=1'b0;
#(IMU_NREADY_DURATION) IMU_DATA_READY=1'b1;
end
assign gpio_pins[4]=SERIAL_BIT;
assign gpio_pins[5]=GPS1SEC;
// assign gpio_pins[6]=ODOMETER_PULSE;
assign gpio_pins[9]=ODOMETER_PULSE;
oneshot i_oneshot (.trigger(IMU_NMOSI),
.out(IMU_ACTIVE));
dly5taps i_dly5taps (.dly_in(IMU_NMOSI),
.dly_out(IMU_TAPS[5:1]));
always @ (negedge IMU_ACTIVE or posedge IMU_TAPS[5]) if (!IMU_ACTIVE) IMU_LATE_ACKN<= 1'b0; else IMU_LATE_ACKN<= 1'b1;
always @ (negedge IMU_LATE_ACKN or posedge IMU_TAPS[4]) if (!IMU_LATE_ACKN) IMU_SCLK<= 1'b1; else IMU_SCLK<= ~IMU_SCLK;
always @ (negedge IMU_SCLK) IMU_MOSI_REVA <= IMU_NMOSI;
task send_serial_bit;
input [7:0] data_byte;
reg [7:0] d;
begin
RS232_SENDING_BYTE <= 1;
d <= data_byte;
wait (axi_hclk); wait (~axi_hclk);
// SERIAL_BIT should be 1 here
// Send start bit
SERIAL_BIT <= 1'b0;
repeat (IMU_GPS_BIT_PERIOD) begin wait (axi_hclk); wait (~axi_hclk); end
// Send 8 data bits, LSB first
repeat (8) begin
SERIAL_BIT <= d[0];
#1 d[7:0] <= {1'b0,d[7:1]};
repeat (IMU_GPS_BIT_PERIOD) begin wait (axi_hclk); wait (~axi_hclk); end
end
// Send stop bit
SERIAL_BIT <= 1'b1;
RS232_SENDING_BYTE <= 0; // before stop bit
repeat (IMU_GPS_BIT_PERIOD) begin wait (axi_hclk); wait (~axi_hclk); end
end
endtask
task send_serial_pause;
begin
RS232_SENDING_PAUSE <= 1;
wait (axi_hclk); wait (~axi_hclk);
SERIAL_BIT <= 1'b1;
repeat (16) begin
repeat (IMU_GPS_BIT_PERIOD) begin wait (axi_hclk); wait (~axi_hclk); end
end
RS232_SENDING_PAUSE <= 0;
end
endtask
// SERIAL_DATA_FD=$fopen("gps_data.dat","r");
task send_serial_line;
integer char;
begin
char=0;
while (!$feof (SERIAL_DATA_FD) && (char != 'h0a)) begin
char=$fgetc(SERIAL_DATA_FD);
send_serial_bit(char);
end
end
endtask
`endif
endmodule endmodule
module oneshot(trigger,
out);
input trigger;
output out;
reg out;
event start;
parameter duration=4000;
initial out= 0;
always @ (posedge trigger) begin
disable timeout;
#0 -> start;
end
always @start
begin : timeout
out = 1;
# duration out = 0;
end
endmodule
module dly5taps (dly_in,
dly_out);
input dly_in;
output [5:1] dly_out;
reg [5:1] dly_out;
parameter dly=6; // delay per tap, ns
always @ (dly_in) # dly dly_out[1] <= dly_in;
always @ (dly_out[1]) # dly dly_out[2] <= dly_out[1];
always @ (dly_out[2]) # dly dly_out[3] <= dly_out[2];
always @ (dly_out[3]) # dly dly_out[4] <= dly_out[3];
always @ (dly_out[4]) # dly dly_out[5] <= dly_out[4];
endmodule
logger/event_logger.v
View file @ 158be190
...@@ -92,7 +92,8 @@ module event_logger#( ...@@ -92,7 +92,8 @@ module event_logger#(
// byte-parallel timestamps from 4 sensors channels (in triggered mode all are the same, different only in free running mode) // byte-parallel timestamps from 4 sensors channels (in triggered mode all are the same, different only in free running mode)
// each may generate logger event, channel number encoded in bits 25:24 of the external microseconds // each may generate logger event, channel number encoded in bits 25:24 of the external microseconds
input [3:0] sof_mclk, // start of frame (per-channel) to filter out non-first timestamps
input ts_stb_chn0, // @mclk 1 clock before ts_rcv_data is valid input ts_stb_chn0, // @mclk 1 clock before ts_rcv_data is valid
input [7:0] ts_data_chn0, // @mclk byte-wide serialized timestamp message received or local input [7:0] ts_data_chn0, // @mclk byte-wide serialized timestamp message received or local
...@@ -133,8 +134,8 @@ module event_logger#( ...@@ -133,8 +134,8 @@ module event_logger#(
reg we_config_gps; // bits 6:3, 7 - enable - {ext,invert, slot[1:0]} slot==0 - disable reg we_config_gps; // bits 6:3, 7 - enable - {ext,invert, slot[1:0]} slot==0 - disable
reg we_config_msg; // bits 12:8,13 - enable - {invert,extinp[3:0]} extinp[3:0]=='hf' - disable reg we_config_msg; // bits 12:8,13 - enable - {invert,extinp[3:0]} extinp[3:0]=='hf' - disable
reg we_config_syn; // bit 14, 15 - enable - enable logging external timestamps reg we_config_syn; // bit 14, 15 - enable - enable logging external timestamps
reg we_config_rst; // bit 14, 15 - enable - enable logging external timestamps reg we_config_rst; // bit 14, 15 - enable - reset
reg we_config_debug; // bit 14, 15 - enable - enable logging external timestamps reg we_config_debug; // bit 14, 15 - enable - debug bits set
reg we_bitHalfPeriod; reg we_bitHalfPeriod;
...@@ -159,7 +160,7 @@ module event_logger#( ...@@ -159,7 +160,7 @@ module event_logger#(
reg [3:0] config_gps_mclk; reg [3:0] config_gps_mclk;
reg [4:0] config_msg_mclk; reg [4:0] config_msg_mclk;
reg [3:0] config_syn_mclk; reg [3:0] config_syn_mclk;
reg config_rst_mclk; reg config_rst_mclk = 0;
reg [3:0] config_debug_mclk; reg [3:0] config_debug_mclk;
reg [15:0] bitHalfPeriod_mclk; reg [15:0] bitHalfPeriod_mclk;
...@@ -211,6 +212,8 @@ module event_logger#( ...@@ -211,6 +212,8 @@ module event_logger#(
reg [31:0] cmd_data_r; // valid next after cmd_we; reg [31:0] cmd_data_r; // valid next after cmd_we;
wire cmd_we; wire cmd_we;
wire cmd_status; wire cmd_status;
reg [3:0] timestamps_en; // enable timestamp to go through (first after sof)
assign ext_en = {{(GPIO_N-5){1'b0}}, assign ext_en = {{(GPIO_N-5){1'b0}},
(config_imu[1:0]==2'h2)?1'b1:1'b0, (config_imu[1:0]==2'h2)?1'b1:1'b0,
...@@ -241,6 +244,9 @@ module event_logger#( ...@@ -241,6 +244,9 @@ module event_logger#(
assign timestamp_request[1]=config_gps[3]? (config_gps[2]?nmea_sent_start:gps_ts_stb):gps_pulse1sec_single; assign timestamp_request[1]=config_gps[3]? (config_gps[2]?nmea_sent_start:gps_ts_stb):gps_pulse1sec_single;
always @ (posedge mclk) begin
timestamps_en <= enable_syn_mclk & (sof_mclk | (timestamps_en & ~{ts_stb_chn3, ts_stb_chn2,ts_stb_chn1, ts_stb_chn0}));
end
// filter gps_pulse1sec // filter gps_pulse1sec
always @ (posedge xclk) begin always @ (posedge xclk) begin
...@@ -257,9 +263,24 @@ module event_logger#( ...@@ -257,9 +263,24 @@ module event_logger#(
gps_pulse1sec_single <= !gps_pulse1sec_denoise[1] && gps_pulse1sec_denoise[0]; gps_pulse1sec_single <= !gps_pulse1sec_denoise[1] && gps_pulse1sec_denoise[0];
end end
always @ (posedge mclk or posedge mrst) begin // was negedge
we_d <= !mrst && cmd_we && !cmd_a;
we_imu <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_IMU);
we_gps <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_GPS);
we_message <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_MSG);
we_period <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_PERIOD);
we_bit_duration <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_BIT_DURATION);
we_bitHalfPeriod<= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_BIT_HALF_PERIOD);
we_config_imu <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_IMU];
we_config_gps <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_GPS];
we_config_msg <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_MSG];
we_config_syn <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_SYN];
we_config_rst <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_EN];
we_config_debug <= !mrst && cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_DBG];
end
always @ (posedge mclk) begin // was negedge always @ (posedge mclk) begin // was negedge
if (cmd_we) cmd_data_r <= cmd_data; // valid next after cmd_we; if (cmd_we) cmd_data_r <= cmd_data; // valid next after cmd_we;
/*
we_d <= cmd_we && !cmd_a; we_d <= cmd_we && !cmd_a;
we_imu <= cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_IMU); we_imu <= cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_IMU);
we_gps <= cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_GPS); we_gps <= cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_GPS);
...@@ -273,6 +294,7 @@ module event_logger#( ...@@ -273,6 +294,7 @@ module event_logger#(
we_config_syn <= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_SYN]; we_config_syn <= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_SYN];
we_config_rst <= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_EN]; we_config_rst <= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_EN];
we_config_debug <= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_DBG]; we_config_debug <= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_DBG];
*/
if (we_config_imu) config_imu_mclk[1:0] <= cmd_data_r[LOGGER_CONF_IMU - 1 -: LOGGER_CONF_IMU_BITS]; // bits 1:0, 2 - enable slot[1:0] if (we_config_imu) config_imu_mclk[1:0] <= cmd_data_r[LOGGER_CONF_IMU - 1 -: LOGGER_CONF_IMU_BITS]; // bits 1:0, 2 - enable slot[1:0]
if (we_config_gps) config_gps_mclk[3:0] <= cmd_data_r[LOGGER_CONF_GPS - 1 -: LOGGER_CONF_GPS_BITS]; // bits 6:3, 7 - enable - {ext,inver, slot[1:0]} slot==0 - disable if (we_config_gps) config_gps_mclk[3:0] <= cmd_data_r[LOGGER_CONF_GPS - 1 -: LOGGER_CONF_GPS_BITS]; // bits 6:3, 7 - enable - {ext,inver, slot[1:0]} slot==0 - disable
...@@ -400,24 +422,24 @@ fixed-length de-noise circuitry with latency 256*T(xclk) (~3usec) ...@@ -400,24 +422,24 @@ fixed-length de-noise circuitry with latency 256*T(xclk) (~3usec)
/* logs frame synchronization data from other camera (same as frame sync) */ /* logs frame synchronization data from other camera (same as frame sync) */
// ts_stb (mclk) -> trig) // ts_stb (mclk) -> trig)
imu_exttime393 i_imu_exttime( imu_exttime393 i_imu_exttime(
// .rst (rst), // input global reset // .rst (rst), // input global reset
.mclk (mclk), // system clock, negedge .mclk (mclk), // system clock, negedge
.xclk (xclk), // half frequency (80 MHz nominal) .xclk (xclk), // half frequency (80 MHz nominal)
.mrst (mrst), // @mclk - sync reset .mrst (mrst), // @mclk - sync reset
.xrst (xrst), // @xclk - sync reset .xrst (xrst), // @xclk - sync reset
.en_chn_mclk (enable_syn_mclk), // enable module operation, if 0 - reset .en_chn_mclk (enable_syn_mclk), // input[3:0] enable module operation, if 0 - reset
.ts_stb_chn0 (ts_stb_chn0), // input .ts_stb_chn0 (ts_stb_chn0 && timestamps_en[0]), // input
.ts_data_chn0 (ts_data_chn0), // input[7:0] .ts_data_chn0 (ts_data_chn0), // input[7:0]
.ts_stb_chn1 (ts_stb_chn1), // input .ts_stb_chn1 (ts_stb_chn1 && timestamps_en[1]), // input
.ts_data_chn1 (ts_data_chn1), // input[7:0] .ts_data_chn1 (ts_data_chn1), // input[7:0]
.ts_stb_chn2 (ts_stb_chn2), // input .ts_stb_chn2 (ts_stb_chn2 && timestamps_en[2]), // input
.ts_data_chn2 (ts_data_chn2), // input[7:0] .ts_data_chn2 (ts_data_chn2), // input[7:0]
.ts_stb_chn3 (ts_stb_chn3), // input .ts_stb_chn3 (ts_stb_chn3 && timestamps_en[3]), // input
.ts_data_chn3 (ts_data_chn3), // input[7:0] .ts_data_chn3 (ts_data_chn3), // input[7:0]
.ts (timestamp_request[2]), // timestamop request .ts (timestamp_request[2]), // timestamop request
.rdy (channel_ready[2]), // data ready .rdy (channel_ready[2]), // data ready
.rd_stb (channel_next[2]), // data read strobe (increment address) .rd_stb (channel_next[2]), // data read strobe (increment address)
.rdata (extts_data[15:0])); // data out (16 bits) .rdata (extts_data[15:0])); // data out (16 bits)
imu_timestamps393 i_imu_timestamps ( imu_timestamps393 i_imu_timestamps (
.xclk (xclk), // 80 MHz, posedge .xclk (xclk), // 80 MHz, posedge
......
logger/imu_exttime393.v
View file @ 158be190
...@@ -67,21 +67,23 @@ module imu_exttime393( ...@@ -67,21 +67,23 @@ module imu_exttime393(
output ts, // timestamop request output ts, // timestamop request
output reg rdy, // data ready will go up with timestamp request (ahead of actual time), but it will output reg rdy, // data ready will go up with timestamp request (ahead of actual time), but it will
// anyway be ready sooner, than the local timestamp retrieved ant sent // anyway be ready sooner, than the local timestamp retrieved ant sent
input rd_stb, // data read strobe (increment address) - continuous 1'b1 until allthe packet is read out input rd_stb, // data read strobe (increment address) - continuous 1'b1 until all the packet is read out
output [15:0] rdata); // data out (16 bits) output [15:0] rdata); // data out (16 bits)
reg [ 4:0] raddr; reg [ 4:0] raddr;
wire en_mclk = |en_chn_mclk; wire en_mclk = |en_chn_mclk;
wire [3:0] ts_stb = {ts_stb_chn3, ts_stb_chn2, ts_stb_chn1, ts_stb_chn0}; wire [3:0] ts_stb = {ts_stb_chn3, ts_stb_chn2, ts_stb_chn1, ts_stb_chn0};
wire [3:0] ts_got; // timestamp transferred to the channel FIFO
reg en; reg en;
reg rd_stb_r; reg rd_stb_r;
reg rd_start; // 1 xclk pulse at the readout start reg rd_start; // 1 xclk pulse at the readout start
wire rd_start_mclk; wire rd_start_mclk;
reg ts_full; // internal 4 x 16 fifo is full (or getting full) reg ts_full; // internal 4 x 16 fifo is full (or getting full)
reg ts_pend; // ts fifo waiting to be rdead out
reg [3:0] in_full; // input fifo has (or is acquiring) timestamp reg [3:0] in_full; // input fifo has (or is acquiring) timestamp
wire pre_copy_w; wire pre_copy_w;
reg [1:0] copy_selected; // copying from the winner of 4 input fifos to the x16 output fifo reg [1:0] copy_selected; // copying from the winner of 4 input FIFOs to the x16 output fifo
reg copy_started; reg copy_started;
reg [2:0] copy_cntr; // byte counter for copying reg [2:0] copy_cntr; // byte counter for copying
reg [1:0] sel_chn; // selected channel reg [1:0] sel_chn; // selected channel
...@@ -90,11 +92,11 @@ module imu_exttime393( ...@@ -90,11 +92,11 @@ module imu_exttime393(
wire [3:0] chn_pri_w; wire [3:0] chn_pri_w;
wire [1:0] chn_enc_w; wire [1:0] chn_enc_w;
reg [15:0] ts_ram [0:3]; // inner timestamp x16 memory that receives timestamp from one of the 4 input channel fifos reg [15:0] ts_ram [0:3]; // inner timestamp x16 memory that receives timestamp from one of the 4 input channel FIFOs
wire [31:0] dout_chn; wire [31:0] dout_chn;
wire [7:0] copy_data; // data from the selected input fifos wire [7:0] copy_data; // data from the selected input fifos
reg [7:0] copy_data_r; // low byte of the timestamp data being copied from one of the input fifos to the ts_ram reg [7:0] copy_data_r; // low byte of the timestamp data being copied from one of the input FIFOs to the ts_ram
reg rd_stb_mclk;
assign chn_pri_w = {in_full[3] & ~(|in_full[2:0]), assign chn_pri_w = {in_full[3] & ~(|in_full[2:0]),
in_full[2] & ~(|in_full[1:0]), in_full[2] & ~(|in_full[1:0]),
in_full[1] & ~in_full[0], in_full[1] & ~in_full[0],
...@@ -110,14 +112,24 @@ module imu_exttime393( ...@@ -110,14 +112,24 @@ module imu_exttime393(
always @ (posedge mclk) begin always @ (posedge mclk) begin
copy_started <= pre_copy_started; copy_started <= pre_copy_started;
if (!en_mclk) ts_full <= 0;
else if (pre_copy_started) ts_full <= 1; // turns on before in_full[*] - || will have no glitches rd_stb_mclk <= rd_stb;
else if (rd_start_mclk) ts_full <= 0; if (!en_mclk) ts_full <= 0;
else if (pre_copy_started) ts_full <= 1; // turns on before in_full[*] - || will have no glitches
// else if (rd_start_mclk) ts_full <= 0;
else if (!ts_pend && !rd_stb_mclk) ts_full <= 0;
if (!en_mclk) ts_pend <= 0;
else if (pre_copy_started) ts_pend <= 1;
else if (rd_stb_mclk) ts_pend <= 0;
if (!en_mclk) in_full <= 0; if (!en_mclk) in_full <= 0;
else in_full <= en_chn_mclk & (ts_stb | (in_full & ~(chn1hot & {4{copy_started}}))); else in_full <= en_chn_mclk & (ts_got | (in_full & ~(chn1hot & {4{copy_started}})));
copy_selected <= {copy_selected[0], pre_copy_w | (copy_selected[0] & ~(&copy_cntr[2:1]))}; // off at count 6 // copy_selected <= {copy_selected[0], (|en_chn_mclk) & (pre_copy_w | (copy_selected[0] & ~(&copy_cntr[2:1])))}; // off at count 6
copy_selected <= {copy_selected[0], (|en_chn_mclk) & (pre_copy_w | (copy_selected[0] & (copy_cntr[2] | ~copy_cntr[1] )))}; // off at count 2
if (pre_copy_w) sel_chn <= chn_enc_w; if (pre_copy_w) sel_chn <= chn_enc_w;
...@@ -145,6 +157,10 @@ module imu_exttime393( ...@@ -145,6 +157,10 @@ module imu_exttime393(
else if (rd_stb && (raddr[1:0]==2'h3)) rdy <= 1'b0; else if (rd_stb && (raddr[1:0]==2'h3)) rdy <= 1'b0;
end end
dly_var #(.WIDTH(1),.DLY_WIDTH(4)) ts_got0_i (.clk(mclk),.rst(~en_chn_mclk[0]), .dly(4'h7), .din(ts_stb[0]),.dout(ts_got[0]));
dly_var #(.WIDTH(1),.DLY_WIDTH(4)) ts_got1_i (.clk(mclk),.rst(~en_chn_mclk[1]), .dly(4'h7), .din(ts_stb[1]),.dout(ts_got[1]));
dly_var #(.WIDTH(1),.DLY_WIDTH(4)) ts_got2_i (.clk(mclk),.rst(~en_chn_mclk[2]), .dly(4'h7), .din(ts_stb[2]),.dout(ts_got[2]));
dly_var #(.WIDTH(1),.DLY_WIDTH(4)) ts_got3_i (.clk(mclk),.rst(~en_chn_mclk[3]), .dly(4'h7), .din(ts_stb[3]),.dout(ts_got[3]));
timestamp_fifo timestamp_fifo_chn0_i ( timestamp_fifo timestamp_fifo_chn0_i (
...@@ -155,7 +171,7 @@ module imu_exttime393( ...@@ -155,7 +171,7 @@ module imu_exttime393(
.din (ts_data_chn0), // input[7:0] .din (ts_data_chn0), // input[7:0]
.aclk (mclk), // input .aclk (mclk), // input
.arst (mrst), // input .arst (mrst), // input
.advance (ts_stb[0]), // enough time .advance (ts_got[0]), // enough time
.rclk (mclk), // input .rclk (mclk), // input
.rrst (mrst), // input .rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h0)),// input .rstb (pre_copy_started && (sel_chn == 2'h0)),// input
...@@ -170,7 +186,7 @@ module imu_exttime393( ...@@ -170,7 +186,7 @@ module imu_exttime393(
.din (ts_data_chn1), // input[7:0] .din (ts_data_chn1), // input[7:0]
.aclk (mclk), // input .aclk (mclk), // input
.arst (mrst), // input .arst (mrst), // input
.advance (ts_stb[1]), // enough time .advance (ts_got[1]), // enough time
.rclk (mclk), // input .rclk (mclk), // input
.rrst (mrst), // input .rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h1)),// input .rstb (pre_copy_started && (sel_chn == 2'h1)),// input
...@@ -185,7 +201,7 @@ module imu_exttime393( ...@@ -185,7 +201,7 @@ module imu_exttime393(
.din (ts_data_chn2), // input[7:0] .din (ts_data_chn2), // input[7:0]
.aclk (mclk), // input .aclk (mclk), // input
.arst (mrst), // input .arst (mrst), // input
.advance (ts_stb[2]), // enough time .advance (ts_got[2]), // enough time
.rclk (mclk), // input .rclk (mclk), // input
.rrst (mrst), // input .rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h2)),// input .rstb (pre_copy_started && (sel_chn == 2'h2)),// input
...@@ -200,7 +216,7 @@ module imu_exttime393( ...@@ -200,7 +216,7 @@ module imu_exttime393(
.din (ts_data_chn3), // input[7:0] .din (ts_data_chn3), // input[7:0]
.aclk (mclk), // input .aclk (mclk), // input
.arst (mrst), // input .arst (mrst), // input
.advance (ts_stb[3]), // enough time .advance (ts_got[3]), // enough time
.rclk (mclk), // input .rclk (mclk), // input
.rrst (mrst), // input .rrst (mrst), // input
.rstb (pre_copy_started && (sel_chn == 2'h3)),// input .rstb (pre_copy_started && (sel_chn == 2'h3)),// input
...@@ -208,10 +224,12 @@ module imu_exttime393( ...@@ -208,10 +224,12 @@ module imu_exttime393(
); );
pulse_cross_clock i_rd_start_mclk (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(rd_start), .out_pulse(rd_start_mclk),.busy()); // pulse_cross_clock i_rd_start_mclk (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(rd_start), .out_pulse(rd_start_mclk),.busy());
pulse_cross_clock i_rd_start_mclk (.rst(!en), .src_clk(xclk), .dst_clk(mclk), .in_pulse(rd_start), .out_pulse(rd_start_mclk),.busy());
// generate timestamp request as soon as one of the sub-channels starts copying. That time stamp will be stored for this (ext) channel // generate timestamp request as soon as one of the sub-channels starts copying. That time stamp will be stored for this (ext) channel
pulse_cross_clock i_ts (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(pre_copy_w), .out_pulse(ts),.busy()); // pulse_cross_clock i_ts (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(pre_copy_w), .out_pulse(ts),.busy());
pulse_cross_clock i_ts (.rst(en_chn_mclk == 0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(pre_copy_w), .out_pulse(ts),.busy());
endmodule endmodule
logger/imu_message393.v
View file @ 158be190
...@@ -81,11 +81,11 @@ module imu_message393 ( ...@@ -81,11 +81,11 @@ module imu_message393 (
ts_r <= !trig_denoise[1] && trig_denoise[0]; ts_r <= !trig_denoise[1] && trig_denoise[0];
if (!en || ts_r) raddr[4:0] <= 5'h0; if (!en || ts_r) raddr[4:0] <= 5'h0;
else if (rd_stb) raddr[4:0] <= raddr[4:0] + 1; else if (rd_stb) raddr[4:0] <= raddr[4:0] + 1;
if (ts_r || (rd_stb && (raddr[4:0]==5'h1b)) || !en) rdy_r <= 1'b0; if (ts_r || (rd_stb && (raddr[4:0]==5'h1b)) || !en) rdy_r <= 1'b0;
else if (trig_denoise[1] && !trig_denoise[0]) rdy_r <= 1'b1; else if (trig_denoise[1] && !trig_denoise[0]) rdy_r <= 1'b1;
end end
reg [31:0] odbuf0_ram[0:15]; reg [31:0] odbuf0_ram[0:15];
......
logger/imu_spi393.v
View file @ 158be190
...@@ -40,25 +40,24 @@ ...@@ -40,25 +40,24 @@
module imu_spi393( module imu_spi393(
// input rst, // input rst,
input mclk, // system clock, negedge TODO:COnvert to posedge! input mclk, // system clock, negedge TODO:COnvert to posedge!
input xclk, // half frequency (80 MHz nominal) input xclk, // half frequency (80 MHz nominal)
input we_ra, // write enable for registers to log (@negedge clk)
input we_ra, // write enable for registers to log (@negedge clk) input we_div, // write enable for clock dividing(@negedge clk)
input we_div,// write enable for clock dividing(@negedge clk) input we_period, // write enable for IMU cycle period(@negedge clk) 0 - disable, 1 - single, >1 - half bit periods
input we_period,// write enable for IMU cycle period(@negedge clk) 0 - disable, 1 - single, >1 - half bit periods input [ 4:0] wa, // write address for register (5 bits, @negedge clk)
input [ 4:0] wa, // write address for register (5 bits, @negedge clk) input [31:0] din, //
input [31:0] din, // output mosi, // to IMU, bit 2 in J9
output mosi, // to IMU, bit 2 in J9 input miso, // from IMU, bit 3 on J9
input miso, // from IMU, bit 3 on J9
input [ 3:0] config_debug, // bit 0 - long sda_en input [ 3:0] config_debug, // bit 0 - long sda_en
output sda, // sda, shared with i2c, bit 1 output sda, // sda, shared with i2c, bit 1
output sda_en, // enable sda output (when sda==0 and 1 cycle after sda 0->1) output sda_en, // enable sda output (when sda==0 and 1 cycle after sda 0->1)
output scl, // scl, shared with i2c, bit 0 output scl, // scl, shared with i2c, bit 0
output scl_en, // enable scl output (when scl==0 and 1 cycle after sda 0->1) output scl_en, // enable scl output (when scl==0 and 1 cycle after sda 0->1)
output ts, // timestamop request output ts, // timestamp request
output rdy, // data ready output rdy, // data ready
input rd_stb, // data read strobe (increment address) input rd_stb, // data read strobe (increment address)
output [15:0] rdata); // data out (16 bits) output [15:0] rdata); // data out (16 bits)
/* /*
input mclk; // system clock, negedge input mclk; // system clock, negedge
input xclk; // half frequency (80 MHz nominal) input xclk; // half frequency (80 MHz nominal)
...@@ -115,14 +114,14 @@ module imu_spi393( ...@@ -115,14 +114,14 @@ module imu_spi393(
reg imu_start; reg imu_start;
reg ts_r; // delay imu_start by one cycle, so it will be after rdy is reset reg ts_r; // delay imu_start by one cycle, so it will be after rdy is reset
reg [31:0] period; // 0 - disable, 1 - single, >1 - period in 50 ns steps reg [31:0] period=0; // 0 - disable, 1 - single, >1 - period in 50 ns steps
// reg [15:0] di_d; // reg [15:0] di_d;
reg imu_enabled_mclk; reg imu_enabled_mclk = 0;
reg [1:0] imu_enabled=2'h0; reg [1:0] imu_enabled=2'h0;
reg imu_run_mclk; reg imu_run_mclk = 0;
reg [1:0] imu_run; reg [1:0] imu_run;
reg imu_when_ready_mclk; reg imu_when_ready_mclk = 0;
reg [1:0] imu_when_ready; reg [1:0] imu_when_ready;
reg imu_run_confirmed; reg imu_run_confirmed;
...@@ -184,7 +183,7 @@ module imu_spi393( ...@@ -184,7 +183,7 @@ module imu_spi393(
if (we_period) period[31:0] <= din[31:0]; if (we_period) period[31:0] <= din[31:0];
if (we_timer[2]) imu_run_mclk <= (period[31:1]!=31'b0); // double-cycle if (we_timer[2]) imu_run_mclk <= (period[31:1]!=31'b0); // double-cycle
if (we_timer[3]) imu_enabled_mclk <= imu_run_mclk | period[0]; if (we_timer[3]) imu_enabled_mclk <= imu_run_mclk | period[0]; // NC393: Why period[0]?
if (we_timer[2]) imu_when_ready_mclk <= &period[31:16]; // double-cycle if (we_timer[2]) imu_when_ready_mclk <= &period[31:16]; // double-cycle
...@@ -317,8 +316,8 @@ module imu_spi393( ...@@ -317,8 +316,8 @@ module imu_spi393(
sngl_wire_stb[2:0] <={sngl_wire_stb[1:0], en & ((scl_r[0] ^ pre_scl) | end_prepare)}; sngl_wire_stb[2:0] <={sngl_wire_stb[1:0], en & ((scl_r[0] ^ pre_scl) | end_prepare)};
if (!en) sngl_wire_r[0]<=1'b0; if (!en) sngl_wire_r[0]<=1'b0;
else if ((pre_scl ^scl_r[0]) | end_prepare) sngl_wire_r[0]<=1'b1; else if ((pre_scl ^scl_r[0]) | end_prepare) sngl_wire_r[0]<=1'b1;
else if (!mosi_reg[15] || sngl_wire_stb[2] || scl_r[0]) sngl_wire_r[0]<=1'b0; else if (!mosi_reg[15] || sngl_wire_stb[2] || scl_r[0]) sngl_wire_r[0]<=1'b0;
......
logger/logger_arbiter393.v
View file @ 158be190
...@@ -39,9 +39,9 @@ ...@@ -39,9 +39,9 @@
`timescale 1ns/1ps `timescale 1ns/1ps
module logger_arbiter393( module logger_arbiter393(
input xclk, // half frequency (80 MHz nominal) input xclk, // half frequency (80 MHz nominal)
input rst, // module reset (sync) input rst, // module reset (sync)
input [3:0] ts_rq_in, // in requests for timestamp (single-cycle - just leading edge ) input [3:0] ts_rq_in, // in requests for timestamp (single-cycle - just leading edge )
output [3:0] ts_rq, // out request for timestamp, to timestmp module output [3:0] ts_rq, // out request for timestamp, to timestmp module
input [3:0] ts_grant, // granted ts requests from timestamping module input [3:0] ts_grant, // granted ts requests from timestamping module
input [3:0] rdy, // channels ready (leading edge - became ready, trailing - no more data, use zero) input [3:0] rdy, // channels ready (leading edge - became ready, trailing - no more data, use zero)
...@@ -98,7 +98,7 @@ module logger_arbiter393( ...@@ -98,7 +98,7 @@ module logger_arbiter393(
always @ (posedge xclk) begin always @ (posedge xclk) begin
ts_rq_in_d[3:0] <= ts_rq_in[3:0]; ts_rq_in_d[3:0] <= ts_rq_in[3:0];
if (rst) channel_r[1:0] <= 0;
if (wstart) channel_r[1:0] <= {chn1hot[3] | chn1hot[2],chn1hot[3] | chn1hot[1]}; if (wstart) channel_r[1:0] <= {chn1hot[3] | chn1hot[2],chn1hot[3] | chn1hot[1]};
if (wstart) chn_servicing[3:0] <= {chn1hot[3:1], ~|chn1hot[3:1]}; if (wstart) chn_servicing[3:0] <= {chn1hot[3:1], ~|chn1hot[3:1]};
...@@ -109,7 +109,7 @@ module logger_arbiter393( ...@@ -109,7 +109,7 @@ module logger_arbiter393(
else ts_rq_r[3:0] <= ~ts_grant & ( wts_rq[3:0] | ts_rq_r[3:0]); else ts_rq_r[3:0] <= ~ts_grant & ( wts_rq[3:0] | ts_rq_r[3:0]);
if (rst) ts_valid[3:0] <= 4'h0; if (rst) ts_valid[3:0] <= 4'h0;
else ts_valid[3:0] <= (ts_grant[3:0] | (ts_valid & ~wts_rq[3:0])); else ts_valid[3:0] <= (ts_grant[3:0] | (ts_valid & ~wts_rq[3:0]));
channels_ready[3:0] <= ts_valid[3:0] & rdy[3:0] & ~chn_servicing[3:0]; // ready should go down during servicing channels_ready[3:0] <= ts_valid[3:0] & rdy[3:0] & ~chn_servicing[3:0]; // ready should go down during servicing
......
logger/nmea_decoder393.v
View file @ 158be190
...@@ -201,7 +201,7 @@ module nmea_decoder393( ...@@ -201,7 +201,7 @@ module nmea_decoder393(
if (restart) vfy_first_comma <= 1'b0; if (restart) vfy_first_comma <= 1'b0;
else if (stb[3] && msb) vfy_first_comma <= last_vfy_sent; else if (stb[3] && msb) vfy_first_comma <= last_vfy_sent;
if (restart) valid <= 1'b1; // ready @ stb[2] if (restart) valid <= 1'b1; // ready @ stb[2]
else if (stb[1] && (ser_di!=gp_exp_bit) && else if (stb[1] && (ser_di!=gp_exp_bit) &&
(vfy_dollar || vfy_gp || vfy_first_comma || (vfy_sel_sent && !lsbs5))) valid <= 1'b0; (vfy_dollar || vfy_gp || vfy_first_comma || (vfy_sel_sent && !lsbs5))) valid <= 1'b0;
...@@ -292,14 +292,14 @@ module nmea_decoder393( ...@@ -292,14 +292,14 @@ module nmea_decoder393(
assign rdata[11: 8] = odbuf2_ram[raddr[4:0]]; assign rdata[11: 8] = odbuf2_ram[raddr[4:0]];
assign rdata[15:12] = odbuf3_ram[raddr[4:0]]; assign rdata[15:12] = odbuf3_ram[raddr[4:0]];
reg [3:0] gpxxx_ram[0:3]; reg [3:0] gpxxx_ram[0:15];
always @ (posedge mclk) if (we & ~wa[4]) gpxxx_ram[wa[3:0]] <= wd[3:0]; always @ (posedge mclk) if (we & ~wa[4]) gpxxx_ram[wa[3:0]] <= wd[3:0];
assign gpxxx_w_one[3:0] = gpxxx_ram[gpxxx_addr[3:0]]; assign gpxxx_w_one[3:0] = gpxxx_ram[gpxxx_addr[3:0]];
// for each of the four sentences first byte - number of field (<=24), next 3 bytes - formats for each nmea filed (LSB first): // for each of the four sentences first byte - number of field (<=24), next 3 bytes - formats for each nmea field (LSB first):
// 0 - nibble ("-" -> 0xd, "." -> 0xe), terminated with 0xf // 0 - nibble ("-" -> 0xd, "." -> 0xe), terminated with 0xf
// 1 - byte (2 nibbles), all bytes but last have MSB clear, last - set. // 1 - byte (2 nibbles), all bytes but last have MSB clear, last - set.
// No padding of nibbles to byte borders, bytes are encoded as 2 nibbles // No padding of nibbles to byte borders, bytes are encoded as 2 nibbles
reg [7:0] format_ram[0:3]; reg [7:0] format_ram[0:15];
always @ (posedge mclk) if (we & wa[4]) format_ram[wa[3:0]] <= wd[7:0]; always @ (posedge mclk) if (we & wa[4]) format_ram[wa[3:0]] <= wd[7:0];
assign format_data[7:0] = format_ram[{sentence[1:0],format_field[4:3]}]; assign format_data[7:0] = format_ram[{sentence[1:0],format_field[4:3]}];
......
py393/test_mcntrl.py
View file @ 158be190
...@@ -77,6 +77,7 @@ import x393_rtc ...@@ -77,6 +77,7 @@ import x393_rtc
import x393_jpeg import x393_jpeg
import vrlg import vrlg
import x393_export_c import x393_export_c
import x393_logger
__all__ = [] __all__ = []
__version__ = 0.1 __version__ = 0.1
__date__ = '2015-03-01' __date__ = '2015-03-01'
...@@ -358,6 +359,8 @@ USAGE ...@@ -358,6 +359,8 @@ USAGE
x393Rtc = x393_rtc.X393Rtc(verbose,args.simulated,args.localparams) x393Rtc = x393_rtc.X393Rtc(verbose,args.simulated,args.localparams)
x393Jpeg = x393_jpeg.X393Jpeg(verbose,args.simulated,args.localparams) x393Jpeg = x393_jpeg.X393Jpeg(verbose,args.simulated,args.localparams)
x393ExportC= x393_export_c.X393ExportC(verbose,args.simulated,args.localparams) x393ExportC= x393_export_c.X393ExportC(verbose,args.simulated,args.localparams)
x393Logger = x393_logger.X393Logger(verbose,args.simulated,args.localparams)
#X393Logger
''' '''
print ("----------------------") print ("----------------------")
print("x393_mem.__dict__="+str(x393_mem.__dict__)) print("x393_mem.__dict__="+str(x393_mem.__dict__))
...@@ -392,6 +395,7 @@ USAGE ...@@ -392,6 +395,7 @@ USAGE
extractTasks(x393_rtc.X393Rtc, x393Rtc) extractTasks(x393_rtc.X393Rtc, x393Rtc)
extractTasks(x393_jpeg.X393Jpeg, x393Jpeg) extractTasks(x393_jpeg.X393Jpeg, x393Jpeg)
extractTasks(x393_export_c.X393ExportC, x393ExportC) extractTasks(x393_export_c.X393ExportC, x393ExportC)
extractTasks(x393_logger.X393Logger, x393Logger)
for cmdLine in commands: for cmdLine in commands:
print ('Running task: '+str(cmdLine)) print ('Running task: '+str(cmdLine))
......
py393/x393_jpeg.py
View file @ 158be190
...@@ -2160,6 +2160,118 @@ jpeg_sim_multi 4 ...@@ -2160,6 +2160,118 @@ jpeg_sim_multi 4
jpeg_sim_multi 8 jpeg_sim_multi 8
################## Simulate Parallel 11 - external trigger ####################
./py393/test_mcntrl.py @py393/cocoargs --simulated=localhost:7777
measure_all "*DI"
setup_all_sensors True None 0xf
set_sensor_io_ctl all None None 1 # Set ARO low - check if it is still needed?
#just testing
set_gpio_ports 1 1 # enable software gpio pins and porta (camsync)
set_gpio_pins 0 1 # pin 0 low, pin 1 - high
set_logger_params_file "/home/eyesis/git/x393-neon/attic/imu_config.bin"
set_camsync_period 31 # set bit duration
set_camsync_period 8000 # 80 usec
set_camsync_delay 0 400
set_camsync_delay 1 100
set_camsync_delay 2 200
set_camsync_delay 3 300
#set_camsync_inout <is_out> <bit_number> <active_positive>
set_camsync_inout 1 8 0
#set_camsync_inout 0 7 0
reset_camsync_inout 0 # start with internal trigger
#set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None>
set_camsync_mode 1 1 1 1 0 0xf
set_sensor_histogram_window 0 0 4 4 25 21
set_sensor_histogram_window 1 0 4 4 41 21
set_sensor_histogram_window 2 0 4 4 25 41
set_sensor_histogram_window 3 0 4 4 41 41
r
read_control_register 0x430
read_control_register 0x431
write_cmd_frame_sequencer 0 1 2 0x600 0x48 # compressor q page = 1 // too late for frame 2
set_qtables 0 0 80
set_qtables 0 1 70
#irq coming, image not changing - yes
write_cmd_frame_sequencer 0 1 1 0x686 0x280005 #save 4 more lines than sensor has
write_cmd_frame_sequencer 0 1 1 0x680 0x5507 #enable abort
#write_cmd_frame_sequencer 0 1 1 0x6c6 0x300006 #save 4 more lines that compressor has
write_cmd_frame_sequencer 0 1 2 0x600 0x5 #stop compressor `
write_cmd_frame_sequencer 0 1 2 0x680 0x5405 # stop sensor memory (+0) // sensor memory should be controlled first, (9 commands
write_cmd_frame_sequencer 0 1 2 0x6c0 0x5c49 # stop compressor memory (+0)
write_cmd_frame_sequencer 0 1 3 0x686 0x240005 # correct lines
write_cmd_frame_sequencer 0 1 3 0x680 0x5507 # run sensor memory (+1) Can not be 0
write_cmd_frame_sequencer 0 1 4 0x686 0x280005 #save 4 more lines than sensor has
write_cmd_frame_sequencer 0 1 4 0x6c6 0x300006 #save more lines than compressor needs (sensor provides)
write_cmd_frame_sequencer 0 1 4 0x6c0 0x7d4b # run compressor memory (+2)
write_cmd_frame_sequencer 0 1 4 0x600 0x7 # run compressor (+0)
write_cmd_frame_sequencer 0 1 1 0x600 0x48 # compressor q page = 1
write_cmd_frame_sequencer 0 1 4 0x600 0x40 # compressor q page = 0
read_control_register 0x431
read_control_register 0x430
#testing histograms
write_control_register 0x409 0xc0
#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
#set_sensor_io_ctl all None None None None None 1 None # load all delays?
compressor_control all None None None None None 2
compressor_interrupt_control all clr
compressor_interrupt_control all en
compressor_control all 3
r
read_status 0x21
r
jpeg_sim_multi 4
r
read_status 0x21
r
jpeg_sim_multi 3
r
read_status 0x21
r
write_cmd_frame_sequencer 0 1 1 0x686 0x240005 # correct lines
write_cmd_frame_sequencer 0 1 1 0x6c6 0x200006 # correct lines
write_cmd_frame_sequencer 0 1 1 0x680 0x5507 # run sensor memory, update frame#, reset buffers
write_cmd_frame_sequencer 0 1 1 0x6c0 0x7d4b # run compressor memory
write_cmd_frame_sequencer 0 1 1 0x600 0x7 # run compressor
#switch to external (wired) trigger
set_camsync_inout 0 7 0
jpeg_sim_multi 4
###switch to external (wired) trigger
##set_camsync_inout 0 7 0
jpeg_sim_multi 4
#set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None>
#keeping external trigger mode (#9 was switching to internal)
#set_camsync_mode None None None 0
jpeg_sim_multi 4
jpeg_sim_multi 8
################## Serial #################### ################## Serial ####################
cd /usr/local/verilog/; test_mcntrl.py @hargs cd /usr/local/verilog/; test_mcntrl.py @hargs
......
x393.v
View file @ 158be190
...@@ -2314,7 +2314,8 @@ assign axi_grst = axi_rst_pre; ...@@ -2314,7 +2314,8 @@ assign axi_grst = axi_rst_pre;
.ts_local_data (ts_logegr_data), // input[7:0] .ts_local_data (ts_logegr_data), // input[7:0]
.ext_di (gpio_rd), // input[9:0] .ext_di (gpio_rd), // input[9:0]
.ext_do (gpio_logger), // output[9:0] .ext_do (gpio_logger), // output[9:0]
.ext_en (gpio_logger_en), // output[9:0] .ext_en (gpio_logger_en), // output[9:0]
.sof_mclk (sof_out_mclk), // input[3:0]
.ts_stb_chn0 (ts_pre_stb[0]), // input .ts_stb_chn0 (ts_pre_stb[0]), // input
.ts_data_chn0 (ts_data[0 * 8 +: 8]), // input[7:0] .ts_data_chn0 (ts_data[0 * 8 +: 8]), // input[7:0]
.ts_stb_chn1 (ts_pre_stb[1]), // input .ts_stb_chn1 (ts_pre_stb[1]), // input
......
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