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Commit 149d5fa7 authored by Andrey Filippov's avatar Andrey Filippov
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restoring parallel to 1003 - 1004 autoexposure problems

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fpga_version.vh
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...@@ -35,7 +35,8 @@ ...@@ -35,7 +35,8 @@
* contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
parameter FPGA_VERSION = 32'h03934015; // Boson640, for 103993A, debugging 4 removed DE deglitch - modifying decimation parameter FPGA_VERSION = 32'h03931003; // parallel, adding camsync trigger decimation - modifying decimation
// parameter FPGA_VERSION = 32'h03934015; // Boson640, for 103993A, debugging 4 removed DE deglitch - modifying decimation
// parameter FPGA_VERSION = 32'h03931004; // parallel, adding camsync trigger decimation - modifying decimation // parameter FPGA_VERSION = 32'h03931004; // parallel, adding camsync trigger decimation - modifying decimation
// parameter FPGA_VERSION = 32'h03934014; // Boson640, for 103993A, debugging 4 removed DE deglitch // parameter FPGA_VERSION = 32'h03934014; // Boson640, for 103993A, debugging 4 removed DE deglitch
// parameter FPGA_VERSION = 32'h03934013; // Boson640, for 103993A, debugging 3 failed (maybe just phases) // parameter FPGA_VERSION = 32'h03934013; // Boson640, for 103993A, debugging 3 failed (maybe just phases)
...@@ -303,4 +304,4 @@ ...@@ -303,4 +304,4 @@
// parameter FPGA_VERSION = 32'h03930056; // 'new' (no 2x clocks) sensor/converter w/o debug - broken // parameter FPGA_VERSION = 32'h03930056; // 'new' (no 2x clocks) sensor/converter w/o debug - broken
// parameter FPGA_VERSION = 32'h03930055; // 'old' sensor/converter w/o debug, fixed bug with irst - OK // parameter FPGA_VERSION = 32'h03930055; // 'old' sensor/converter w/o debug, fixed bug with irst - OK
// parameter FPGA_VERSION = 32'h03930054; // 'old' sensor/converter with debug // parameter FPGA_VERSION = 32'h03930054; // 'old' sensor/converter with debug
// parameter FPGA_VERSION = 32'h03930053; // trying if(reset ) reg <- 'bx // parameter FPGA_VERSION = 32'h03930053; // trying if(reset ) reg <- 'bx
\ No newline at end of file
system_defines.vh
View file @ 149d5fa7
...@@ -65,7 +65,7 @@ ...@@ -65,7 +65,7 @@
`define DISPLAY_COMPRESSED_DATA `define DISPLAY_COMPRESSED_DATA
// if specific sesnor is not defined, parallel sensor interface is used for all channels // if specific sesnor is not defined, parallel sensor interface is used for all channels
/*************** CHANGE here and x393_hispi | x393_parallel | x393_lwir | x393_boson in bitstream (and few other) tool settings ****************/ /*************** CHANGE here and x393_hispi | x393_parallel | x393_lwir | x393_boson in bitstream (and few other) tool settings ****************/
`define BOSON 1 // `define BOSON 1
// `define LWIR // `define LWIR
// `define HISPI // `define HISPI
// also change in utilization and timimg summary tools (x393_parallel_utilization.report, ...) // also change in utilization and timimg summary tools (x393_parallel_utilization.report, ...)
......
x393_parallel.bit
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x393_parallel.timing_summary_impl
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x393_parallel_utilization.report
View file @ 149d5fa7
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Tue Apr 23 14:24:49 2019 | Date : Mon Mar 22 12:57:54 2021
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS | Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_utilization -file vivado_build/x393_parallel_utilization.report | Command : report_utilization -file vivado_build/x393_parallel_utilization.report
| Design : x393 | Design : x393
...@@ -31,13 +31,13 @@ Table of Contents ...@@ -31,13 +31,13 @@ Table of Contents
+----------------------------+-------+-------+-----------+-------+ +----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% | | Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+ +----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 41842 | 0 | 78600 | 53.23 | | Slice LUTs | 41951 | 0 | 78600 | 53.37 |
| LUT as Logic | 38488 | 0 | 78600 | 48.97 | | LUT as Logic | 38565 | 0 | 78600 | 49.06 |
| LUT as Memory | 3354 | 0 | 26600 | 12.61 | | LUT as Memory | 3386 | 0 | 26600 | 12.73 |
| LUT as Distributed RAM | 2802 | 0 | | | | LUT as Distributed RAM | 2850 | 0 | | |
| LUT as Shift Register | 552 | 0 | | | | LUT as Shift Register | 536 | 0 | | |
| Slice Registers | 53911 | 0 | 157200 | 34.29 | | Slice Registers | 54224 | 0 | 157200 | 34.49 |
| Register as Flip Flop | 53911 | 0 | 157200 | 34.29 | | Register as Flip Flop | 54224 | 0 | 157200 | 34.49 |
| Register as Latch | 0 | 0 | 157200 | 0.00 | | Register as Latch | 0 | 0 | 157200 | 0.00 |
| F7 Muxes | 30 | 0 | 39300 | 0.08 | | F7 Muxes | 30 | 0 | 39300 | 0.08 |
| F8 Muxes | 0 | 0 | 19650 | 0.00 | | F8 Muxes | 0 | 0 | 19650 | 0.00 |
...@@ -56,10 +56,10 @@ Table of Contents ...@@ -56,10 +56,10 @@ Table of Contents
| 0 | _ | Set | - | | 0 | _ | Set | - |
| 0 | _ | Reset | - | | 0 | _ | Reset | - |
| 0 | Yes | - | - | | 0 | Yes | - | - |
| 8 | Yes | - | Set | | 16 | Yes | - | Set |
| 672 | Yes | - | Reset | | 692 | Yes | - | Reset |
| 965 | Yes | Set | - | | 953 | Yes | Set | - |
| 52266 | Yes | Reset | - | | 52563 | Yes | Reset | - |
+-------+--------------+-------------+--------------+ +-------+--------------+-------------+--------------+
...@@ -69,27 +69,27 @@ Table of Contents ...@@ -69,27 +69,27 @@ Table of Contents
+-------------------------------------------+-------+-------+-----------+-------+ +-------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% | | Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+-------+-------+-----------+-------+ +-------------------------------------------+-------+-------+-----------+-------+
| Slice | 16425 | 0 | 19650 | 83.59 | | Slice | 16473 | 0 | 19650 | 83.83 |
| SLICEL | 10820 | 0 | | | | SLICEL | 10855 | 0 | | |
| SLICEM | 5605 | 0 | | | | SLICEM | 5618 | 0 | | |
| LUT as Logic | 38488 | 0 | 78600 | 48.97 | | LUT as Logic | 38565 | 0 | 78600 | 49.06 |
| using O5 output only | 4 | | | | | using O5 output only | 3 | | | |
| using O6 output only | 29940 | | | | | using O6 output only | 30027 | | | |
| using O5 and O6 | 8544 | | | | | using O5 and O6 | 8535 | | | |
| LUT as Memory | 3354 | 0 | 26600 | 12.61 | | LUT as Memory | 3386 | 0 | 26600 | 12.73 |
| LUT as Distributed RAM | 2802 | 0 | | | | LUT as Distributed RAM | 2850 | 0 | | |
| using O5 output only | 2 | | | | | using O5 output only | 2 | | | |
| using O6 output only | 84 | | | | | using O6 output only | 84 | | | |
| using O5 and O6 | 2716 | | | | | using O5 and O6 | 2764 | | | |
| LUT as Shift Register | 552 | 0 | | | | LUT as Shift Register | 536 | 0 | | |
| using O5 output only | 279 | | | | | using O5 output only | 263 | | | |
| using O6 output only | 221 | | | | | using O6 output only | 221 | | | |
| using O5 and O6 | 52 | | | | | using O5 and O6 | 52 | | | |
| LUT Flip Flop Pairs | 24240 | 0 | 78600 | 30.84 | | LUT Flip Flop Pairs | 24440 | 0 | 78600 | 31.09 |
| fully used LUT-FF pairs | 4483 | | | | | fully used LUT-FF pairs | 4610 | | | |
| LUT-FF pairs with one unused LUT output | 17581 | | | | | LUT-FF pairs with one unused LUT output | 17751 | | | |
| LUT-FF pairs with one unused Flip Flop | 17490 | | | | | LUT-FF pairs with one unused Flip Flop | 17508 | | | |
| Unique Control Sets | 4744 | | | | | Unique Control Sets | 4633 | | | |
+-------------------------------------------+-------+-------+-----------+-------+ +-------------------------------------------+-------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets. * Note: Review the Control Sets Report for more information regarding control sets.
...@@ -100,9 +100,9 @@ Table of Contents ...@@ -100,9 +100,9 @@ Table of Contents
+-------------------+------+-------+-----------+-------+ +-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% | | Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+ +-------------------+------+-------+-----------+-------+
| Block RAM Tile | 89 | 0 | 265 | 33.58 | | Block RAM Tile | 85 | 0 | 265 | 32.08 |
| RAMB36/FIFO* | 58 | 0 | 265 | 21.89 | | RAMB36/FIFO* | 54 | 0 | 265 | 20.38 |
| RAMB36E1 only | 58 | | | | | RAMB36E1 only | 54 | | | |
| RAMB18 | 62 | 0 | 530 | 11.70 | | RAMB18 | 62 | 0 | 530 | 11.70 |
| RAMB18E1 only | 62 | | | | | RAMB18E1 only | 62 | | | |
+-------------------+------+-------+-----------+-------+ +-------------------+------+-------+-----------+-------+
...@@ -136,19 +136,20 @@ Table of Contents ...@@ -136,19 +136,20 @@ Table of Contents
| PHASER_REF | 0 | 0 | 5 | 0.00 | | PHASER_REF | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 20 | 0.00 | | OUT_FIFO | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 20 | 0.00 | | IN_FIFO | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 1 | 0 | 5 | 20.00 | | IDELAYCTRL | 3 | 0 | 5 | 60.00 |
| IBUFDS | 2 | 2 | 155 | 1.29 | | IBUFDS | 2 | 2 | 155 | 1.29 |
| GTXE2_COMMON | 0 | 0 | 1 | 0.00 | | GTXE2_COMMON | 0 | 0 | 1 | 0.00 |
| GTXE2_CHANNEL | 1 | 1 | 4 | 25.00 | | GTXE2_CHANNEL | 1 | 1 | 4 | 25.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | | PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | | PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 18 | 18 | 250 | 7.20 | | IDELAYE2/IDELAYE2_FINEDELAY | 78 | 78 | 250 | 31.20 |
| IDELAYE2 only | 60 | 60 | | |
| IDELAYE2_FINEDELAY only | 18 | 18 | | | | IDELAYE2_FINEDELAY only | 18 | 18 | | |
| ODELAYE2/ODELAYE2_FINEDELAY | 43 | 43 | 150 | 28.67 | | ODELAYE2/ODELAYE2_FINEDELAY | 43 | 43 | 150 | 28.67 |
| ODELAYE2_FINEDELAY only | 43 | 43 | | | | ODELAYE2_FINEDELAY only | 43 | 43 | | |
| IBUFDS_GTE2 | 1 | 1 | 2 | 50.00 | | IBUFDS_GTE2 | 1 | 1 | 2 | 50.00 |
| ILOGIC | 16 | 16 | 163 | 9.82 | | ILOGIC | 72 | 72 | 163 | 44.17 |
| ISERDES | 16 | 16 | | | | ISERDES | 72 | 72 | | |
| OLOGIC | 48 | 48 | 163 | 29.45 | | OLOGIC | 48 | 48 | 163 | 29.45 |
| OUTFF_ODDR_Register | 5 | 5 | | | | OUTFF_ODDR_Register | 5 | 5 | | |
| OSERDES | 43 | 43 | | | | OSERDES | 43 | 43 | | |
...@@ -158,18 +159,18 @@ Table of Contents ...@@ -158,18 +159,18 @@ Table of Contents
6. Clocking 6. Clocking
----------- -----------
+--------------+------+-------+-----------+-------+ +--------------+------+-------+-----------+--------+
| Site Type | Used | Fixed | Available | Util% | | Site Type | Used | Fixed | Available | Util% |
+--------------+------+-------+-----------+-------+ +--------------+------+-------+-----------+--------+
| BUFGCTRL | 11 | 0 | 32 | 34.38 | | BUFGCTRL | 14 | 0 | 32 | 43.75 |
| BUFIO | 1 | 0 | 20 | 5.00 | | BUFIO | 3 | 0 | 20 | 15.00 |
| BUFIO only | 1 | 0 | | | | BUFIO only | 3 | 0 | | |
| MMCME2_ADV | 1 | 0 | 5 | 20.00 | | MMCME2_ADV | 5 | 0 | 5 | 100.00 |
| PLLE2_ADV | 2 | 0 | 5 | 40.00 | | PLLE2_ADV | 2 | 0 | 5 | 40.00 |
| BUFMRCE | 0 | 0 | 10 | 0.00 | | BUFMRCE | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 96 | 0.00 | | BUFHCE | 0 | 0 | 96 | 0.00 |
| BUFR | 4 | 0 | 20 | 20.00 | | BUFR | 6 | 0 | 20 | 30.00 |
+--------------+------+-------+-----------+-------+ +--------------+------+-------+-----------+--------+
7. Specific Feature 7. Specific Feature
...@@ -196,51 +197,52 @@ Table of Contents ...@@ -196,51 +197,52 @@ Table of Contents
+------------------------+-------+----------------------+ +------------------------+-------+----------------------+
| Ref Name | Used | Functional Category | | Ref Name | Used | Functional Category |
+------------------------+-------+----------------------+ +------------------------+-------+----------------------+
| FDRE | 52266 | Flop & Latch | | FDRE | 52563 | Flop & Latch |
| LUT3 | 11326 | LUT | | LUT3 | 11354 | LUT |
| LUT6 | 10159 | LUT | | LUT6 | 10387 | LUT |
| LUT2 | 8321 | LUT | | LUT2 | 8328 | LUT |
| LUT4 | 7915 | LUT | | LUT4 | 7774 | LUT |
| LUT5 | 7730 | LUT | | LUT5 | 7637 | LUT |
| RAMD32 | 4126 | Distributed Memory | | RAMD32 | 4198 | Distributed Memory |
| CARRY4 | 2725 | CarryLogic | | CARRY4 | 2809 | CarryLogic |
| LUT1 | 1581 | LUT | | LUT1 | 1620 | LUT |
| RAMS32 | 1392 | Distributed Memory | | RAMS32 | 1416 | Distributed Memory |
| FDSE | 965 | Flop & Latch | | FDSE | 953 | Flop & Latch |
| FDCE | 672 | Flop & Latch | | FDCE | 692 | Flop & Latch |
| SRL16E | 496 | Distributed Memory | | SRL16E | 484 | Distributed Memory |
| SRLC32E | 108 | Distributed Memory | | OBUFT | 121 | IO |
| SRLC32E | 104 | Distributed Memory |
| IBUF | 99 | IO | | IBUF | 99 | IO |
| OBUFT | 97 | IO |
| DSP48E1 | 76 | Block Arithmetic | | DSP48E1 | 76 | Block Arithmetic |
| ISERDESE2 | 72 | IO |
| RAMB18E1 | 62 | Block Memory | | RAMB18E1 | 62 | Block Memory |
| RAMB36E1 | 58 | Block Memory | | IDELAYE2 | 60 | IO |
| RAMB36E1 | 54 | Block Memory |
| OSERDESE2 | 43 | IO | | OSERDESE2 | 43 | IO |
| ODELAYE2_FINEDELAY | 43 | IO | | ODELAYE2_FINEDELAY | 43 | IO |
| MUXF7 | 30 | MuxFx | | MUXF7 | 30 | MuxFx |
| OBUFT_DCIEN | 18 | IO | | OBUFT_DCIEN | 18 | IO |
| IDELAYE2_FINEDELAY | 18 | IO | | IDELAYE2_FINEDELAY | 18 | IO |
| IBUF_IBUFDISABLE | 18 | IO | | IBUF_IBUFDISABLE | 18 | IO |
| ISERDESE2 | 16 | IO | | PULLUP | 16 | I/O |
| BUFG | 11 | Clock | | FDPE | 16 | Flop & Latch |
| PULLUP | 8 | I/O | | BUFG | 14 | Clock |
| FDPE | 8 | Flop & Latch | | BUFR | 6 | Clock |
| ODDR | 5 | IO | | ODDR | 5 | IO |
| MMCME2_ADV | 5 | Clock |
| OBUFTDS_DCIEN | 4 | IO | | OBUFTDS_DCIEN | 4 | IO |
| IBUFDS_IBUFDISABLE_INT | 4 | IO | | IBUFDS_IBUFDISABLE_INT | 4 | IO |
| BUFR | 4 | Clock |
| OBUF | 3 | IO | | OBUF | 3 | IO |
| INV | 3 | LUT | | INV | 3 | LUT |
| IDELAYCTRL | 3 | IO |
| BUFIO | 3 | Clock |
| PLLE2_ADV | 2 | Clock | | PLLE2_ADV | 2 | Clock |
| OBUFTDS | 2 | IO | | OBUFTDS | 2 | IO |
| IBUFDS | 2 | IO | | IBUFDS | 2 | IO |
| PS7 | 1 | Specialized Resource | | PS7 | 1 | Specialized Resource |
| MMCME2_ADV | 1 | Clock |
| IDELAYCTRL | 1 | IO |
| IBUFDS_GTE2 | 1 | IO | | IBUFDS_GTE2 | 1 | IO |
| GTXE2_CHANNEL | 1 | IO | | GTXE2_CHANNEL | 1 | IO |
| DCIRESET | 1 | Others | | DCIRESET | 1 | Others |
| BUFIO | 1 | Clock |
+------------------------+-------+----------------------+ +------------------------+-------+----------------------+
......
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