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Elphel
x393
Commits
12f27fa3
Commit
12f27fa3
authored
Oct 22, 2015
by
Andrey Filippov
Browse files
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Plain Diff
matched new and old histograms simulation
parent
cfdcac60
Changes
5
Hide whitespace changes
Inline
Side-by-side
Showing
5 changed files
with
178 additions
and
97 deletions
+178
-97
sens_histogram.v
sensor/sens_histogram.v
+1
-1
sens_histogram_snglclk.v
sensor/sens_histogram_snglclk.v
+78
-70
sensor_channel.v
sensor/sensor_channel.v
+1
-1
sensors393.v
sensor/sensors393.v
+1
-1
x393_testbench03.sav
x393_testbench03.sav
+97
-24
No files found.
sensor/sens_histogram.v
View file @
12f27fa3
...
...
@@ -24,7 +24,7 @@
// Alternative: copy/erase to a separate buffer in the beginning/end of a frame?
module
sens_histogram
#(
parameter
HISTOGRAM_RAM_MODE
=
"NOBUF"
,
// valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter
HISTOGRAM_RAM_MODE
=
"
BUF32"
,
// "
NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter
HISTOGRAM_ADDR
=
'h33c
,
parameter
HISTOGRAM_ADDR_MASK
=
'h7fe
,
parameter
HISTOGRAM_LEFT_TOP
=
'h0
,
...
...
sensor/sens_histogram_snglclk.v
View file @
12f27fa3
...
...
@@ -37,7 +37,7 @@ module sens_histogram_snglclk #(
input
mrst
,
// @posedge mclk, sync reset
input
prst
,
// @posedge pclk, sync reset
input
pclk
,
// global clock input, pixel rate (96MHz for MT9P006)
//
input pclk2x,
// input pclk2x,
input
sof
,
input
eof
,
input
hact
,
...
...
@@ -113,7 +113,8 @@ module sens_histogram_snglclk #(
reg
hist_out
;
// some data yet to be sent out
reg
hist_out_d
;
reg
[
2
:
0
]
hist_re
;
reg
[
1
:
0
]
hist_re_even_odd
;
reg
hist_re_even
;
reg
hist_re_odd
;
reg
[
9
:
0
]
hist_raddr
;
reg
hist_rq_r
;
wire
hist_xfer_done_mclk
;
//@ mclk
...
...
@@ -146,20 +147,6 @@ module sens_histogram_snglclk #(
if
(
sof
)
debug_lines
<=
debug_line_cntr
;
end
`endif
/*
always @ (posedge pclk) begin
if (!hact) pxd_wa <= 0;
else pxd_wa <= pxd_wa + 1;
if (!hact) pxd_wa_woi <= -PXD_2X_LATENCY;
else pxd_wa_woi <= pxd_wa_woi + 1;
if (hist_en_pclk && hact) pxd_ram[pxd_wa] <= hist_di;
if (hist_en_pclk && hact) bayer_ram[pxd_wa] <= bayer_pclk;
if (hist_en_pclk && hact_d[1]) woi_ram[pxd_wa_woi] <= hor_woi; // PXD_2X_LATENCY;
end
*/
always
@
(
posedge
mclk
)
begin
if
(
set_left_top_w
)
lt_mclk
<=
pio_data
;
...
...
@@ -210,7 +197,8 @@ module sens_histogram_snglclk #(
else
if
(
left_margin
||
hor_woi
[
0
])
hcntr
<=
hcntr
-
1
;
if
(
!
en
)
hist_bank_pclk
<=
0
;
else
if
(
hist_done
&&
(
HISTOGRAM_RAM_MODE
!=
"NOBUF"
))
hist_bank_pclk
<=
!
hist_bank_pclk
;
//else if (hist_done && (HISTOGRAM_RAM_MODE != "NOBUF")) hist_bank_pclk <= !hist_bank_pclk;// NOT applicable in this module
else
if
(
hist_done
)
hist_bank_pclk
<=
!
hist_bank_pclk
;
// hist_xfer_busy to extend en
if
(
!
en
)
hist_xfer_busy
<=
0
;
else
if
(
hist_xfer_done
)
hist_xfer_busy
<=
0
;
...
...
@@ -266,7 +254,7 @@ module sens_histogram_snglclk #(
wire
eq_prev_prev_d2
;
// eq_prev_prev delayed by 2 clocks to select r1 source
reg
eq_prev
;
// pixel equals previous of the same color
wire
eq_prev_d3
;
// eq_prev delayed by 3 clocks to select r1 source
wire
start_hor_woi
=
hcntr_zero_w
&&
left_margin
&&
vert_woi
;
//
wire start_hor_woi = hcntr_zero_w && left_margin && vert_woi;
// hist_di is 2 cycles ahead of hor_woi
...
...
@@ -339,14 +327,22 @@ module sens_histogram_snglclk #(
else
if
(
hist_grant
)
hist_re
[
0
]
<=
1
;
hist_re
[
2
:
1
]
<=
hist_re
[
1
:
0
]
;
// reg hist_re_even;
// reg hist_re_odd;
if
(
!
hist_out
||
(
&
hist_raddr
[
7
:
0
]))
hist_re_even
<=
0
;
else
if
(
hist_grant
&&
!
hist_re
[
0
])
hist_re_even
<=
!
hist_raddr
[
8
]
;
// reg [2:0] hist_re_even_odd;
if
(
!
hist_out
||
(
&
hist_raddr
[
7
:
1
]))
hist_re_even_odd
[
0
]
<=
0
;
else
if
(
hist_re
[
0
])
hist_re_even_odd
[
0
]
<=
~
hist_re_even_odd
[
0
]
;
else
if
(
hist_grant
)
hist_re_even_odd
[
0
]
<=
1
;
// hist_re[0] == 0 here
if
(
!
hist_out
||
(
&
hist_raddr
[
7
:
0
]))
hist_re_odd
<=
0
;
else
if
(
hist_grant
&&
!
hist_re
[
0
])
hist_re_odd
<=
hist_raddr
[
8
]
;
// if (!hist_out || (&hist_raddr[7:1])) hist_re_even_odd[0] <= 0;
// else if (hist_re[0]) hist_re_even_odd[0] <= ~hist_re_even_odd[0];
// else if (hist_grant) hist_re_even_odd[0] <= 1; // hist_re[0] == 0 here
if
(
!
en_mclk
)
hist_bank_mclk
<=
0
;
else
if
(
hist_xfer_done_mclk
&&
(
HISTOGRAM_RAM_MODE
!=
"NOBUF"
))
hist_bank_mclk
<=
!
hist_bank_mclk
;
// else if (hist_xfer_done_mclk && (HISTOGRAM_RAM_MODE != "NOBUF")) hist_bank_mclk <= !hist_bank_mclk; // Not applicable in this module
else
if
(
hist_xfer_done_mclk
)
hist_bank_mclk
<=
!
hist_bank_mclk
;
hist_dv
<=
hist_re
[
2
]
;
...
...
@@ -354,7 +350,7 @@ module sens_histogram_snglclk #(
always
@
(
posedge
pclk
)
begin
if
(
!
en
)
wait_readout
<=
0
;
else
if
((
HISTOGRAM_RAM_MODE
==
"NOBUF"
)
&&
hist_done
)
wait_readout
<=
1
;
// else if ((HISTOGRAM_RAM_MODE == "NOBUF") && hist_done) wait_readout <= 1; // Not applicable in this module
else
if
(
hist_xfer_done
)
wait_readout
<=
0
;
end
...
...
@@ -501,40 +497,42 @@ module sens_histogram_snglclk #(
if
((
HISTOGRAM_RAM_MODE
==
"BUF32"
)
||
(
HISTOGRAM_RAM_MODE
==
"NOBUF"
))
// impossible to use a two RAMB18E1 32-bit wide
sens_hist_ram_snglclk_32
sens_hist_ram_snglclk_32_i
(
.
pclk
(
pclk
)
,
// input
.
addr_a_even
(
{
hist_bank_pclk
,
hist_rwaddr_even
}
)
,
// input[9:0]
.
addr_a_odd
(
{
hist_bank_pclk
,
hist_rwaddr_odd
}
)
,
// input[9:0]
.
data_in_a
(
r2
)
,
// input[31:0]
.
data_out_a_even
(
hist_new_even
)
,
// output[31:0]
.
data_out_a_odd
(
hist_new_odd
)
,
// output[31:0]
.
en_a_even
(
rwen_even
)
,
// input
.
en_a_odd
(
rwen_odd
)
,
// input
.
regen_a_even
(
regen_even
)
,
// input
.
regen_a_odd
(
regen_odd
)
,
// input
.
we_a_even
(
we_even
)
,
// input
.
we_a_odd
(
we_odd
)
,
// input
.
mclk
(
mclk
)
,
// input
.
addr_b
(
{
hist_bank_mclk
,
hist_raddr
[
9
:
1
]
}
)
,
// input[9:0]
.
data_out_b
(
hist_do
)
,
// output[31:0] reg
.
re_b
(
hist_re_even_odd
[
0
])
// input
.
addr_a_even
(
{
hist_bank_pclk
,
hist_rwaddr_even
}
)
,
// input[9:0]
.
addr_a_odd
(
{
hist_bank_pclk
,
hist_rwaddr_odd
}
)
,
// input[9:0]
.
data_in_a
(
r2
)
,
// input[31:0]
.
data_out_a_even
(
hist_new_even
)
,
// output[31:0]
.
data_out_a_odd
(
hist_new_odd
)
,
// output[31:0]
.
en_a_even
(
rwen_even
)
,
// input
.
en_a_odd
(
rwen_odd
)
,
// input
.
regen_a_even
(
regen_even
)
,
// input
.
regen_a_odd
(
regen_odd
)
,
// input
.
we_a_even
(
we_even
)
,
// input
.
we_a_odd
(
we_odd
)
,
// input
.
mclk
(
mclk
)
,
// input
.
addr_b
(
{
hist_bank_mclk
,
hist_raddr
[
9
]
,
hist_raddr
[
7
:
0
]
}
)
,
// input[9:0]
.
data_out_b
(
hist_do
)
,
// output[31:0] reg
.
re_even
(
hist_re_even
)
,
// input
.
re_odd
(
hist_re_odd
)
// input
)
;
else
if
(
HISTOGRAM_RAM_MODE
==
"BUF18"
)
sens_hist_ram_snglclk_18
sens_hist_ram_snglclk_18_i
(
.
pclk
(
pclk
)
,
// input
.
addr_a_even
(
{
hist_bank_pclk
,
hist_rwaddr_even
}
)
,
// input[9:0]
.
addr_a_odd
(
{
hist_bank_pclk
,
hist_rwaddr_odd
}
)
,
// input[9:0]
.
data_in_a
(
r2
[
17
:
0
])
,
// input[31:0]
.
data_out_a_even
(
hist_new_even
[
17
:
0
])
,
// output[31:0]
.
data_out_a_odd
(
hist_new_odd
[
17
:
0
])
,
// output[31:0]
.
en_a_even
(
rwen_even
)
,
// input
.
en_a_odd
(
rwen_odd
)
,
// input
.
regen_a_even
(
regen_even
)
,
// input
.
regen_a_odd
(
regen_odd
)
,
// input
.
we_a_even
(
we_even
)
,
// input
.
we_a_odd
(
we_odd
)
,
// input
.
mclk
(
mclk
)
,
// input
.
addr_b
(
{
hist_bank_mclk
,
hist_raddr
[
9
:
1
]
}
)
,
// input[9:0]
.
data_out_b
(
hist_do
)
,
// output[31:0] reg
.
re_b
(
hist_re_even_odd
[
0
])
// input
.
addr_a_even
(
{
hist_bank_pclk
,
hist_rwaddr_even
}
)
,
// input[9:0]
.
addr_a_odd
(
{
hist_bank_pclk
,
hist_rwaddr_odd
}
)
,
// input[9:0]
.
data_in_a
(
r2
[
17
:
0
])
,
// input[31:0]
.
data_out_a_even
(
hist_new_even
[
17
:
0
])
,
// output[31:0]
.
data_out_a_odd
(
hist_new_odd
[
17
:
0
])
,
// output[31:0]
.
en_a_even
(
rwen_even
)
,
// input
.
en_a_odd
(
rwen_odd
)
,
// input
.
regen_a_even
(
regen_even
)
,
// input
.
regen_a_odd
(
regen_odd
)
,
// input
.
we_a_even
(
we_even
)
,
// input
.
we_a_odd
(
we_odd
)
,
// input
.
mclk
(
mclk
)
,
// input
.
addr_b
(
{
hist_bank_mclk
,
hist_raddr
[
9
]
,
hist_raddr
[
7
:
0
]
}
)
,
// input[9:0]
.
data_out_b
(
hist_do
)
,
// output[31:0] reg
.
re_even
(
hist_re_even
)
,
// input
.
re_odd
(
hist_re_odd
)
// input
)
;
endgenerate
...
...
@@ -559,14 +557,19 @@ module sens_hist_ram_snglclk_32(
input
mclk
,
input
[
9
:
0
]
addr_b
,
output
reg
[
31
:
0
]
data_out_b
,
input
re_b
input
re_even
,
input
re_odd
)
;
reg
[
1
:
0
]
re_b_r
;
reg
re_even_d
;
reg
re_odd_d
;
reg
odd
;
wire
[
31
:
0
]
data_out_b_w_even
;
wire
[
31
:
0
]
data_out_b_w_odd
;
always
@
(
posedge
mclk
)
begin
re_b_r
<=
{
re_b_r
[
0
]
,
re_b
};
data_out_b
<=
re_b_r
[
1
]
?
data_out_b_w_even
:
data_out_b_w_odd
;
re_even_d
<=
re_even
;
re_odd_d
<=
re_odd
;
odd
<=
re_odd
;
data_out_b
<=
odd
?
data_out_b_w_odd
:
data_out_b_w_even
;
end
ramt_var_w_var_r
#(
...
...
@@ -586,8 +589,8 @@ module sens_hist_ram_snglclk_32(
.
data_in_a
(
data_in_a
)
,
// input[15:0]
.
clk_b
(
mclk
)
,
// input
.
addr_b
(
addr_b
)
,
// input[10:0]
.
en_b
(
re_
b
)
,
// input FIXME: read (and write!) only when needed odd/even
.
regen_b
(
re_
b_r
[
0
])
,
// input FIXME: read only when needed odd/even
.
en_b
(
re_
even
)
,
// input
.
regen_b
(
re_
even_d
)
,
// input
.
we_b
(
1'b1
)
,
// input
.
data_out_b
(
data_out_b_w_even
)
,
// output[15:0]
.
data_in_b
(
32'b0
)
// input[15:0]
...
...
@@ -610,8 +613,8 @@ module sens_hist_ram_snglclk_32(
.
data_in_a
(
data_in_a
)
,
// input[15:0]
.
clk_b
(
mclk
)
,
// input
.
addr_b
(
addr_b
)
,
// input[10:0]
.
en_b
(
re_
b_r
[
0
])
,
// input
.
regen_b
(
re_
b_r
[
1
])
,
// input
.
en_b
(
re_
odd
)
,
// input
.
regen_b
(
re_
odd_d
)
,
// input
.
we_b
(
1'b1
)
,
// input
.
data_out_b
(
data_out_b_w_odd
)
,
// output[15:0]
.
data_in_b
(
32'b0
)
// input[15:0]
...
...
@@ -637,14 +640,19 @@ module sens_hist_ram_snglclk_18(
input
mclk
,
input
[
9
:
0
]
addr_b
,
output
reg
[
31
:
0
]
data_out_b
,
input
re_b
input
re_even
,
input
re_odd
)
;
reg
[
1
:
0
]
re_b_r
;
reg
re_even_d
;
reg
re_odd_d
;
reg
odd
;
wire
[
17
:
0
]
data_out_b_w_even
;
wire
[
17
:
0
]
data_out_b_w_odd
;
always
@
(
posedge
mclk
)
begin
re_b_r
<=
{
re_b_r
[
0
]
,
re_b
};
data_out_b
<=
{
14'b0
,
(
re_b_r
[
1
]
?
data_out_b_w_even
:
data_out_b_w_odd
)
};
re_even_d
<=
re_even
;
re_odd_d
<=
re_odd
;
odd
<=
re_odd
;
data_out_b
<=
{
14'b0
,
(
odd
?
data_out_b_w_odd
:
data_out_b_w_even
)
};
end
ram18tp_var_w_var_r
#(
...
...
@@ -664,8 +672,8 @@ module sens_hist_ram_snglclk_18(
.
data_in_a
(
data_in_a
)
,
// input[15:0]
.
clk_b
(
mclk
)
,
// input
.
addr_b
(
addr_b
)
,
// input[10:0]
.
en_b
(
re_
b
)
,
// input
.
regen_b
(
re_
b_r
[
0
]
)
,
// input
.
en_b
(
re_
even
)
,
// input
.
regen_b
(
re_
even_d
)
,
// input
.
we_b
(
1'b1
)
,
// input
.
data_out_b
(
data_out_b_w_even
)
,
// output[15:0]
.
data_in_b
(
18'b0
)
// input[15:0]
...
...
@@ -688,8 +696,8 @@ module sens_hist_ram_snglclk_18(
.
data_in_a
(
data_in_a
)
,
// input[15:0]
.
clk_b
(
mclk
)
,
// input
.
addr_b
(
addr_b
)
,
// input[10:0]
.
en_b
(
re_
b_r
[
0
])
,
// input
.
regen_b
(
re_
b_r
[
1
])
,
// input
.
en_b
(
re_
odd
)
,
// input
.
regen_b
(
re_
odd_d
)
,
// input
.
we_b
(
1'b1
)
,
// input
.
data_out_b
(
data_out_b_w_odd
)
,
// output[15:0]
.
data_in_b
(
18'b0
)
// input[15:0]
...
...
sensor/sensor_channel.v
View file @
12f27fa3
...
...
@@ -43,7 +43,7 @@ module sensor_channel#(
parameter
SENSOR_NUM_HISTOGRAM
=
3
,
// number of histogram channels
parameter
HISTOGRAM_RAM_MODE
=
"NOBUF"
,
// valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter
HISTOGRAM_RAM_MODE
=
"
BUF32"
,
// "
NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter
SENS_NUM_SUBCHN
=
3
,
// number of subchannels for his sensor ports (1..4)
parameter
SENS_GAMMA_BUFFER
=
0
,
// 1 - use "shadow" table for clean switching, 0 - single table per channel
...
...
sensor/sensors393.v
View file @
12f27fa3
...
...
@@ -35,7 +35,7 @@ module sensors393 #(
parameter
SENSI2C_STATUS_REG_REL
=
0
,
// 4 locations" 'h20, 'h22, 'h24, 'h26
parameter
SENSIO_STATUS_REG_REL
=
1
,
// 4 locations" 'h21, 'h23, 'h25, 'h27
parameter
SENSOR_NUM_HISTOGRAM
=
3
,
// number of histogram channels
parameter
HISTOGRAM_RAM_MODE
=
"NOBUF"
,
// valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter
HISTOGRAM_RAM_MODE
=
"
BUF32"
,
// "
NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter
SENS_NUM_SUBCHN
=
3
,
// number of subchannels for his sensor ports (1..4)
parameter
SENS_GAMMA_BUFFER
=
0
,
// 1 - use "shadow" table for clean switching, 0 - single table per channel
...
...
x393_testbench03.sav
View file @
12f27fa3
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Thu Oct 22
02:28:16
2015
[*] Thu Oct 22
19:01:31
2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-2015102
1192628858
.fst"
[dumpfile_mtime] "Thu Oct 22
01:43:50
2015"
[dumpfile_size]
66340427
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-2015102
2091046904
.fst"
[dumpfile_mtime] "Thu Oct 22
15:49:46
2015"
[dumpfile_size]
277840396
[savefile] "/home/andrey/git/x393/x393_testbench03.sav"
[timestart]
7506883
0
[timestart]
3184000
0
[size] 1823 1180
[pos] 1917 0
*-
14.020046 7511583
0 178682388 184032388 75106570 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-
24.043108 7574730
0 178682388 184032388 75106570 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].
...
...
@@ -28,8 +28,8 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.
...
...
@@ -41,6 +41,8 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
...
...
@@ -49,7 +51,7 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
[sst_width] 4
37
[sst_width] 4
41
[signals_width] 322
[sst_expanded] 1
[sst_vpaned_height] 670
...
...
@@ -72,7 +74,7 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.ipclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sns_mrst
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.rst_mmcm
@
8
00200
@
c
00200
-sens_hispi12l4
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sns_mrst
...
...
@@ -621,12 +623,13 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_lane_i.zero_after_ones_w
@1000200
-sens_hispi_lane0
@1401200
-sens_hispi12l4
@200
-
@1000200
-sens_10398
@
8
00200
@
c
00200
-sensor_channel_0
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.mclk
...
...
@@ -905,6 +908,7 @@ x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i
-
@1000200
-mcntr_linear_rw_sensor0
@1401200
-sensor_channel_0
@800200
-DDR3
...
...
@@ -1628,7 +1632,6 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_re[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_re_even_odd[1:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rq
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rq_r
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rst
...
...
@@ -1636,7 +1639,7 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_xfer_busy
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_xfer_done
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_xfer_done_mclk
@
8
00022
@
c
00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
...
...
@@ -1646,7 +1649,7 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
(4)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
(5)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
@1
0
01200
@1
4
01200
-group_end
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.left[15:0]
...
...
@@ -1657,7 +1660,7 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.lt_mclk[31:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.mclk
@
8
00022
@
c
00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
...
...
@@ -1667,9 +1670,9 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
(4)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
(5)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
@1
0
01200
@1
4
01200
-group_end
@
8
00022
@
c
00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
...
...
@@ -1679,7 +1682,7 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
(4)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
(5)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
@1
0
01200
@1
4
01200
-group_end
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.mrst
...
...
@@ -1694,13 +1697,11 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.prst
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_di[7:0]
@23
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.px_d0[7:0]
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.px_d2[7:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.px_d4[7:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.px_d5[7:0]
@
8
00022
@
c
00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
...
...
@@ -1712,7 +1713,7 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
(7)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
(8)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
@1
0
01200
@1
4
01200
-group_end
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_odd[8:0]
...
...
@@ -1759,18 +1760,86 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.vcntr_zero_w
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.vert_woi
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.wait_readout
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_odd[8:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.r2[31:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.we_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.we_odd
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.wh_mclk[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.width_m1[15:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.eq_prev_d3
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.eq_prev_prev_d2
@200
-
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_bank_pclk
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.addr_a_even[9:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.en_a_even
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.addr_a_odd[9:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.en_a_odd
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.regen_a_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.regen_a_odd
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.we_a_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.we_a_odd
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.data_out_a_even[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.data_out_a_odd[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.data_in_a[31:0]
@200
-
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_out
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_re[2:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_re[2:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_re[2:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_re[2:0]
@1401200
-group_end
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
(4)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
(5)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
(7)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
(8)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
(9)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
@1401200
-group_end
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rq
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_grant
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_do[31:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_dv
@1000200
-sens_hist_sngl0
@800200
-histogram_chn0
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_bank_pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pclk2x
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.inc_sat[31:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_we
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rwaddr[9:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_di[7:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.left[15:0]
@28
...
...
@@ -1796,23 +1865,27 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.ge
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
@29
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.bayer_pclk[1:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.mclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_out
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rq
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_grant
@
800028
@
c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@1
001200
@1
401202
-group_end
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_raddr[9:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_dv
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_out
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
@1001200
-group_end
@1000200
...
...
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