Skip to content

X
x393
Commit 0fda102e authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

Fixed ddr3 -> system memory transfer

parent 59a577c9
Hide whitespace changes
Inline Side-by-side
Showing with 268 additions and 75 deletions
.project
View file @ 0fda102e
......@@ -62,77 +62,77 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150503212342992.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150504180408074.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150503212342992.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150504180408074.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150503212342992.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150504180408074.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150503212342992.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150504180408074.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150503212342992.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150504180408074.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150503212342992.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150504180408074.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150503212133457.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150504180215142.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150503212342992.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150504180408074.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150503212133457.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150504180215142.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150503212342992.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150504180408074.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150503212133457.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150504180215142.log</location>
</link>
<link>
<name>vivado_state/x393-opt-phys.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150503212342992.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150504180408074.dcp</location>
</link>
<link>
<name>vivado_state/x393-place.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150503212342992.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150504180408074.dcp</location>
</link>
<link>
<name>vivado_state/x393-route.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150503212342992.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150504180408074.dcp</location>
</link>
<link>
<name>vivado_state/x393-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150503212133457.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150504180215142.dcp</location>
</link>
</linkedResources>
</projectDescription>
axi/membridge.v
View file @ 0fda102e
......@@ -19,7 +19,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
//`define MEMBRIDGE_DEBUG_READ 1
module membridge#(
parameter MEMBRIDGE_ADDR= 'h200,
parameter MEMBRIDGE_MASK= 'h3f0,
......@@ -164,10 +164,28 @@ module membridge#(
reg [28:0] size64_mclk;
reg [28:0] start64_mclk;
reg [28:0] len64_mclk;
reg [FRAME_WIDTH_BITS+1:0] width64_mclk; // FRAME_WIDTH_BITS in 128 bit bursts
// reg [FRAME_WIDTH_BITS+1:0] width64_mclk; // FRAME_WIDTH_BITS in 128 bit bursts
reg [FRAME_WIDTH_BITS:0] width64_mclk; // FRAME_WIDTH_BITS in 128 bit bursts
reg [FRAME_WIDTH_BITS:0] width64_minus1_mclk; // FRAME_WIDTH_BITS in 128 bit bursts
reg rdwr_en_mclk;
reg rdwr_reset_addr_mclk; // resets system memory address
reg start_mclk;
`ifdef MEMBRIDGE_DEBUG_READ
reg debug_aw_mclk; // enable sending next address over AFI
reg debug_w_mclk; // enable sending next data burst over AFI
wire debug_aw; // enable sending next address over AFI, sync to hclk
wire debug_w; // enable sending next data burst over AFI, sync to hclk
reg [6:0] debug_aw_allowed;
reg [8:0] debug_w_allowed;
reg [4:0] debug_bufrd_rd;
reg debug_disable_set_mclk; // disable debug slowdown
wire debug_disable_set; // disable debug slowdown
reg debug_disable; // disable debug slowdown
wire debug_aw_ready;
wire debug_w_ready;
assign debug_aw_ready = (!debug_aw_allowed[6] && (|debug_aw_allowed[5:0])) || debug_disable; // > 0
assign debug_w_ready = (!debug_w_allowed[8] && (|debug_w_allowed [7:0]) &&((|debug_w_allowed [7:1]) || !(|debug_bufrd_rd))) || debug_disable; // > 0
`endif
//cmd_wrmem
always @ (posedge mclk) begin
if (set_lo_addr64_w) lo_addr64_mclk <= {cmd_data[28:4],4'b0}; // align to 16-bursts
......@@ -175,9 +193,10 @@ module membridge#(
if (set_lo_addr64_w) start64_mclk <= 0;
else if (set_start64_w) start64_mclk <= {cmd_data[28:4],4'b0}; // align to 16-bursts
if (set_len64_w) len64_mclk <= cmd_data[28:0]; // OK not to be aligned
if (set_width64_w) width64_mclk <= {~(|cmd_data[FRAME_WIDTH_BITS:0]),cmd_data[FRAME_WIDTH_BITS:0]}; // OK not to be aligned
// if (set_width64_w) width64_mclk <= {~(|cmd_data[FRAME_WIDTH_BITS:0]),cmd_data[FRAME_WIDTH_BITS:0]}; // OK not to be aligned
if (set_width64_w) width64_mclk <= cmd_data[FRAME_WIDTH_BITS:0]; // OK not to be aligned
if (set_ctrl_w) rdwr_reset_addr_mclk <= cmd_data[1] && !cmd_data[2];
width64_minus1_mclk <= width64_mclk-1;
end
always @ (posedge mclk or posedge rst) begin
......@@ -186,6 +205,16 @@ module membridge#(
if (rst) start_mclk <= 0;
else start_mclk <= set_ctrl_w & cmd_data[1];
`ifdef MEMBRIDGE_DEBUG_READ
if (rst) debug_aw_mclk <= 0;
else debug_aw_mclk <= set_ctrl_w & cmd_data[2];
if (rst) debug_w_mclk <= 0;
else debug_w_mclk <= set_ctrl_w & cmd_data[3];
if (rst) debug_disable_set_mclk <= 0;
else debug_disable_set_mclk <= set_ctrl_w & cmd_data[4];
`endif
end
......@@ -236,7 +265,8 @@ module membridge#(
start64 <= start64_mclk;
len64 <= len64_mclk;
// width64 <= width64_mclk;
last_in_line64 <= width64_mclk[FRAME_WIDTH_BITS:0]-1;
last_in_line64 <= width64_minus1_mclk;
// last_in_line64 <= width64_mclk[FRAME_WIDTH_BITS:0]-1;
wr_mode <= cmd_wrmem;
rdwr_reset_addr <= rdwr_reset_addr_mclk;
last_addr1k <= size64[28:4] - 1;
......@@ -270,6 +300,13 @@ module membridge#(
pulse_cross_clock page_ready_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(page_ready_chn), .out_pulse(page_ready),.busy());
pulse_cross_clock frame_done_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(frame_done_chn), .out_pulse(frame_done),.busy());
pulse_cross_clock reset_page_wr_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(xfer_reset_page_wr), .out_pulse(reset_page_wr),.busy());
`ifdef MEMBRIDGE_DEBUG_READ
// mclk -> hclk, debug-only
pulse_cross_clock debug_aw_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(debug_aw_mclk), .out_pulse(debug_aw),.busy());
pulse_cross_clock debug_w_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(debug_w_mclk), .out_pulse(debug_w), .busy());
pulse_cross_clock debug_disable_set_i(.rst(rst),.src_clk(mclk),.dst_clk(hclk), .in_pulse(debug_disable_set_mclk),.out_pulse(debug_disable_set), .busy());
`endif
// negedge mclk -> hclk (verify clock inversion is absorbed)
pulse_cross_clock reset_page_rd_i (.rst(rst), .src_clk(~mclk),.dst_clk(hclk), .in_pulse(xfer_reset_page_rd), .out_pulse(reset_page_rd),.busy());
......@@ -377,17 +414,43 @@ module membridge#(
reg afi_wa_safe_not_full;
assign advance_rel_addr_w = advance_rel_addr_wr || advance_rel_addr_rd;
assign advance_rel_addr_wr = read_started && afi_wa_safe_not_full && (|left64); // left 64 is decremented by 16, except possibly the last (partial)
// assign advance_rel_addr_wr = read_started && afi_wa_safe_not_full && (|left64); // left 64 is decremented by 16, except possibly the last (partial)
`ifdef MEMBRIDGE_DEBUG_READ
assign advance_rel_addr_wr = read_started && afi_wa_safe_not_full && (|left64) && debug_aw_ready; // debugging ddr3 -> system
`else
assign advance_rel_addr_wr = read_started && afi_wa_safe_not_full && (|left64);
`endif
assign afi_awvalid=advance_rel_addr && read_started;
always @ (posedge hclk or posedge rst) begin
if (rst) read_busy <= 0;
else if (rd_start) read_busy <= 1;
else if (read_over) read_busy <= 0;
if (rst) read_started <= 0;
else if (!read_busy) read_started <= 0;
else if (wr_mode) read_started <= 0; // just debugging, making sure read is disabled in write mode
else if (page_ready) read_started <= 1; // first page is in the buffer - use it to mask page number comparison
`ifdef MEMBRIDGE_DEBUG_READ
if (rst) debug_aw_allowed <= 0;
else if (!read_busy) debug_aw_allowed <= 0;
else if ( debug_aw && !afi_awvalid) debug_aw_allowed <= debug_aw_allowed + 1;
else if (!debug_aw && afi_awvalid) debug_aw_allowed <= debug_aw_allowed - 1;
if (rst) debug_w_allowed <= 0;
else if (!read_busy) debug_w_allowed <= 0;
else if ( debug_w && !(afi_wvalid && afi_wlast)) debug_w_allowed <= debug_w_allowed + 1;
else if (!debug_w && (afi_wvalid && afi_wlast)) debug_w_allowed <= debug_w_allowed - 1;
if (rst) debug_disable <= 0;
else if (!read_busy) debug_disable <= 0;
else if (debug_disable_set) debug_disable <= 1;
`endif
afi_bvalid_r <=afi_bvalid;
......@@ -396,6 +459,8 @@ module membridge#(
else if (afi_bvalid_r) wresp_conf <= wresp_conf +1;
read_over <= left_zero && (axi_wr_pending == 0) && read_started;
// read_over <= ((left_zero && (axi_wr_pending == 0)) || frame_done) && read_started ; // WRONG, just for debugging
// else if (frame_done) read_busy <= 0;
if (rst) read_page <= 0;
else if (reset_page_rd) read_page <= 0;
......@@ -436,14 +501,22 @@ module membridge#(
assign next_page_rd_w = read_started && !busy_next_page && is_last_in_page && bufrd_rd[0];
assign is_last_in_line = buf_in_line64 == last_in_line64;
assign is_last_in_page = is_last_in_line || (&buf_in_line64[6:0]);
`ifdef MEMBRIDGE_DEBUG_READ
assign bufrd_rd_w = afi_wd_safe_not_full && (|read_pages_ready[2:1] || (read_pages_ready[0] && !is_last_in_page)) && debug_w_ready;
`else
assign bufrd_rd_w = afi_wd_safe_not_full && (|read_pages_ready[2:1] || (read_pages_ready[0] && !is_last_in_page));
`endif
//last_in_line64 - last word number in scan line
reg left_was_1; // was 1 or 0 (0 does not matter)
reg left_was_1; // was <=1 (0 does not matter) valid next after buffer address
reg [3:0] src_wcntr;
reg [2:0] wlast_in_burst;
// reg [2:0] wlast_in_burst;
reg wlast; // valid 2 after buffer address, same as wvalid
assign afi_wlast = wlast_in_burst[2];
reg src_was_f; // valid next after buffer address
// assign afi_wlast = wlast_in_burst[2];
assign afi_wlast = wlast;
always @ (posedge hclk) begin
if (!rw_in_progress) left_was_1 <= 0;
else if (buf_rdwr) left_was_1 <= !(|buf_left64[28:1]);
......@@ -451,10 +524,20 @@ module membridge#(
if (!read_started) src_wcntr <= 0;
else if (bufrd_rd[0]) src_wcntr <= src_wcntr+1;
if (!read_started) wlast_in_burst <= 0;
else if (bufrd_rd[0]) wlast_in_burst <= {wlast_in_burst[1:0],left_was_1 | (&src_wcntr)};
if (!read_started) src_was_f <= 0;
else if (bufrd_rd[0]) src_was_f <= &src_wcntr; // valid with buffer address
// if (!read_started) wlast_in_burst <= 0;
// else if (bufrd_rd[0]) wlast_in_burst <= {wlast_in_burst[1:0],left_was_1 | (&src_wcntr)};
if (!read_started) wlast <= 0;
else if (bufrd_rd[1]) wlast <= left_was_1 || src_was_f;
bufrd_rd <= {bufrd_rd[1:0], bufrd_rd_w };
`ifdef MEMBRIDGE_DEBUG_READ
debug_bufrd_rd<= {debug_bufrd_rd[3:0], bufrd_rd_w };
`endif
buf_rdwr <= bufrd_rd_w || bufwr_we_w;
bufwr_we <= {bufwr_we[0],bufwr_we_w};
......@@ -484,6 +567,7 @@ module membridge#(
always @ (posedge hclk or posedge rst) begin
if (rst) write_busy <= 0;
else if (wr_start) write_busy <= 1;
else if (!wr_mode) write_busy <= 0; // Just debugging, making sure write mode is disabled in read mode
else if (frame_done) write_busy <= 0;
if (rst) axi_arw_requested <= 0;
......@@ -543,13 +627,21 @@ module membridge#(
status_generate #(
.STATUS_REG_ADDR (MEMBRIDGE_STATUS_REG),
.PAYLOAD_BITS (2) // ???
`ifdef MEMBRIDGE_DEBUG_READ
.PAYLOAD_BITS (18) // 2) // With debug
`else
.PAYLOAD_BITS (2)
`endif
) status_generate_i (
.rst (rst), // input
.clk (mclk), // input
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
.wd (cmd_data[7:0]), // input[7:0]
`ifdef MEMBRIDGE_DEBUG_READ
.status ({debug_aw_allowed, debug_w_allowed, done, busy}), // input[25:0]
`else
.status ({done,busy}), // input[25:0]
`endif
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
......
includes/x393_localparams.vh
View file @ 0fda102e
......@@ -119,8 +119,12 @@
localparam FRAME_START_ADDRESS= 'h1000; // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
localparam FRAME_FULL_WIDTH= 'h0c0; // Padded line length (8-row increment), in 8-bursts (16 bytes)
localparam AFI_LO_ADDR64= 'h4000; // start of the system memory range in 64-bit words
localparam AFI_SIZE64= 'h4000; // size of system memory range in 64-bit words
// localparam AFI_LO_ADDR64= 'h4000; // start of the system memory range in 64-bit words
// localparam AFI_SIZE64= 'h4000; // size of system memory range in 64-bit words
// Same as in the actual hardware
localparam AFI_LO_ADDR64= 'h4f20000; // start of the system memory range in 64-bit words
localparam AFI_SIZE64= 'h0c80000; // size of system memory range in 64-bit words
// localparam SCANLINE_WINDOW_WH= `h079000a2; // 2592*1936: low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
......
py393/x393_axi_control_status.py
View file @ 0fda102e
......@@ -355,7 +355,7 @@ class X393AxiControlStatus(object):
"""
global mcntrl_en
en=(0,1)[en]
if self.verbose > -10: # 0:
if self.verbose > 0:
print ("ENABLE MEMCTRL %s"%str(en))
self.write_contol_register(vrlg.MCONTR_TOP_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_MCONTR_EN + en, 0);
mcntrl_en=en
......@@ -368,7 +368,7 @@ class X393AxiControlStatus(object):
global enabled_channels
enabled_channels = chnen # currently enabled memory channels
self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,chnen});
if self.verbose > -10: # 0:
if self.verbose > 0:
print ("ENABLED MEMCTRL CHANNELS 0x%x (word), chnen=0x%x"%(enabled_channels,chnen))
def enable_memcntrl_en_dis(self,
......@@ -385,7 +385,7 @@ class X393AxiControlStatus(object):
else:
enabled_channels &= ~(1<<chn);
self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,ENABLED_CHANNELS});
if self.verbose > -10: #0:
if self.verbose > 0:
print ("ENABLED MEMCTRL CHANNELS 0x%x (en/dis)"%enabled_channels)
def configure_channel_priority(self,
......@@ -398,7 +398,7 @@ class X393AxiControlStatus(object):
"""
global channel_priority
self.write_contol_register(vrlg.MCONTR_ARBIT_ADDR + chn, priority & 0xffff)# {16'b0,priority});
if self.verbose > -1: # 0:
if self.verbose > 0:
print ("SET CHANNEL %d priority=0x%x"%(chn,priority))
channel_priority[chn]=priority
system_defines.vh
View file @ 0fda102e
// This file may be used to define same pre-processor macros to be included into each parsed file
`ifndef SYSTEM_DEFINES
`define SYSTEM_DEFINES
//`define MEMBRIDGE_DEBUG_READ 1
`define use200Mhz 1
`define USE_CMD_ENCOD_TILED_32_RD 1
// It can be used to check different `ifdef branches
......
x393_testbench01.sav
View file @ 0fda102e
[*]
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
[*] Mon May 4 03:20:08 2015
[*] Mon May 4 23:59:20 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150503211205371.lxt"
[dumpfile_mtime] "Mon May 4 03:17:38 2015"
[dumpfile_size] 274999726
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150504175355196.lxt"
[dumpfile_mtime] "Mon May 4 23:58:48 2015"
[dumpfile_size] 264023680
[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
[timestart] 41895630
[timestart] 50540000
[size] 1823 1180
[pos] 1919 0
*-13.063198 41917667 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-20.063198 54490000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01.
[treeopen] x393_testbench01.ddr3_i.
[treeopen] x393_testbench01.simul_axi_hp_wr_i.
......@@ -18,7 +18,7 @@
[sst_width] 202
[signals_width] 547
[sst_expanded] 1
[sst_vpaned_height] 644
[sst_vpaned_height] 775
@800200
-DDR3
@28
......@@ -39,25 +39,6 @@ x393_testbench01.SDD[15:0]
@1000200
-DDR3
@800200
-DDR3
@28
x393_testbench01.SDRST[0]
x393_testbench01.SDCLK[0]
@22
x393_testbench01.SDBA[2:0]
x393_testbench01.SDA[14:0]
@28
x393_testbench01.SDRAS[0]
x393_testbench01.SDCAS[0]
x393_testbench01.SDWE[0]
x393_testbench01.SDODT[0]
x393_testbench01.DQSL[0]
x393_testbench01.DQSU[0]
@22
x393_testbench01.SDD[15:0]
@1000200
-DDR3
@800200
-top
@28
x393_testbench01.RST[0]
......@@ -78,7 +59,7 @@ x393_testbench01.PS_REG_DOUT[31:0]
x393_testbench01.PS_RDATA[31:0]
@1000200
-PS
@c00200
@800200
-simul_afi_wr
@28
x393_testbench01.simul_axi_hp_wr_i.WrCmdReleaseMode[1:0]
......@@ -198,9 +179,9 @@ x393_testbench01.simul_axi_hp_wr_i.wstrb[7:0]
x393_testbench01.simul_axi_hp_wr_i.wstrb_out[7:0]
@28
x393_testbench01.simul_axi_hp_wr_i.wvalid[0]
@1401200
@1000200
-simul_afi_wr
@800200
@c00200
-simul_afi_rd
@28
x393_testbench01.simul_axi_hp_rd_i.aclk[0]
......@@ -289,12 +270,12 @@ x393_testbench01.simul_axi_hp_rd_i.sim_rd_data[63:0]
x393_testbench01.simul_axi_hp_rd_i.sim_rd_qos[3:0]
@28
x393_testbench01.simul_axi_hp_rd_i.sim_rd_ready[0]
@c00029
@c00028
x393_testbench01.simul_axi_hp_rd_i.sim_rd_resp[1:0]
@29
@28
(0)x393_testbench01.simul_axi_hp_rd_i.sim_rd_resp[1:0]
(1)x393_testbench01.simul_axi_hp_rd_i.sim_rd_resp[1:0]
@1401201
@1401200
-group_end
@28
x393_testbench01.simul_axi_hp_rd_i.sim_rd_valid[0]
......@@ -305,10 +286,33 @@ x393_testbench01.simul_axi_hp_rd_i.start_read_burst_w[0]
x393_testbench01.simul_axi_hp_rd_i.was_addr_fifo_write[0]
x393_testbench01.simul_axi_hp_rd_i.was_data_fifo_read[0]
x393_testbench01.simul_axi_hp_rd_i.was_data_fifo_write[0]
@1000200
@1401200
-simul_afi_rd
@800200
-membridge
@200
-
@22
x393_testbench01.x393_i.membridge_i.afi_awaddr[31:0]
x393_testbench01.x393_i.membridge_i.afi_awlen[3:0]
@28
x393_testbench01.x393_i.membridge_i.afi_awvalid[0]
x393_testbench01.x393_i.membridge_i.afi_wlast[0]
x393_testbench01.x393_i.membridge_i.afi_wvalid[0]
@200
-
@28
x393_testbench01.x393_i.membridge_i.read_over[0]
x393_testbench01.x393_i.membridge_i.read_started[0]
x393_testbench01.x393_i.membridge_i.left_zero[0]
@22
x393_testbench01.x393_i.membridge_i.axi_arw_requested[7:0]
x393_testbench01.x393_i.membridge_i.wresp_conf[7:0]
x393_testbench01.x393_i.membridge_i.axi_wr_pending[7:0]
@28
x393_testbench01.x393_i.membridge_i.read_busy[0]
@200
-
@22
x393_testbench01.x393_i.membridge_i.afi_arlen[3:0]
@28
......@@ -619,7 +623,6 @@ x393_testbench01.x393_i.membridge_i.status_rq[0]
x393_testbench01.x393_i.membridge_i.status_start[0]
x393_testbench01.x393_i.membridge_i.suspend_chn1[0]
@22
x393_testbench01.x393_i.membridge_i.width64_mclk[14:0]
x393_testbench01.x393_i.membridge_i.wr_id[4:0]
@28
x393_testbench01.x393_i.membridge_i.wr_mode[0]
......@@ -637,6 +640,85 @@ x393_testbench01.x393_i.membridge_i.xfer_reset_page_rd[0]
x393_testbench01.x393_i.membridge_i.xfer_reset_page_wr[0]
@1000200
-membridge
@200
-
@800200
-SAXIHP0
@28
x393_testbench01.x393_i.ps7_i.SAXIHP0ACLK[0]
@22
x393_testbench01.x393_i.ps7_i.SAXIHP0ARADDR[31:0]
@28
x393_testbench01.x393_i.ps7_i.SAXIHP0ARBURST[1:0]
@22
x393_testbench01.x393_i.ps7_i.SAXIHP0ARCACHE[3:0]
@28
x393_testbench01.x393_i.ps7_i.SAXIHP0ARESETN[0]
@22
x393_testbench01.x393_i.ps7_i.SAXIHP0ARID[5:0]
x393_testbench01.x393_i.ps7_i.SAXIHP0ARLEN[3:0]
@28
x393_testbench01.x393_i.ps7_i.SAXIHP0ARLOCK[1:0]
x393_testbench01.x393_i.ps7_i.SAXIHP0ARPROT[2:0]
@22
x393_testbench01.x393_i.ps7_i.SAXIHP0ARQOS[3:0]
@28
x393_testbench01.x393_i.ps7_i.SAXIHP0ARREADY[0]
x393_testbench01.x393_i.ps7_i.SAXIHP0ARSIZE[2:0]
x393_testbench01.x393_i.ps7_i.SAXIHP0ARVALID[0]
@22
x393_testbench01.x393_i.ps7_i.SAXIHP0AWADDR[31:0]
@28
x393_testbench01.x393_i.ps7_i.SAXIHP0AWBURST[1:0]
@22
x393_testbench01.x393_i.ps7_i.SAXIHP0AWCACHE[3:0]
x393_testbench01.x393_i.ps7_i.SAXIHP0AWID[5:0]
x393_testbench01.x393_i.ps7_i.SAXIHP0AWLEN[3:0]
@28
x393_testbench01.x393_i.ps7_i.SAXIHP0AWLOCK[1:0]
x393_testbench01.x393_i.ps7_i.SAXIHP0AWPROT[2:0]
@22
x393_testbench01.x393_i.ps7_i.SAXIHP0AWQOS[3:0]
@28
x393_testbench01.x393_i.ps7_i.SAXIHP0AWREADY[0]
@22
x393_testbench01.x393_i.ps7_i.SAXIHP0AWSIZE[2:0]
@28
x393_testbench01.x393_i.ps7_i.SAXIHP0AWVALID[0]
@22
x393_testbench01.x393_i.ps7_i.SAXIHP0BID[5:0]
@28
x393_testbench01.x393_i.ps7_i.SAXIHP0BREADY[0]
x393_testbench01.x393_i.ps7_i.SAXIHP0BRESP[1:0]
x393_testbench01.x393_i.ps7_i.SAXIHP0BVALID[0]
x393_testbench01.x393_i.ps7_i.SAXIHP0RACOUNT[2:0]
@22
x393_testbench01.x393_i.ps7_i.SAXIHP0RCOUNT[7:0]
x393_testbench01.x393_i.ps7_i.SAXIHP0RDATA[63:0]
@28
x393_testbench01.x393_i.ps7_i.SAXIHP0RDISSUECAP1EN[0]
@22
x393_testbench01.x393_i.ps7_i.SAXIHP0RID[5:0]
@28
x393_testbench01.x393_i.ps7_i.SAXIHP0RLAST[0]
x393_testbench01.x393_i.ps7_i.SAXIHP0RREADY[0]
x393_testbench01.x393_i.ps7_i.SAXIHP0RRESP[1:0]
x393_testbench01.x393_i.ps7_i.SAXIHP0RVALID[0]
@22
x393_testbench01.x393_i.ps7_i.SAXIHP0WACOUNT[5:0]
x393_testbench01.x393_i.ps7_i.SAXIHP0WCOUNT[7:0]
x393_testbench01.x393_i.ps7_i.SAXIHP0WDATA[63:0]
x393_testbench01.x393_i.ps7_i.SAXIHP0WID[5:0]
@28
x393_testbench01.x393_i.ps7_i.SAXIHP0WLAST[0]
x393_testbench01.x393_i.ps7_i.SAXIHP0WREADY[0]
x393_testbench01.x393_i.ps7_i.SAXIHP0WRISSUECAP1EN[0]
@22
x393_testbench01.x393_i.ps7_i.SAXIHP0WSTRB[7:0]
@28
x393_testbench01.x393_i.ps7_i.SAXIHP0WVALID[0]
@1000200
-SAXIHP0
@c00200
-linear_rw_chn1
@28
......
x393_testbench01.tf
View file @ 0fda102e
......@@ -31,7 +31,7 @@
//`define TEST_READ_PATTERN 1
//`define TEST_WRITE_BLOCK 1
//`define TEST_READ_BLOCK 1
//`define TEST_SCANLINE_WRITE
`define TEST_SCANLINE_WRITE
`define TEST_SCANLINE_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
//`define TEST_SCANLINE_READ
`define TEST_READ_SHOW 1
......@@ -42,7 +42,7 @@
//`define TEST_TILED_WRITE32 1
//`define TEST_TILED_READ32 1
`define TEST_AFI_WRITE 1
//`define TEST_AFI_WRITE 1
`define TEST_AFI_READ 1
module x393_testbench01 #(
......@@ -580,8 +580,8 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
end
// protect from never end
initial begin
#200000;
// #50000;
// #200000;
#60000;
$display("finish testbench 2");
$finish;
end
......@@ -1424,6 +1424,9 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
// -----------------------------------------
integer mode;
`ifdef MEMBRIDGE_DEBUG_READ
integer ii;
`endif
begin
$display("====== test_afi_rw: write=%d, extra_pages=%d, frame_start= %x, window_full_width=%d, window_width=%d, window_height=%d, window_left=%d, window_top=%d,@%t",
write_ddr3, extra_pages, frame_start_addr, window_full_width, window_width, window_height, window_left, window_top, $time);
......@@ -1452,7 +1455,16 @@ task test_afi_rw; // SuppressThisWarning VEditor - may be unused
start64,
lo_addr64,
size64);
membridge_start (continue);
membridge_start (continue);
`ifdef MEMBRIDGE_DEBUG_READ
// debugging
for (ii=0; ii < 10; ii=ii +1) begin
#200; //#50;
write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL, {27'b0,continue,4'b1101}); // enable both address and data
end
#500;
write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL, {26'b0,continue,5'b10001}); // disable debug (enable remaining xfers)
`endif
// just wait done
wait_status_condition ( // may also be read directly from the same bit of mctrl_linear_rw (address=5) status
MEMBRIDGE_STATUS_REG, // MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
......
x393_timing.xdc
View file @ 0fda102e
......@@ -79,3 +79,5 @@ create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
# do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
# do not check timing between clk_axihp_pre and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock_axihp -asynchronous -group {clk_axihp_pre}
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment