fixed timing measurement with the same start/end signal. v.03930102

fpga_version.vh

@@ -36,7 +36,8 @@
  * with at least one of the Free Software programs.
  */
  
-        parameter FPGA_VERSION =          32'h03930101;      // serial - 17.4 - disabling SOF when setting interface
+        parameter FPGA_VERSION =          32'h03930102;      // serial - 17.4 - disabling SOF when setting interface, bug fix
+//      parameter FPGA_VERSION =          32'h03930101;      // serial - 17.4 - disabling SOF when setting interface - met
 //      parameter FPGA_VERSION =          32'h03930100;      // serial - 17.4 - disabling SOF when setting interface timing OK
 //      parameter FPGA_VERSION =          32'h039300ff;      // serial - 15.3 - same, suspected bitstream problems
 //      parameter FPGA_VERSION =          32'h039300fe;      // serial - 17.4 - same, suspected bitstream problems no timing errors

sensor/sens_hispi12l4.v

@@ -174,8 +174,8 @@ module  sens_hispi12l4#(
         else if (tim_ibusy[0] && tim_f)  tim_ibusy <= 2;
         else if (tim_ibusy[1] && tim_t)  tim_ibusy <= 0;
         
-        if      (tim_ibusy[0] || tim_f)  tim_icntr <= 0; // reset if repeated start (e.g. to measure last sol to eof)
-        else if (tim_ibusy[1])           tim_icntr <= tim_icntr + 1;
+        if      (tim_ibusy[0] || (tim_f && !tim_t))  tim_icntr <= 0; // reset if repeated start (e.g. to measure last sol to eof)
+        else if (tim_ibusy[1])                       tim_icntr <= tim_icntr + 1;
     end
     always @ (posedge mclk) begin
         tim_busy_r <= {tim_busy_r[0], |tim_ibusy};