Commit 0ec5957a authored by Andrey Filippov's avatar Andrey Filippov
Browse files

Reordered fold ROM table so first/second variant match colors, repeating 

R/B color twice (instead of 0), so the output values will have the same
value range.
parent 412a3a33

dsp/create_bayer_fold_rom.py

+23 −1
Original line number Original line Diff line number Diff line
@@ -218,6 +218,27 @@ def create_fold(n = 8): # n - DCT and window size 
                if not blank:

                if not blank:

                    addresses.append (fold_index[i][var4])

                    addresses.append (fold_index[i][var4])

                    signs.append ([((0,1)[fold_signs[0][i][var4] < 0]),((0,1)[fold_signs[1][i][var4] < 0])])

                    signs.append ([((0,1)[fold_signs[0][i][var4] < 0]),((0,1)[fold_signs[1][i][var4] < 0])])

            byrs = []

            for var2 in range(2):

                row = (addresses[var2] >> 4) & 0xf

                col = (addresses[var2] >> 0) & 0xf

                byr = ((row & 1) << 1) + (col & 1)

                byrs.append(byr)

            #make sure first variant always has lower byr index

            if byrs[1] < byrs[0]:

                addresses = [addresses[1],addresses[0]]

                signs =     [signs[1],signs[0]]

        

            for var2 in range(2):

                row = (addresses[var2] >> 4) & 0xf

                col = (addresses[var2] >> 0) & 0xf

                byr = ((row & 1) << 1) + (col & 1)

                print ("%1d "%(byr,),end="")

            print ("   ",end="")

            

            if ((i + 1) % 8) == 0:

                print()         

                    

            for size_bits, size_val in enumerate ([16,18,20,22]):

            for size_bits, size_val in enumerate ([16,18,20,22]):

                for var2 in range(2):

                for var2 in range(2):

                    row = (addresses[var2] >> 4) & 0xf

                    row = (addresses[var2] >> 4) & 0xf
@@ -228,6 +249,7 @@ def create_fold(n = 8): # n - DCT and window size 
                        ((full_addr & 0xff) << 8) +

                        ((full_addr & 0xff) << 8) +

                        (signs[var2][0] << 16) +

                        (signs[var2][0] << 16) +

                        (signs[var2][1] << 17))

                        (signs[var2][1] << 17))

        print()                     

            

            

#      wire                        [7:0] wnd_a_w =   fold_rom_out[7:0];

#      wire                        [7:0] wnd_a_w =   fold_rom_out[7:0];

#    wire         [PIX_ADDR_WIDTH-1:0] pix_a_w =   {~fold_rom_out[15] & fold_rom_out[7],fold_rom_out[15:8]};

#    wire         [PIX_ADDR_WIDTH-1:0] pix_a_w =   {~fold_rom_out[15] & fold_rom_out[7],fold_rom_out[15:8]};

dsp/mclt16x16_bayer.v

+12 −28
Original line number Original line Diff line number Diff line
@@ -97,7 +97,6 @@ module mclt16x16_bayer#( 
    reg                   inv_checker_r3;                

    reg                   inv_checker_r3;                

    reg                   inv_checker_r4;                

    reg                   inv_checker_r4;                





//    wire signed       [WND_WIDTH-1:0] window;       //!< msb==0, always positive

    wire                         [1:0] signs;        //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input

    wire                         [1:0] signs;        //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input

    wire                        [14:0] phases;        //!< other signals

    wire                        [14:0] phases;        //!< other signals
@@ -140,7 +139,6 @@ module mclt16x16_bayer#( 
    reg                            dtt_r_regen;

    reg                            dtt_r_regen;

    reg                            dtt_start;

    reg                            dtt_start;

    

    

//    wire                     [1:0] dtt_mode = {dtt_r_cntr[7], dtt_r_cntr[6]}; // TODO: or reverse? 

    wire                           dtt_mode = dtt_r_cntr[6]; // TODO: or reverse? 

    wire                           dtt_mode = dtt_r_cntr[6]; // TODO: or reverse? 

    wire                     [8:0] dtt_r_ra = {1'b0,dtt_r_page,dtt_r_cntr};

    wire                     [8:0] dtt_r_ra = {1'b0,dtt_r_page,dtt_r_cntr};

    wire signed             [35:0] dtt_r_data_w; // high bits are not used 

    wire signed             [35:0] dtt_r_data_w; // high bits are not used
@@ -179,25 +177,21 @@ module mclt16x16_bayer#( 
            y_shft_r4 <= y_shft_r3;

            y_shft_r4 <= y_shft_r3;

            inv_checker_r4 <= inv_checker_r3;

            inv_checker_r4 <= inv_checker_r3;

        end

        end

        

        if (phases[8]) begin

        if (phases[8]) begin

            pix_d_r <= pix_d;

            pix_d_r <= pix_d;

            window_r <=   window_w;

            window_r <=   window_w;

        end

        end

        if (phases[9])  pix_wnd_r <= pix_d_r * window_r; // 1 MSB is extra

        if (phases[9])  pix_wnd_r <= pix_d_r * window_r; // 1 MSB is extra

    

    

        // pix_wnd_r2 - positive with 2 extra zeros, max value 0x3fff60

        if (phases[10]) begin

        if (phases[10]) begin

            pix_wnd_r2 <= {{2{pix_wnd_r2_w[DTT_IN_WIDTH-3]}},pix_wnd_r2_w};

            pix_wnd_r2 <= {{2{pix_wnd_r2_w[DTT_IN_WIDTH-3]}},pix_wnd_r2_w};

//            mpix_use_r  <= mpix_use_d;

//            var_first_r <= var_first_d;

            pix_sgn_r <=  pix_sgn_d; 

            pix_sgn_r <=  pix_sgn_d; 

        end

        end

        

        

        var_last <= var_first & phases[11];

        var_last <= var_first & phases[11];

       

       

        if (phases[11]) begin

        if (phases[11]) begin

//            data_cc_r <= (var_first ? {DTT_IN_WIDTH{1'b0}} : data_cc_r) + (mpix_use_r ? (mpix_sgn_r[0]?(-pix_wnd_r2):pix_wnd_r2): {DTT_IN_WIDTH{1'b0}}) ;

//            data_sc_r <= (var_first ? {DTT_IN_WIDTH{1'b0}} : data_sc_r) + (mpix_use_r ? (mpix_sgn_r[1]?(-pix_wnd_r2):pix_wnd_r2): {DTT_IN_WIDTH{1'b0}}) ;

             data_cc_r <= (var_first ? {DTT_IN_WIDTH{1'b0}} : data_cc_r) + (pix_sgn_r[0]?(-pix_wnd_r2):pix_wnd_r2) ;

             data_cc_r <= (var_first ? {DTT_IN_WIDTH{1'b0}} : data_cc_r) + (pix_sgn_r[0]?(-pix_wnd_r2):pix_wnd_r2) ;

             data_sc_r <= (var_first ? {DTT_IN_WIDTH{1'b0}} : data_sc_r) + (pix_sgn_r[1]?(-pix_wnd_r2):pix_wnd_r2) ;

             data_sc_r <= (var_first ? {DTT_IN_WIDTH{1'b0}} : data_sc_r) + (pix_sgn_r[1]?(-pix_wnd_r2):pix_wnd_r2) ;

             data_sc_r2 <= data_sc_r;

             data_sc_r2 <= data_sc_r;
@@ -233,7 +227,6 @@ module mclt16x16_bayer#( 
        if (!dtt_r_re) dtt_r_cntr <= 0;

        if (!dtt_r_re) dtt_r_cntr <= 0;

        else           dtt_r_cntr <= dtt_r_cntr + 1;

        else           dtt_r_cntr <= dtt_r_cntr + 1;

        

        

///        dtt_start <= dtt_r_cntr[5:0] == 0;

        dtt_start <= (dtt_r_cntr[5:0] == 0) && dtt_r_re;

        dtt_start <= (dtt_r_cntr[5:0] == 0) && dtt_r_re;

    

    

    end

    end
@@ -243,17 +236,17 @@ module mclt16x16_bayer#( 
        .SHIFT_WIDTH     (SHIFT_WIDTH),

        .SHIFT_WIDTH     (SHIFT_WIDTH),

        .PIX_ADDR_WIDTH  (PIX_ADDR_WIDTH),

        .PIX_ADDR_WIDTH  (PIX_ADDR_WIDTH),

        .COORD_WIDTH     (COORD_WIDTH),

        .COORD_WIDTH     (COORD_WIDTH),

        .PIXEL_WIDTH     (PIXEL_WIDTH),

//        .PIXEL_WIDTH     (PIXEL_WIDTH),

        .WND_WIDTH       (WND_WIDTH),

        .WND_WIDTH       (WND_WIDTH)

        .OUT_WIDTH       (OUT_WIDTH),

//        .OUT_WIDTH       (OUT_WIDTH),

        .DTT_IN_WIDTH    (DTT_IN_WIDTH),

//        .DTT_IN_WIDTH    (DTT_IN_WIDTH),

        .TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),

//        .TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),

        .OUT_RSHIFT      (OUT_RSHIFT),

//        .OUT_RSHIFT      (OUT_RSHIFT),

        .OUT_RSHIFT2     (OUT_RSHIFT2),

//        .OUT_RSHIFT2     (OUT_RSHIFT2),

        .DSP_B_WIDTH     (DSP_B_WIDTH),

//        .DSP_B_WIDTH     (DSP_B_WIDTH),

        .DSP_A_WIDTH     (DSP_A_WIDTH),

//        .DSP_A_WIDTH     (DSP_A_WIDTH),

        .DSP_P_WIDTH     (DSP_P_WIDTH),

//        .DSP_P_WIDTH     (DSP_P_WIDTH),

        .DEAD_CYCLES     (DEAD_CYCLES)

//        .DEAD_CYCLES     (DEAD_CYCLES)

    ) mclt_bayer_fold_i (

    ) mclt_bayer_fold_i (

        .clk         (clk),         // input

        .clk         (clk),         // input

        .rst         (rst),         // input

        .rst         (rst),         // input
@@ -324,12 +317,10 @@ module mclt16x16_bayer#( 
 

 

    wire                  [8:0] dtt_out_ram_wa = {dtt_out_ram_wah,dtt_out_wa16};

    wire                  [8:0] dtt_out_ram_wa = {dtt_out_ram_wah,dtt_out_wa16};

    reg                   [7:0] dtt_dly_cntr;

    reg                   [7:0] dtt_dly_cntr;

//    reg                   [8:0] dtt_rd_cntr; // counter for dtt readout to rotator

    reg                   [8:0] dtt_rd_cntr_pre; // 1 ahead of the former counter for dtt readout to rotator

    reg                   [8:0] dtt_rd_cntr_pre; // 1 ahead of the former counter for dtt readout to rotator

    

    

    // TODO: fix rd addresses

    // TODO: fix rd addresses

    

    

//    wire                  [8:0] dtt_rd_ra = {dtt_rd_cntr[8],dtt_rd_cntr[0],dtt_rd_cntr[1],dtt_rd_cntr[7:2]}; // page, mode, frequency

    reg                   [8:0] dtt_rd_ra0; 

    reg                   [8:0] dtt_rd_ra0; 

    reg                   [8:0] dtt_rd_ra1; 

    reg                   [8:0] dtt_rd_ra1;
@@ -340,7 +331,6 @@ module mclt16x16_bayer#( 
    wire signed [OUT_WIDTH-1:0] dtt_rd_data0 = dtt_rd_data0_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3]

    wire signed [OUT_WIDTH-1:0] dtt_rd_data0 = dtt_rd_data0_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3]

    wire signed [OUT_WIDTH-1:0] dtt_rd_data1 = dtt_rd_data1_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3]

    wire signed [OUT_WIDTH-1:0] dtt_rd_data1 = dtt_rd_data1_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3]

    

    

//    wire                        dtt_first_quad_out = ~dtt_out_ram_cntr[3] & ~dtt_out_ram_cntr[2];

    wire                        dtt_first_quad_out = ~dtt_out_ram_cntr[2];

    wire                        dtt_first_quad_out = ~dtt_out_ram_cntr[2];

    

    

    always @(posedge clk) begin

    always @(posedge clk) begin
@@ -358,10 +348,6 @@ module mclt16x16_bayer#( 
        

        

        dtt_start_out <= dtt_dly_cntr == 1;

        dtt_start_out <= dtt_dly_cntr == 1;





//        if      (rst)               dtt_rd_regen_dv[0] <= 0;

//        else if (dtt_start_out)     dtt_rd_regen_dv[0] <= 1;

//        else if (&dtt_rd_cntr[7:0]) dtt_rd_regen_dv[0] <= 0;



        if      (rst)                   dtt_rd_regen_dv[0] <= 0;

        if      (rst)                   dtt_rd_regen_dv[0] <= 0;

        else if (dtt_start_out)         dtt_rd_regen_dv[0] <= 1;

        else if (dtt_start_out)         dtt_rd_regen_dv[0] <= 1;

        else if (&dtt_rd_cntr_pre[6:0]) dtt_rd_regen_dv[0] <= 0;

        else if (&dtt_rd_cntr_pre[6:0]) dtt_rd_regen_dv[0] <= 0;
@@ -369,11 +355,9 @@ module mclt16x16_bayer#( 
        if      (rst)               dtt_rd_regen_dv[3:1] <= 0;

        if      (rst)               dtt_rd_regen_dv[3:1] <= 0;

        else                        dtt_rd_regen_dv[3:1] <= dtt_rd_regen_dv[2:0];

        else                        dtt_rd_regen_dv[3:1] <= dtt_rd_regen_dv[2:0];

        

        

//        if (dtt_start_out)           dtt_rd_cntr_pre <= {dtt_out_ram_wah[4], 8'b0}; //copy page number

        if (dtt_start_out)           dtt_rd_cntr_pre <= {dtt_out_ram_wpage, 7'b0}; //copy page number

        if (dtt_start_out)           dtt_rd_cntr_pre <= {dtt_out_ram_wpage, 7'b0}; //copy page number

        

        

        else if (dtt_rd_regen_dv[0]) dtt_rd_cntr_pre <= dtt_rd_cntr_pre + 1;

        else if (dtt_rd_regen_dv[0]) dtt_rd_cntr_pre <= dtt_rd_cntr_pre + 1;

////    wire                  [8:0] dtt_rd_ra = {dtt_rd_cntr[8],dtt_rd_cntr[0],dtt_rd_cntr[1],dtt_rd_cntr[7:2]}; // page, mode, frequency

        

        

        dtt_rd_ra0 <= {dtt_rd_cntr_pre[8:7],

        dtt_rd_ra0 <= {dtt_rd_cntr_pre[8:7],

                       dtt_rd_cntr_pre[6] ^ dtt_rd_cntr_pre[5],

                       dtt_rd_cntr_pre[6] ^ dtt_rd_cntr_pre[5],

dsp/mclt_bayer_fold.v

+22 −19
Original line number Original line Diff line number Diff line
@@ -42,19 +42,19 @@ module mclt_bayer_fold#( 
    parameter SHIFT_WIDTH =      7, // bits in shift (7 bits - fractional)

    parameter SHIFT_WIDTH =      7, // bits in shift (7 bits - fractional)

    parameter PIX_ADDR_WIDTH =   9, // number of pixel address width

    parameter PIX_ADDR_WIDTH =   9, // number of pixel address width

//    parameter EXT_PIX_LATENCY =  2, // external pixel buffer a->d latency

//    parameter EXT_PIX_LATENCY =  2, // external pixel buffer a->d latency

    parameter ADDR_DLY =        4'h2, // extra delay of pixel address to match window delay

//    parameter ADDR_DLY =        4'h2, // extra delay of pixel address to match window delay

    parameter COORD_WIDTH =     10, // bits in full coordinate 10 for 18K RAM

    parameter COORD_WIDTH =     10, // bits in full coordinate 10 for 18K RAM

    parameter PIXEL_WIDTH =     16, // input pixel width (unsigned) 

//    parameter PIXEL_WIDTH =     16, // input pixel width (unsigned) 

    parameter WND_WIDTH =       18, // input pixel width (unsigned) 

    parameter WND_WIDTH =       18 // input pixel width (unsigned) 

    parameter OUT_WIDTH =       25, // bits in dtt output

//    parameter OUT_WIDTH =       25, // bits in dtt output

    parameter DTT_IN_WIDTH =    25, // bits in DTT input

//    parameter DTT_IN_WIDTH =    25, // bits in DTT input

    parameter TRANSPOSE_WIDTH = 25, // width of the transpose memory (intermediate results)    

//    parameter TRANSPOSE_WIDTH = 25, // width of the transpose memory (intermediate results)    

    parameter OUT_RSHIFT =       2, // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)

//    parameter OUT_RSHIFT =       2, // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)

    parameter OUT_RSHIFT2 =      0, // overall right shift for the second (vertical) pass

//    parameter OUT_RSHIFT2 =      0, // overall right shift for the second (vertical) pass

    parameter DSP_B_WIDTH =     18, // signed, output from sin/cos ROM

//    parameter DSP_B_WIDTH =     18, // signed, output from sin/cos ROM

    parameter DSP_A_WIDTH =     25,

//    parameter DSP_A_WIDTH =     25,

    parameter DSP_P_WIDTH =     48,

//    parameter DSP_P_WIDTH =     48,

    parameter DEAD_CYCLES =     14  // start next block immedaitely, or with longer pause

//    parameter DEAD_CYCLES =     14  // start next block immedaitely, or with longer pause

)(

)(

    input                             clk,          //!< system clock, posedge

    input                             clk,          //!< system clock, posedge

    input                             rst,          //!< sync reset

    input                             rst,          //!< sync reset
@@ -77,12 +77,15 @@ module mclt_bayer_fold#( 
);

);

    reg                         [6:0] in_cntr;      // input phase counter

    reg                         [6:0] in_cntr;      // input phase counter

    reg                        [14:0] run_r;        // run phase

    reg                        [14:0] run_r;        // run phase

    

    reg                         [1:0] tile_size_r;  // 0: 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (max for 9-bit addr)

    reg                         [1:0] tile_size_r;  // 0: 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (max for 9-bit addr)

    reg                               inv_checker_r;// 0 - includes main diagonal (symmetrical DTT), 1 - antisymmetrical DTT

    reg                               inv_checker_r;// 0 - includes main diagonal (symmetrical DTT), 1 - antisymmetrical DTT

    reg                         [7:0] top_left_r0;  // index of the 16x16 top left corner

    reg                         [7:0] top_left_r0;  // index of the 16x16 top left corner

    reg                         [7:0] top_left_r;   // index of the 16x16 top left corner

    reg                         [7:0] top_left_r;   // index of the 16x16 top left corner

    reg                         [1:0] valid_rows_r0;// 3 for green, 1 or 2 for R/B - which of the even/odd checker rows contain pixels

    reg                         [1:0] valid_rows_r0;// 3 for green, 1 or 2 for R/B - which of the even/odd checker rows contain pixels

    reg                         [1:0] valid_rows_r ;// correct latency for window rom

//    reg                         [1:0] valid_rows_r ;// correct latency for window rom

/// wire                       [ 9:0] fold_addr=    {tile_size_r,inv_checker_r, in_cntr[0],in_cntr[6:1]}; 

    wire                       [ 9:0] fold_addr=    {tile_size_r,inv_checker_r, (valid_rows_r0==3)?in_cntr[0]:valid_rows_r0[0],in_cntr[6:1]}; 

    reg             [SHIFT_WIDTH-1:0] x_shft_r0;    // tile pixel X fractional shift (valid @ start) 

    reg             [SHIFT_WIDTH-1:0] x_shft_r0;    // tile pixel X fractional shift (valid @ start) 

    reg             [SHIFT_WIDTH-1:0] y_shft_r0;    // tile pixel Y fractional shift (valid @ start)

    reg             [SHIFT_WIDTH-1:0] y_shft_r0;    // tile pixel Y fractional shift (valid @ start)

    reg             [SHIFT_WIDTH-1:0] x_shft_r;     // matching delay 

    reg             [SHIFT_WIDTH-1:0] x_shft_r;     // matching delay
@@ -94,7 +97,7 @@ module mclt_bayer_fold#( 
    wire         [PIX_ADDR_WIDTH-1:0] pix_a_w =   {~fold_rom_out[15] & fold_rom_out[7],fold_rom_out[15:8]};

    wire         [PIX_ADDR_WIDTH-1:0] pix_a_w =   {~fold_rom_out[15] & fold_rom_out[7],fold_rom_out[15:8]};

    reg          [PIX_ADDR_WIDTH-1:0] pix_a_r;

    reg          [PIX_ADDR_WIDTH-1:0] pix_a_r;

    wire                       [ 1:0] sgn_w =     fold_rom_out[16 +: 2];

    wire                       [ 1:0] sgn_w =     fold_rom_out[16 +: 2];

    reg                               blank_r;    // blank window (latency 1 from fold_rom_out)

//    reg                               blank_r;    // blank window (latency 1 from fold_rom_out)

//    wire                              blank_d;    //  delayed to matchwindow rom regrst

//    wire                              blank_d;    //  delayed to matchwindow rom regrst

    wire                              pre_page =  in_cntr == 2; // valid 1 cycle before fold_rom_out

    wire                              pre_page =  in_cntr == 2; // valid 1 cycle before fold_rom_out
@@ -139,15 +142,15 @@ module mclt_bayer_fold#( 
        if (run_r[2]) pix_a_r <= pix_a_w + {1'b0, top_left_r};

        if (run_r[2]) pix_a_r <= pix_a_w + {1'b0, top_left_r};

        

        





        if (in_cntr == 2) valid_rows_r <= valid_rows_r0;

///        if (in_cntr == 2) valid_rows_r <= valid_rows_r0;

        

        

        blank_r <= ~(wnd_a_w[0] ? valid_rows_r[1]: valid_rows_r[0]);  

///        blank_r <= ~(wnd_a_w[0] ? valid_rows_r[1]: valid_rows_r[0]);  

        

        

        if (run_r[10]) begin

        if (run_r[10]) begin

            var_first <= var_first_d;

            var_first <= var_first_d;

        end

        end

         

         

        pre_last_in <= in_cntr[7:0] == 8'hfd;

        pre_last_in <= in_cntr[6:0] == 7'h7d;
@@ -164,7 +167,7 @@ module mclt_bayer_fold#( 
    ) i_mclt_fold_rom (

    ) i_mclt_fold_rom (

    

    

        .clk_a     (clk),          // input

        .clk_a     (clk),          // input

        .addr_a    ({tile_size_r,inv_checker_r, in_cntr[0],in_cntr[6:1]}),    // input[9:0] 

        .addr_a    (fold_addr),    // input[9:0] 

        .en_a      (run_r[0]),     // input

        .en_a      (run_r[0]),     // input

        .regen_a   (run_r[1]),     // input

        .regen_a   (run_r[1]),     // input

        .we_a      (1'b0),         // input

        .we_a      (1'b0),         // input
@@ -219,7 +222,7 @@ module mclt_bayer_fold#( 
        .y_in      (wnd_a_w[7:4]), // input[3:0] 

        .y_in      (wnd_a_w[7:4]), // input[3:0] 

        .x_shft    (x_shft_r),     // input[7:0] 

        .x_shft    (x_shft_r),     // input[7:0] 

        .y_shft    (y_shft_r),     // input[7:0]

        .y_shft    (y_shft_r),     // input[7:0]

        .zero_in   (blank_r),      // input 2 cycles after inputs! 

        .zero_in   (1'b0),         // blank_r),      // input 2 cycles after inputs! 

        .wnd_out   (window)        // output[17:0] valid with in_busy[8]

        .wnd_out   (window)        // output[17:0] valid with in_busy[8]

    );

    );

includes/mclt_bayer_fold_rom.vh

+72 −72
Original line number Original line Diff line number Diff line 
// Created with ./create_bayer_fold_rom.py

// Created with ./create_bayer_fold_rom.py

// MCLT 16x16...22x22 Bayer -> 8x8 fold indices

// MCLT 16x16...22x22 Bayer -> 8x8 fold indices

, .INIT_00 (256'hA4A4A2A2A6A6A0A0A8A8AEAEAAAAACACB3B3B5B5B1B1B7B7BFBFB9B9BDBDBBBB)

, .INIT_00 (256'hA4A4A2A2A6A6A0A0A8A8AEAEAAAAACACC4C4C2C2C6C6C0C0C8C8CECECACACCCC)

, .INIT_01 (256'h848482828686808088888E8E8A8A8C8C93939595919197979F9F99999D9D9B9B)

, .INIT_01 (256'h848482828686808088888E8E8A8A8C8CE4E4E2E2E6E6E0E0E8E8EEEEEAEAECEC)

, .INIT_02 (256'h13131515111117171F1F19191D1D1B1B040402020606000008080E0E0A0A0C0C)

, .INIT_02 (256'h646462626666606068686E6E6A6A6C6C040402020606000008080E0E0A0A0C0C)

, .INIT_03 (256'h33333535313137373F3F39393D3D3B3B242422222626202028282E2E2A2A2C2C)

, .INIT_03 (256'h444442424646404048484E4E4A4A4C4C242422222626202028282E2E2A2A2C2C)

, .INIT_04 (256'hD3D3D5D5D1D1D7D7DFDFD9D9DDDDDBDBC4C4C2C2C6C6C0C0C8C8CECECACACCCC)

, .INIT_04 (256'hD3D3D5D5D1D1D7D7DFDFD9D9DDDDDBDBB3B3B5B5B1B1B7B7BFBFB9B9BDBDBBBB)

, .INIT_05 (256'hF3F3F5F5F1F1F7F7FFFFF9F9FDFDFBFBE4E4E2E2E6E6E0E0E8E8EEEEEAEAECEC)

, .INIT_05 (256'hF3F3F5F5F1F1F7F7FFFFF9F9FDFDFBFB93939595919197979F9F99999D9D9B9B)

, .INIT_06 (256'h646462626666606068686E6E6A6A6C6C73737575717177777F7F79797D7D7B7B)

, .INIT_06 (256'h13131515111117171F1F19191D1D1B1B73737575717177777F7F79797D7D7B7B)

, .INIT_07 (256'h444442424646404048484E4E4A4A4C4C53535555515157575F5F59595D5D5B5B)

, .INIT_07 (256'h33333535313137373F3F39393D3D3B3B53535555515157575F5F59595D5D5B5B)

, .INIT_08 (256'hA3A3A5A5A1A1A7A7AFAFA9A9ADADABABB4B4B2B2B6B6B0B0B8B8BEBEBABABCBC)

, .INIT_08 (256'hA3A3A5A5A1A1A7A7AFAFA9A9ADADABABC3C3C5C5C1C1C7C7CFCFC9C9CDCDCBCB)

, .INIT_09 (256'h83838585818187878F8F89898D8D8B8B949492929696909098989E9E9A9A9C9C)

, .INIT_09 (256'h83838585818187878F8F89898D8D8B8BE3E3E5E5E1E1E7E7EFEFE9E9EDEDEBEB)

, .INIT_0A (256'h141412121616101018181E1E1A1A1C1C03030505010107070F0F09090D0D0B0B)

, .INIT_0A (256'h63636565616167676F6F69696D6D6B6B03030505010107070F0F09090D0D0B0B)

, .INIT_0B (256'h343432323636303038383E3E3A3A3C3C23232525212127272F2F29292D2D2B2B)

, .INIT_0B (256'h43434545414147474F4F49494D4D4B4B23232525212127272F2F29292D2D2B2B)

, .INIT_0C (256'hD4D4D2D2D6D6D0D0D8D8DEDEDADADCDCC3C3C5C5C1C1C7C7CFCFC9C9CDCDCBCB)

, .INIT_0C (256'hD4D4D2D2D6D6D0D0D8D8DEDEDADADCDCB4B4B2B2B6B6B0B0B8B8BEBEBABABCBC)

, .INIT_0D (256'hF4F4F2F2F6F6F0F0F8F8FEFEFAFAFCFCE3E3E5E5E1E1E7E7EFEFE9E9EDEDEBEB)

, .INIT_0D (256'hF4F4F2F2F6F6F0F0F8F8FEFEFAFAFCFC949492929696909098989E9E9A9A9C9C)

, .INIT_0E (256'h63636565616167676F6F69696D6D6B6B747472727676707078787E7E7A7A7C7C)

, .INIT_0E (256'h141412121616101018181E1E1A1A1C1C747472727676707078787E7E7A7A7C7C)

, .INIT_0F (256'h43434545414147474F4F49494D4D4B4B545452525656505058585E5E5A5A5C5C)

, .INIT_0F (256'h343432323636303038383E3E3A3A3C3C545452525656505058585E5E5A5A5C5C)

, .INIT_10 (256'hB8A4B6A2BAA6B4A0BCA8C2AEBEAAC0ACC9B3CBB5C7B1CDB7D5BFCFB9D3BDD1BB)

, .INIT_10 (256'hB8A4B6A2BAA6B4A0BCA8C2AEBEAAC0ACDCC4DAC2DEC6D8C0E0C8E6CEE2CAE4CC)

, .INIT_11 (256'h948492829686908098889E8E9A8A9C8CA593A795A391A997B19FAB99AF9DAD9B)

, .INIT_11 (256'h948492829686908098889E8E9A8A9C8C00E4FEE202E6FCE004E80AEE06EA08EC)

, .INIT_12 (256'h1513171513111917211F1B191F1D1D1B040402020606000008080E0E0A0A0C0C)

, .INIT_12 (256'h70646E6272666C6074687A6E766A786C040402020606000008080E0E0A0A0C0C)

, .INIT_13 (256'h39333B3537313D37453F3F39433D413B282426222A2624202C28322E2E2A302C)

, .INIT_13 (256'h4C444A424E4648405048564E524A544C282426222A2624202C28322E2E2A302C)

, .INIT_14 (256'hEDD3EFD5EBD1F1D7F9DFF3D9F7DDF5DBDCC4DAC2DEC6D8C0E0C8E6CEE2CAE4CC)

, .INIT_14 (256'hEDD3EFD5EBD1F1D7F9DFF3D9F7DDF5DBC9B3CBB5C7B1CDB7D5BFCFB9D3BDD1BB)

, .INIT_15 (256'h11F313F50FF115F71DFF17F91BFD19FB00E4FEE202E6FCE004E80AEE06EA08EC)

, .INIT_15 (256'h11F313F50FF115F71DFF17F91BFD19FBA593A795A391A997B19FAB99AF9DAD9B)

, .INIT_16 (256'h70646E6272666C6074687A6E766A786C817383757F7185778D7F87798B7D897B)

, .INIT_16 (256'h1513171513111917211F1B191F1D1D1B817383757F7185778D7F87798B7D897B)

, .INIT_17 (256'h4C444A424E4648405048564E524A544C5D535F555B516157695F6359675D655B)

, .INIT_17 (256'h39333B3537313D37453F3F39433D413B5D535F555B516157695F6359675D655B)

, .INIT_18 (256'hB7A3B9A5B5A1BBA7C3AFBDA9C1ADBFABCAB4C8B2CCB6C6B0CEB8D4BED0BAD2BC)

, .INIT_18 (256'hB7A3B9A5B5A1BBA7C3AFBDA9C1ADBFABDBC3DDC5D9C1DFC7E7CFE1C9E5CDE3CB)

, .INIT_19 (256'h93839585918197879F8F99899D8D9B8BA694A492A896A290AA98B09EAC9AAE9C)

, .INIT_19 (256'h93839585918197879F8F99899D8D9B8BFFE301E5FDE103E70BEF05E909ED07EB)

, .INIT_1A (256'h16141412181612101A18201E1C1A1E1C03030505010107070F0F09090D0D0B0B)

, .INIT_1A (256'h6F6371656D6173677B6F7569796D776B03030505010107070F0F09090D0D0B0B)

, .INIT_1B (256'h3A3438323C3636303E38443E403A423C2723292525212B27332F2D29312D2F2B)

, .INIT_1B (256'h4B434D4549414F47574F5149554D534B2723292525212B27332F2D29312D2F2B)

, .INIT_1C (256'hEED4ECD2F0D6EAD0F2D8F8DEF4DAF6DCDBC3DDC5D9C1DFC7E7CFE1C9E5CDE3CB)

, .INIT_1C (256'hEED4ECD2F0D6EAD0F2D8F8DEF4DAF6DCCAB4C8B2CCB6C6B0CEB8D4BED0BAD2BC)

, .INIT_1D (256'h12F410F214F60EF016F81CFE18FA1AFCFFE301E5FDE103E70BEF05E909ED07EB)

, .INIT_1D (256'h12F410F214F60EF016F81CFE18FA1AFCA694A492A896A290AA98B09EAC9AAE9C)

, .INIT_1E (256'h6F6371656D6173677B6F7569796D776B8274807284767E7086788C7E887A8A7C)

, .INIT_1E (256'h16141412181612101A18201E1C1A1E1C8274807284767E7086788C7E887A8A7C)

, .INIT_1F (256'h4B434D4549414F47574F5149554D534B5E545C5260565A506258685E645A665C)

, .INIT_1F (256'h3A3438323C3636303E38443E403A423C5E545C5260565A506258685E645A665C)

, .INIT_20 (256'hCCA4CAA2CEA6C8A0D0A8D6AED2AAD4ACDFB3E1B5DDB1E3B7EBBFE5B9E9BDE7BB)

, .INIT_20 (256'hCCA4CAA2CEA6C8A0D0A8D6AED2AAD4ACF4C4F2C2F6C6F0C0F8C8FECEFACAFCCC)

, .INIT_21 (256'hA484A282A686A080A888AE8EAA8AAC8CB793B995B591BB97C39FBD99C19DBF9B)

, .INIT_21 (256'hA484A282A686A080A888AE8EAA8AAC8C1CE41AE21EE618E020E826EE22EA24EC)

, .INIT_22 (256'h1713191515111B17231F1D19211D1F1B040402020606000008080E0E0A0A0C0C)

, .INIT_22 (256'h7C647A627E6678608068866E826A846C040402020606000008080E0E0A0A0C0C)

, .INIT_23 (256'h3F3341353D3143374B3F4539493D473B2C242A222E2628203028362E322A342C)

, .INIT_23 (256'h544452425646504058485E4E5A4A5C4C2C242A222E2628203028362E322A342C)

, .INIT_24 (256'h07D309D505D10BD713DF0DD911DD0FDBF4C4F2C2F6C6F0C0F8C8FECEFACAFCCC)

, .INIT_24 (256'h07D309D505D10BD713DF0DD911DD0FDBDFB3E1B5DDB1E3B7EBBFE5B9E9BDE7BB)

, .INIT_25 (256'h2FF331F52DF133F73BFF35F939FD37FB1CE41AE21EE618E020E826EE22EA24EC)

, .INIT_25 (256'h2FF331F52DF133F73BFF35F939FD37FBB793B995B591BB97C39FBD99C19DBF9B)

, .INIT_26 (256'h7C647A627E6678608068866E826A846C8F7391758D7193779B7F9579997D977B)

, .INIT_26 (256'h1713191515111B17231F1D19211D1F1B8F7391758D7193779B7F9579997D977B)

, .INIT_27 (256'h544452425646504058485E4E5A4A5C4C6753695565516B57735F6D59715D6F5B)

, .INIT_27 (256'h3F3341353D3143374B3F4539493D473B6753695565516B57735F6D59715D6F5B)

, .INIT_28 (256'hCBA3CDA5C9A1CFA7D7AFD1A9D5ADD3ABE0B4DEB2E2B6DCB0E4B8EABEE6BAE8BC)

, .INIT_28 (256'hCBA3CDA5C9A1CFA7D7AFD1A9D5ADD3ABF3C3F5C5F1C1F7C7FFCFF9C9FDCDFBCB)

, .INIT_29 (256'hA383A585A181A787AF8FA989AD8DAB8BB894B692BA96B490BC98C29EBE9AC09C)

, .INIT_29 (256'hA383A585A181A787AF8FA989AD8DAB8B1BE31DE519E11FE727EF21E925ED23EB)

, .INIT_2A (256'h181416121A1614101C18221E1E1A201C03030505010107070F0F09090D0D0B0B)

, .INIT_2A (256'h7B637D6579617F67876F8169856D836B03030505010107070F0F09090D0D0B0B)

, .INIT_2B (256'h40343E3242363C3044384A3E463A483C2B232D2529212F27372F3129352D332B)

, .INIT_2B (256'h53435545514157475F4F59495D4D5B4B2B232D2529212F27372F3129352D332B)

, .INIT_2C (256'h08D406D20AD604D00CD812DE0EDA10DCF3C3F5C5F1C1F7C7FFCFF9C9FDCDFBCB)

, .INIT_2C (256'h08D406D20AD604D00CD812DE0EDA10DCE0B4DEB2E2B6DCB0E4B8EABEE6BAE8BC)

, .INIT_2D (256'h30F42EF232F62CF034F83AFE36FA38FC1BE31DE519E11FE727EF21E925ED23EB)

, .INIT_2D (256'h30F42EF232F62CF034F83AFE36FA38FCB894B692BA96B490BC98C29EBE9AC09C)

, .INIT_2E (256'h7B637D6579617F67876F8169856D836B90748E7292768C7094789A7E967A987C)

, .INIT_2E (256'h181416121A1614101C18221E1E1A201C90748E7292768C7094789A7E967A987C)

, .INIT_2F (256'h53435545514157475F4F59495D4D5B4B685466526A5664506C58725E6E5A705C)

, .INIT_2F (256'h40343E3242363C3044384A3E463A483C685466526A5664506C58725E6E5A705C)

, .INIT_30 (256'hE0A4DEA2E2A6DCA0E4A8EAAEE6AAE8ACF5B3F7B5F3B1F9B701BFFBB9FFBDFDBB)

, .INIT_30 (256'hE0A4DEA2E2A6DCA0E4A8EAAEE6AAE8AC0CC40AC20EC608C010C816CE12CA14CC)

, .INIT_31 (256'hB484B282B686B080B888BE8EBA8ABC8CC993CB95C791CD97D59FCF99D39DD19B)

, .INIT_31 (256'hB484B282B686B080B888BE8EBA8ABC8C38E436E23AE634E03CE842EE3EEA40EC)

, .INIT_32 (256'h19131B1517111D17251F1F19231D211B040402020606000008080E0E0A0A0C0C)

, .INIT_32 (256'h886486628A6684608C68926E8E6A906C040402020606000008080E0E0A0A0C0C)

, .INIT_33 (256'h4533473543314937513F4B394F3D4D3B30242E2232262C2034283A2E362A382C)

, .INIT_33 (256'h5C445A425E4658406048664E624A644C30242E2232262C2034283A2E362A382C)

, .INIT_34 (256'h21D323D51FD125D72DDF27D92BDD29DB0CC40AC20EC608C010C816CE12CA14CC)

, .INIT_34 (256'h21D323D51FD125D72DDF27D92BDD29DBF5B3F7B5F3B1F9B701BFFBB9FFBDFDBB)

, .INIT_35 (256'h4DF34FF54BF151F759FF53F957FD55FB38E436E23AE634E03CE842EE3EEA40EC)

, .INIT_35 (256'h4DF34FF54BF151F759FF53F957FD55FBC993CB95C791CD97D59FCF99D39DD19B)

, .INIT_36 (256'h886486628A6684608C68926E8E6A906C9D739F759B71A177A97FA379A77DA57B)

, .INIT_36 (256'h19131B1517111D17251F1F19231D211B9D739F759B71A177A97FA379A77DA57B)

, .INIT_37 (256'h5C445A425E4658406048664E624A644C715373556F5175577D5F77597B5D795B)

, .INIT_37 (256'h4533473543314937513F4B394F3D4D3B715373556F5175577D5F77597B5D795B)

, .INIT_38 (256'hDFA3E1A5DDA1E3A7EBAFE5A9E9ADE7ABF6B4F4B2F8B6F2B0FAB800BEFCBAFEBC)

, .INIT_38 (256'hDFA3E1A5DDA1E3A7EBAFE5A9E9ADE7AB0BC30DC509C10FC717CF11C915CD13CB)

, .INIT_39 (256'hB383B585B181B787BF8FB989BD8DBB8BCA94C892CC96C690CE98D49ED09AD29C)

, .INIT_39 (256'hB383B585B181B787BF8FB989BD8DBB8B37E339E535E13BE743EF3DE941ED3FEB)

, .INIT_3A (256'h1A1418121C1616101E18241E201A221C03030505010107070F0F09090D0D0B0B)

, .INIT_3A (256'h8763896585618B67936F8D69916D8F6B03030505010107070F0F09090D0D0B0B)

, .INIT_3B (256'h46344432483642304A38503E4C3A4E3C2F2331252D2133273B2F3529392D372B)

, .INIT_3B (256'h5B435D4559415F47674F6149654D634B2F2331252D2133273B2F3529392D372B)

, .INIT_3C (256'h22D420D224D61ED026D82CDE28DA2ADC0BC30DC509C10FC717CF11C915CD13CB)

, .INIT_3C (256'h22D420D224D61ED026D82CDE28DA2ADCF6B4F4B2F8B6F2B0FAB800BEFCBAFEBC)

, .INIT_3D (256'h4EF44CF250F64AF052F858FE54FA56FC37E339E535E13BE743EF3DE941ED3FEB)

, .INIT_3D (256'h4EF44CF250F64AF052F858FE54FA56FCCA94C892CC96C690CE98D49ED09AD29C)

, .INIT_3E (256'h8763896585618B67936F8D69916D8F6B9E749C72A0769A70A278A87EA47AA67C)

, .INIT_3E (256'h1A1418121C1616101E18241E201A221C9E749C72A0769A70A278A87EA47AA67C)

, .INIT_3F (256'h5B435D4559415F47674F6149654D634B7254705274566E5076587C5E785A7A5C)

, .INIT_3F (256'h46344432483642304A38503E4C3A4E3C7254705274566E5076587C5E785A7A5C)

, .INITP_00 (256'hBB88EE22BB88EE22EE22BB88EE22BB8811DD447711DD4477BB88EE22BB88EE22)

, .INITP_00 (256'h11DDEE2211DDEE22EE22EE22EE22EE22BB884477BB884477BB88BB88BB88BB88)

, .INITP_01 (256'hEE22BB88EE22BB88BB88EE22BB88EE22447711DD447711DDEE22BB88EE22BB88)

, .INITP_01 (256'h4477BB884477BB88BB88BB88BB88BB88EE2211DDEE2211DDEE22EE22EE22EE22)

, .INITP_02 (256'hBB88EE22BB88EE22EE22BB88EE22BB8811DD447711DD4477BB88EE22BB88EE22)

, .INITP_02 (256'h11DDEE2211DDEE22EE22EE22EE22EE22BB884477BB884477BB88BB88BB88BB88)

, .INITP_03 (256'hEE22BB88EE22BB88BB88EE22BB88EE22447711DD447711DDEE22BB88EE22BB88)

, .INITP_03 (256'h4477BB884477BB88BB88BB88BB88BB88EE2211DDEE2211DDEE22EE22EE22EE22)

, .INITP_04 (256'hBB88EE22BB88EE22EE22BB88EE22BB8811DD447711DD4477BB88EE22BB88EE22)

, .INITP_04 (256'h11DDEE2211DDEE22EE22EE22EE22EE22BB884477BB884477BB88BB88BB88BB88)

, .INITP_05 (256'hEE22BB88EE22BB88BB88EE22BB88EE22447711DD447711DDEE22BB88EE22BB88)

, .INITP_05 (256'h4477BB884477BB88BB88BB88BB88BB88EE2211DDEE2211DDEE22EE22EE22EE22)

, .INITP_06 (256'hBB88EE22BB88EE22EE22BB88EE22BB8811DD447711DD4477BB88EE22BB88EE22)

, .INITP_06 (256'h11DDEE2211DDEE22EE22EE22EE22EE22BB884477BB884477BB88BB88BB88BB88)

, .INITP_07 (256'hEE22BB88EE22BB88BB88EE22BB88EE22447711DD447711DDEE22BB88EE22BB88)
 
, .INITP_07 (256'h4477BB884477BB88BB88BB88BB88BB88EE2211DDEE2211DDEE22EE22EE22EE22)

mclt_test_02.sav

+25 −7

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