Commit 0e866d77 authored by Andrey Filippov's avatar Andrey Filippov

Simulating 8x8 DCT

parent 6912f6d6
...@@ -44,7 +44,7 @@ module dct2d8x8_chen#( ...@@ -44,7 +44,7 @@ module dct2d8x8_chen#(
parameter STAGE1_SAFE_BITS = 3, // leave this number of extra bits on DCT1D input to prevent output saturation parameter STAGE1_SAFE_BITS = 3, // leave this number of extra bits on DCT1D input to prevent output saturation
parameter STAGE2_SAFE_BITS = 3, // leave this number of extra bits on DCT1D input to prevent output saturation parameter STAGE2_SAFE_BITS = 3, // leave this number of extra bits on DCT1D input to prevent output saturation
parameter TRANSPOSE_WIDTH = 16, // transpose memory width parameter TRANSPOSE_WIDTH = 16, // transpose memory width
parameter TRIM_STAGE_1 = 0, // Trim these MSBs from the stage1 results parameter TRIM_STAGE_1 = 1, // Trim these MSBs from the stage1 results (1 - matches old DCT)
parameter TRIM_STAGE_2 = 2, // Trim these MSBs from the stage2 results TODO: put real value parameter TRIM_STAGE_2 = 2, // Trim these MSBs from the stage2 results TODO: put real value
parameter DSP_WIDTH = 24, parameter DSP_WIDTH = 24,
parameter DSP_OUT_WIDTH = 24, parameter DSP_OUT_WIDTH = 24,
......
...@@ -56,7 +56,7 @@ module dct_chen_transpose#( ...@@ -56,7 +56,7 @@ module dct_chen_transpose#(
reg wcol13; // columns 1 and 3 (special) reg wcol13; // columns 1 and 3 (special)
wire [3:0] wrow_mod; // effective row, including modifier for wpage wire [3:0] wrow_mod; // effective row, including modifier for wpage
wire [1:0] wcol01_mod = wcol[1:0] + wcol[2]; wire [1:0] wcol01_mod = wcol[1:0] - wcol[2];
reg [6:0] waddr; reg [6:0] waddr;
wire pre2_stop; wire pre2_stop;
reg [WIDTH-1:0] transpose_ram[0:127]; reg [WIDTH-1:0] transpose_ram[0:127];
...@@ -76,12 +76,12 @@ module dct_chen_transpose#( ...@@ -76,12 +76,12 @@ module dct_chen_transpose#(
assign dout_10_32_76_54 = ram_reg2; assign dout_10_32_76_54 = ram_reg2;
// TODO: prevent writing to previous page after pause! // TODO: prevent writing to previous page after pause!
always @(posedge clk) begin always @(posedge clk) begin
wcol13 <= ~wcol[0] & ~wcol[2]; wcol13 <= pre_we_r & ~wcol[0] & ~wcol[2];
waddr[0] <= wrow_mod[0] ^ wrow_mod[2]; waddr[0] <= wrow_mod[0] ^ wrow_mod[2];
waddr[1] <= wcol[1]; waddr[1] <= wcol[0];
waddr[2] <= ~wcol01_mod[0] ^ wcol01_mod[1]; waddr[2] <= wcol01_mod[1];
waddr[3] <= ~wcol01_mod[1]; waddr[3] <= ~wcol01_mod[0] ^ wcol01_mod[1];
waddr[4] <= wrow_mod[0] ^ wrow_mod[2]; waddr[4] <= wrow_mod[1] ^ wrow_mod[2];
waddr[5] <= wrow_mod[2]; waddr[5] <= wrow_mod[2];
waddr[6] <= wpage; waddr[6] <= wpage;
...@@ -91,7 +91,7 @@ module dct_chen_transpose#( ...@@ -91,7 +91,7 @@ module dct_chen_transpose#(
if (rst) wcntr <= 0; if (rst) wcntr <= 0;
else if (pre_we_r) wcntr <= wcntr + 1; // including page, should be before 'if (pre2_start)' else if (pre_we_r) wcntr <= wcntr + 1; // including page, should be before 'if (pre2_start)'
else if (pre2_start) wcntr <= {wcntr[6], 6'b0}; // if happens during pre_we_r - will be ignore, otherwise (after pause) will zero in-page adderss else if (pre2_start) wcntr <= {wcntr[6], 6'b0}; // if happens during pre_we_r - will be ignored, otherwise (after pause) will zero in-page adderss
we_r <= pre_we_r; we_r <= pre_we_r;
...@@ -99,7 +99,7 @@ module dct_chen_transpose#( ...@@ -99,7 +99,7 @@ module dct_chen_transpose#(
if (rst) rcntr <= ~0; if (rst) rcntr <= ~0;
else if (pre_rstart_w) rcntr <= 0; else if (pre_rstart_w) rcntr <= 0;
else if (rcntr != ~0) rcntr <= rcntr + 1; else if (!(&rcntr)) rcntr <= rcntr + 1;
re_r <= ~rcntr[2]; re_r <= ~rcntr[2];
regen_r <= re_r; regen_r <= re_r;
......
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