Commit 0cfebd24 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

More editing, trying to run Xilinx tools

parent 210ed954
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+15 −15
Original line number Original line Diff line number Diff line
@@ -62,77 +62,77 @@
		<link>
		<link>
			<name>vivado_logs/VivadoBitstream.log</name>
			<name>vivado_logs/VivadoBitstream.log</name>
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			<type>1</type>
			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150720133322322.log</location>
			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150722003723406.log</location>
		</link>
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			<name>vivado_logs/VivadoOpt.log</name>
			<name>vivado_logs/VivadoOpt.log</name>
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			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150720133322322.log</location>
			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150722003207037.log</location>
		</link>
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			<name>vivado_logs/VivadoOptPhys.log</name>
			<name>vivado_logs/VivadoOptPhys.log</name>
			<type>1</type>
			<type>1</type>
			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150720133322322.log</location>
			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150722003723406.log</location>
		</link>
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		<link>
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			<name>vivado_logs/VivadoOptPower.log</name>
			<name>vivado_logs/VivadoOptPower.log</name>
			<type>1</type>
			<type>1</type>
			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150720133322322.log</location>
			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150722003207037.log</location>
		</link>
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			<name>vivado_logs/VivadoPlace.log</name>
			<name>vivado_logs/VivadoPlace.log</name>
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			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150720133322322.log</location>
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			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150720133322322.log</location>
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			<name>vivado_logs/VivadoSynthesis.log</name>
			<name>vivado_logs/VivadoSynthesis.log</name>
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			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
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			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
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			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150720130350146.log</location>
			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150722002329036.log</location>
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			<location>/home/andrey/git/x393/vivado_state/x393-place-20150720133322322.dcp</location>
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		</link>
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</projectDescription>
</projectDescription>
+1 −1
Original line number Original line Diff line number Diff line
@@ -4,6 +4,6 @@ VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_127_verbose=true
VivadoSynthesis_127_verbose=true
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_95_ShowInfo=true
VivadoSynthesis_95_ShowInfo=false
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->
eclipse.preferences.version=1
eclipse.preferences.version=1
+3 −3
Original line number Original line Diff line number Diff line
@@ -455,8 +455,8 @@ module cmprs_afi_mux#(
        .chunk_ptr_ra (chunk_ptr_ra), // output[3:0] reg 
        .chunk_ptr_ra (chunk_ptr_ra), // output[3:0] reg 
        .chunk_ptr_rd (chunk_ptr_rd[CMPRS_AFIMUX_WIDTH-1:0]) // input[25:0] 
        .chunk_ptr_rd (chunk_ptr_rd[CMPRS_AFIMUX_WIDTH-1:0]) // input[25:0] 
    );
    );
    pulse_cross_clock sa_len_we_i (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(cmd_we_sa_len_w), .out_pulse(sa_len_we),.busy());
    pulse_cross_clock sa_len_we_i (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(cmd_we_sa_len_w), .out_pulse(sa_len_we),.busy());
    pulse_cross_clock en_we_i     (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(cmd_we_en_w),     .out_pulse(en_we),    .busy());
    pulse_cross_clock en_we_i     (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(cmd_we_en_w),     .out_pulse(en_we),    .busy());
    pulse_cross_clock en_rst_i    (.rst(rst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(cmd_we_rst_w),    .out_pulse(en_rst),.busy());
    pulse_cross_clock en_rst_i    (.rst(mrst), .src_clk(mclk), .dst_clk(hclk), .in_pulse(cmd_we_rst_w),    .out_pulse(en_rst),.busy());


endmodule
endmodule
+0 −1
Original line number Original line Diff line number Diff line
@@ -421,7 +421,6 @@ module histogram_saxi#(
    ) fifo_same_clock_i (
    ) fifo_same_clock_i (
        .rst       (1'b0),           // input
        .rst       (1'b0),           // input
        .clk       (aclk),           // input
        .clk       (aclk),           // input
        .sync_rst  (arst),           // input
        .sync_rst  (!en_aclk),       // input
        .sync_rst  (!en_aclk),       // input
        .we        (buf_re[2]),      // input
        .we        (buf_re[2]),      // input
        .re        (fifo_re),        // input 
        .re        (fifo_re),        // input 

compressor_jp/color_proc393.v

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