Added more code: Farme level scanline memory interface with window,...

Added more code: Farme level scanline memory interface with window, multiplexor for multiple channels sharing the same linear R/W command encoder

.editor_defines

@@ -6,18 +6,22 @@
   // chn 0 is read from memory
  `define def_enable_mem_chn0
  `define def_read_mem_chn0
+ `undef  def_scanline_chn0
  
   // chn 1 is write to memory
  `define def_enable_mem_chn1
  `undef  def_read_mem_chn1
+ `undef  def_scanline_chn1
 
   // chn 2 is read from memory
  `define def_enable_mem_chn2
  `define def_read_mem_chn2
+ `define def_scanline_chn2
 
   // chn 3 is write to memory
  `define def_enable_mem_chn3
  `undef  def_read_mem_chn3
+ `define def_scanline_chn3
 
   // chn 4 is disabled
  `undef  def_enable_mem_chn4

address_map.txt

@@ -57,7 +57,7 @@
     parameter MCONTR_TOP_16BIT_REFRESH_ADDRESS= 'h2,    // 10 bits refresh address in the sequencer (PL) memory
     parameter MCONTR_TOP_16BIT_STATUS_CNTRL=    'h3,    // 8 bits - write to status control (and debug?)
 
-0x1100..11ff - 16-bit per-channel memory control    
+0x1100..11ff - 32-bit per-channel memory control    
 0x1100..110f - control of memory channels 0,1 - PS-controlled sequences
     parameter MCNTRL_PS_ADDR=            'h100,
     parameter MCNTRL_PS_MASK=            'h3e0, // both channels 0 and 1
@@ -69,6 +69,30 @@
     parameter MCNTRL_PS_STATUS_CNTRL=            'h2,
 
     
+    
+============= Add the following (addresses will vary for individual channels)
+    parameter ADDRESS_NUMBER=                   15,
+    parameter COLADDR_NUMBER=                   10,
+    parameter NUM_XFER_BITS=                     6,    // number of bits to specify transfer length
+    parameter FRAME_WIDTH_BITS=                 13,    // Maximal frame width - 8-word (16 bytes) bursts 
+    parameter FRAME_HEIGHT_BITS=                16,    // Maximal frame height 
+    parameter MCNTRL_SCANLINE_ADDR=            'h120,
+    parameter MCNTRL_SCANLINE_MASK=            'h3f0, // both channels 0 and 1
+    parameter MCNTRL_SCANLINE_MODE=            'h0,   // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
+    parameter MCNTRL_SCANLINE_STATUS_CNTRL=    'h1,   // control status reporting
+    parameter MCNTRL_SCANLINE_STARTADDR=       'h2,   // 22-bit frame start address (3 CA LSBs==0. BA==0)
+    parameter MCNTRL_SCANLINE_FRAME_FULL_WIDTH='h3,   // Padded line length (8-row increment), in 8-bursts (16 bytes)
+    parameter MCNTRL_SCANLINE_WINDOW_WH=       'h4,   // low word - 13-bit window width (0->'n4000), high word - 16-bit frame height (0->'h10000)
+    parameter MCNTRL_SCANLINE_WINDOW_X0Y0=     'h5,   // low word - 13-bit window left, high word - 16-bit window top
+    parameter MCNTRL_SCANLINE_WINDOW_STARTXY=  'h6,   // low word - 13-bit start X (relative to window), high word - 16-bit start y
+                                                      // Start XY can be used when read command to start from the middle
+                                                      // TODO: Add number of blocks to R/W? (blocks can be different) - total length?
+                                                      // Read back current address (fro debugging)?
+    parameter MCNTRL_SCANLINE_STATUS_REG_ADDR= 'h4,
+
+    
+    
+    
 // Status read address
     parameter STATUS_ADDR =         'h1400, // AXI write address of status read registers
     parameter STATUS_ADDR_MASK =    'h1400, // AXI write address of status registers

memctrl/cmd_encod_linear_rd.v

@@ -45,7 +45,7 @@ module  cmd_encod_linear_rd #(
     input                  [2:0] bank_in,     // bank address
     input   [ADDRESS_NUMBER-1:0] row_in,      // memory row
     input   [COLADDR_NUMBER-4:0] start_col,   // start memory column in 8-bursts
-    input                  [5:0] num128_in,   // number of 128-bit words to transfer (8*16 bits) - full burst of 8
+    input                  [5:0] num128_in,   // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
     input                        start,       // start generating commands
     output reg            [31:0] enc_cmd,     // encoded commnad
     output reg                   enc_wr,      // write encoded command

memctrl/mcntrl_ps_pio.v

@@ -85,7 +85,7 @@ module  mcntrl_ps_pio#(
 // Port memory buffer (4 pages each, R/W fixed, port 0 - AXI read from DDR, port 1 - AXI write to DDR
 // generate 16-bit data commands (and set defaults to registers)
  wire               [4:0] cmd_a;
- wire              [15:0] cmd_data;
+ wire              [31:0] cmd_data;
  wire                     cmd_we;
  wire               [1:0] status_data;
  
@@ -98,8 +98,8 @@ module  mcntrl_ps_pio#(
  wire                     set_status_w;
  wire                     set_en_rst; // set enable, reset register
  reg                [1:0] en_reset;//
- wire                     chn_en = en_reset[1];   // enable requests by channle (continue ones in progress)
  wire                     chn_rst = ~en_reset[0]; // resets command, including fifo;
+ wire                     chn_en = &en_reset[1];   // enable requests by channle (continue ones in progress)
  reg                      mem_run;              // sequencere pgm granted and set, waiting/executing memory transfer to/from buffur 0/1
  wire                     busy;
  wire                     start;
@@ -113,7 +113,7 @@ module  mcntrl_ps_pio#(
  reg                      cmd_set;
  
  assign busy= want_rq0 || need_rq0 ||want_rq1 || need_rq1 || mem_run;
- assign start= !chn_rst && chn_en && !busy && cmd_nempty;
+ assign start= chn_en && !busy && cmd_nempty;
  assign seq_data0= cmd_seq_a;
  assign seq_set0=cmd_set;
  assign status_data=   {cmd_half_full,cmd_nempty | busy};
@@ -161,10 +161,10 @@ module  mcntrl_ps_pio#(
     cmd_deser #(
         .ADDR       (MCNTRL_PS_ADDR),
         .ADDR_MASK  (MCNTRL_PS_MASK),
-        .NUM_CYCLES (4),
+        .NUM_CYCLES (6),
         .ADDR_WIDTH (5),
-        .DATA_WIDTH (16)
-    ) cmd_deser_mcontr_16bit_i (
+        .DATA_WIDTH (32)
+    ) cmd_deser_mcontr_32bit_i (
         .rst        (rst), // input
         .clk        (mclk), // input
         .ad         (cmd_ad), // input[7:0]