Commit 0ad0b4a8 authored by Andrey Filippov's avatar Andrey Filippov

corrected memsensor/memcompressor line comparison

parent f8db6dd0
[*] [*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Tue Nov 15 08:28:37 2016 [*] Thu Nov 17 03:52:16 2016
[*] [*]
[dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20161115004643177.fst" [dumpfile] "/home/eyesis/git/x393-neon/simulation/x393_dut-20161116200800621.fst"
[dumpfile_mtime] "Tue Nov 15 08:28:05 2016" [dumpfile_mtime] "Thu Nov 17 03:40:28 2016"
[dumpfile_size] 302685090 [dumpfile_size] 230939121
[savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_03.sav" [savefile] "/home/eyesis/git/x393-neon/cocotb/x393_cocotb_03.sav"
[timestart] 152590000 [timestart] 0
[size] 1814 1171 [size] 1814 1171
[pos] 0 0 [pos] 0 0
*-23.275805 166587388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-25.389460 68867388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_dut. [treeopen] x393_dut.
[treeopen] x393_dut.simul_sensor12bits_2_i. [treeopen] x393_dut.simul_sensor12bits_2_i.
[treeopen] x393_dut.simul_sensor12bits_3_i. [treeopen] x393_dut.simul_sensor12bits_3_i.
...@@ -47,7 +47,9 @@ ...@@ -47,7 +47,9 @@
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i. [treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[1]. [treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[1].
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[2]. [treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[3]. [treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i. [treeopen] x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.
[treeopen] x393_dut.x393_i.mult_saxi_wr_inbuf_i. [treeopen] x393_dut.x393_i.mult_saxi_wr_inbuf_i.
[treeopen] x393_dut.x393_i.sensors393_i. [treeopen] x393_dut.x393_i.sensors393_i.
...@@ -2758,18 +2760,69 @@ x393_dut.x393_i.sof_out_mclk[3:0] ...@@ -2758,18 +2760,69 @@ x393_dut.x393_i.sof_out_mclk[3:0]
-group_end -group_end
@800200 @800200
-jpeg3 -jpeg3
-memsensor3
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_linear_wr_sensor_i.window_height[16:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_linear_wr_sensor_i.window_width[13:0]
@1000200
-memsensor3
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.window_height[16:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.window_width[13:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.tile_rows[6:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.tile_vstep[6:0]
@28 @28
x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.chn_en x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.chn_en
x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.chn_rst x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.chn_rst
x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.frame_en x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.frame_en
x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.frame_start x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.frame_start
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.frames_numbers_differ x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.frames_numbers_differ
@23 @22
[color] 6 [color] 6
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished_src[15:0] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished_src[15:0]
@28
x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.frame_start_mod
x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.chn_dis_delayed
(6)x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.recalc_r[8:0]
@c00022
[color] 6 [color] 6
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished[15:0] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished[15:0]
@28 @28
[color] 6
(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished[15:0]
[color] 6
(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished[15:0]
[color] 6
(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished[15:0]
[color] 6
(3)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished[15:0]
[color] 6
(4)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished[15:0]
[color] 6
(5)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished[15:0]
[color] 6
(6)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished[15:0]
[color] 6
(7)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished[15:0]
[color] 6
(8)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished[15:0]
[color] 6
(9)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished[15:0]
[color] 6
(10)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished[15:0]
[color] 6
(11)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished[15:0]
[color] 6
(12)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished[15:0]
[color] 6
(13)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished[15:0]
[color] 6
(14)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished[15:0]
[color] 6
(15)x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_unfinished[15:0]
@1401200
-group_end
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_numbers_sync x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.line_numbers_sync
x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.frames_in_sync x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.frames_in_sync
[color] 3 [color] 3
...@@ -2807,6 +2860,11 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuf ...@@ -2807,6 +2860,11 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuf
@28 @28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.stuffer_bytes[1:0] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.stuffer_bytes[1:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.stuffer_dv x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.stuffer_dv
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.flush_in
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.flush_hclk
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.irq
@23
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.frame_num_compressed[3:0]
@c00200 @c00200
-bit_stuffer_27_32 -bit_stuffer_27_32
@28 @28
......
...@@ -188,7 +188,8 @@ module cmprs_frame_sync#( ...@@ -188,7 +188,8 @@ module cmprs_frame_sync#(
frames_numbers_differ <= !suspend_end && (frame_number_src != frame_number); // during end of frame, before frame number is incremented frames_numbers_differ <= !suspend_end && (frame_number_src != frame_number); // during end of frame, before frame number is incremented
line_numbers_sync <= (line_unfinished_src > line_unfinished); /// line_numbers_sync <= (line_unfinished_src > line_unfinished);
line_numbers_sync <= (line_unfinished_src >= line_unfinished);
suspend <= bonded_mode && (!frames_in_sync || !((sigle_frame_buf ? frames_differ : frames_numbers_differ) || line_numbers_sync)); suspend <= bonded_mode && (!frames_in_sync || !((sigle_frame_buf ? frames_differ : frames_numbers_differ) || line_numbers_sync));
......
...@@ -35,7 +35,12 @@ ...@@ -35,7 +35,12 @@
* contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
parameter FPGA_VERSION = 32'h039300cd; //parallel - making stop compression clean -0.048/8, 79.50 parameter FPGA_VERSION = 32'h039300d1; //parallel - removed extra debug -0.042/9 80.34%
// parameter FPGA_VERSION = 32'h039300d1; //parallel - changing line_numbers_sync condition -0.011/3, 80.78 %
// parameter FPGA_VERSION = 32'h039300d0; //parallel - more status data
// parameter FPGA_VERSION = 32'h039300cf; //parallel - more status data for debugging ddr3_clk_div -0.033/2, 80.94%
// parameter FPGA_VERSION = 32'h039300ce; //parallel - frame_number_cntr >= last_frame_number -0.019/6 80.42%
// parameter FPGA_VERSION = 32'h039300cd; //parallel - making stop compression clean -0.048/8, 79.50
// parameter FPGA_VERSION = 32'h039300cc; //parallel - more jpeg tail -0.268/56, 80.24 % // parameter FPGA_VERSION = 32'h039300cc; //parallel - more jpeg tail -0.268/56, 80.24 %
// parameter FPGA_VERSION = 32'h039300cb; //parallel - modifying trigger/timestamps -0.050/13 80.38% // parameter FPGA_VERSION = 32'h039300cb; //parallel - modifying trigger/timestamps -0.050/13 80.38%
// parameter FPGA_VERSION = 32'h039300ca; //parallel - and more ... fixed -0.267/46, 80.42% // parameter FPGA_VERSION = 32'h039300ca; //parallel - and more ... fixed -0.267/46, 80.42%
......
...@@ -39,6 +39,7 @@ ...@@ -39,6 +39,7 @@
*/ */
`timescale 1ns/1ps `timescale 1ns/1ps
// TODO: ADD MCNTRL_SCANLINE_FRAME_PAGE_RESET to caller // TODO: ADD MCNTRL_SCANLINE_FRAME_PAGE_RESET to caller
`undef DEBUG_MCNTRL_LINEAR_EXTRA_STATUS
module mcntrl_linear_rw #( module mcntrl_linear_rw #(
parameter ADDRESS_NUMBER= 15, parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10, parameter COLADDR_NUMBER= 10,
...@@ -218,7 +219,11 @@ module mcntrl_linear_rw #( ...@@ -218,7 +219,11 @@ module mcntrl_linear_rw #(
wire pre_want; wire pre_want;
reg pre_want_r1; reg pre_want_r1;
`ifdef DEBUG_MCNTRL_LINEAR_EXTRA_STATUS
wire [11:0] status_data;
`else
wire [1:0] status_data; wire [1:0] status_data;
`endif
wire [3:0] cmd_a; wire [3:0] cmd_a;
wire [31:0] cmd_data; wire [31:0] cmd_data;
wire cmd_we; wire cmd_we;
...@@ -318,7 +323,8 @@ module mcntrl_linear_rw #( ...@@ -318,7 +323,8 @@ module mcntrl_linear_rw #(
else if (set_frame_width_w) frame_full_width <= {lsw13_zero,cmd_data[FRAME_WIDTH_BITS-1:0]}; else if (set_frame_width_w) frame_full_width <= {lsw13_zero,cmd_data[FRAME_WIDTH_BITS-1:0]};
if (mrst) is_last_frame <= 0; if (mrst) is_last_frame <= 0;
else is_last_frame <= frame_number_cntr == last_frame_number; // else is_last_frame <= frame_number_cntr == last_frame_number;
else is_last_frame <= frame_number_cntr >= last_frame_number; // trying to make it safe
// if (mrst) frame_start_r <= 0; // if (mrst) frame_start_r <= 0;
// else frame_start_r <= {frame_start_r[3:0], frame_start_late & frame_en}; // else frame_start_r <= {frame_start_r[3:0], frame_start_late & frame_en};
...@@ -420,7 +426,11 @@ module mcntrl_linear_rw #( ...@@ -420,7 +426,11 @@ module mcntrl_linear_rw #(
assign skip_too_late = mode_reg[MCONTR_LINTILE_SKIP_LATE]; assign skip_too_late = mode_reg[MCONTR_LINTILE_SKIP_LATE];
assign abort_en = mode_reg[MCONTR_LINTILE_ABORT_LATE]; assign abort_en = mode_reg[MCONTR_LINTILE_ABORT_LATE];
assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit? `ifdef DEBUG_MCNTRL_LINEAR_EXTRA_STATUS
assign status_data= {last_row_w, last_in_row,line_unfinished[7:0], frame_finished_r, busy_r};
`else
assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit?
`endif
assign pgm_param_w= cmd_we; assign pgm_param_w= cmd_we;
localparam [COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] EXTRA_BITS=0; localparam [COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] EXTRA_BITS=0;
assign remainder_in_xfer = {EXTRA_BITS, lim_by_xfer}-mem_page_left; assign remainder_in_xfer = {EXTRA_BITS, lim_by_xfer}-mem_page_left;
...@@ -698,7 +708,11 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r; ...@@ -698,7 +708,11 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
`ifdef DEBUG_SENS_MEM_PAGES `ifdef DEBUG_SENS_MEM_PAGES
.PAYLOAD_BITS (2 + 2 +2 + 2 + 2 + 2 +2 + 3 + 3 + MCNTRL_SCANLINE_PENDING_CNTR_BITS) .PAYLOAD_BITS (2 + 2 +2 + 2 + 2 + 2 +2 + 3 + 3 + MCNTRL_SCANLINE_PENDING_CNTR_BITS)
`else `else
`ifdef DEBUG_MCNTRL_LINEAR_EXTRA_STATUS
.PAYLOAD_BITS (12)
`else
.PAYLOAD_BITS (2) .PAYLOAD_BITS (2)
`endif
`endif `endif
) status_generate_i ( ) status_generate_i (
.rst (1'b0), //rst), // input .rst (1'b0), //rst), // input
......
...@@ -40,7 +40,7 @@ ...@@ -40,7 +40,7 @@
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
`timescale 1ns/1ps `timescale 1ns/1ps
`undef DEBUG_MCNTRL_TILED_EXTRA_STATUS
module mcntrl_tiled_rw#( module mcntrl_tiled_rw#(
parameter ADDRESS_NUMBER= 15, parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10, parameter COLADDR_NUMBER= 10,
...@@ -213,14 +213,16 @@ module mcntrl_tiled_rw#( ...@@ -213,14 +213,16 @@ module mcntrl_tiled_rw#(
reg last_block; reg last_block;
reg [MCNTRL_TILED_PENDING_CNTR_BITS-1:0] pending_xfers; // number of requested,. but not finished block transfers (to genearate frame done) reg [MCNTRL_TILED_PENDING_CNTR_BITS-1:0] pending_xfers; // number of requested,. but not finished block transfers (to genearate frame done)
reg [NUM_RC_BURST_BITS-1:0] row_col_r; reg [NUM_RC_BURST_BITS-1:0] row_col_r;
// reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_r0;
// reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_r1;
// reg [2*FRAME_HEIGHT_BITS-1:0] line_unfinished_r;
reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_relw_r; reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_relw_r;
reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_r; reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_r;
wire pre_want; wire pre_want;
`ifdef DEBUG_MCNTRL_TILED_EXTRA_STATUS
wire [13:0] status_data;
`else
wire [1:0] status_data; wire [1:0] status_data;
`endif
wire [3:0] cmd_a; wire [3:0] cmd_a;
wire [31:0] cmd_data; wire [31:0] cmd_data;
wire cmd_we; wire cmd_we;
...@@ -335,7 +337,8 @@ module mcntrl_tiled_rw#( ...@@ -335,7 +337,8 @@ module mcntrl_tiled_rw#(
else if (set_frame_width_w) frame_full_width <= {lsw13_zero,cmd_data[FRAME_WIDTH_BITS-1:0]}; else if (set_frame_width_w) frame_full_width <= {lsw13_zero,cmd_data[FRAME_WIDTH_BITS-1:0]};
if (mrst) is_last_frame <= 0; if (mrst) is_last_frame <= 0;
else is_last_frame <= frame_number_cntr == last_frame_number; // else is_last_frame <= frame_number_cntr == last_frame_number;
else is_last_frame <= frame_number_cntr >= last_frame_number; // trying to make it safe
if (mrst) frame_start_r <= 0; if (mrst) frame_start_r <= 0;
else frame_start_r <= {frame_start_r[3:0], frame_start_mod & frame_en}; // frame_start else frame_start_r <= {frame_start_r[3:0], frame_start_mod & frame_en}; // frame_start
...@@ -446,7 +449,13 @@ module mcntrl_tiled_rw#( ...@@ -446,7 +449,13 @@ module mcntrl_tiled_rw#(
assign repeat_frames= mode_reg[MCONTR_LINTILE_REPEAT]; assign repeat_frames= mode_reg[MCONTR_LINTILE_REPEAT];
assign disable_need = mode_reg[MCONTR_LINTILE_DIS_NEED]; assign disable_need = mode_reg[MCONTR_LINTILE_DIS_NEED];
assign abort_en = mode_reg[MCONTR_LINTILE_ABORT_LATE]; assign abort_en = mode_reg[MCONTR_LINTILE_ABORT_LATE];
`ifdef DEBUG_MCNTRL_TILED_EXTRA_STATUS
assign status_data= {frames_in_sync, suspend, last_row_w, last_in_row,line_unfinished[7:0], frame_finished_r, busy_r};
`else
assign status_data= {frame_finished_r, busy_r}; assign status_data= {frame_finished_r, busy_r};
`endif
assign pgm_param_w= cmd_we; assign pgm_param_w= cmd_we;
assign rowcol_inc= frame_full_width; assign rowcol_inc= frame_full_width;
assign num_cols_m1_w= num_cols_r-1; assign num_cols_m1_w= num_cols_r-1;
...@@ -644,7 +653,8 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r; ...@@ -644,7 +653,8 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
if (recalc_r[0]) line_unfinished_relw_r <= curr_y + (cmd_wrmem ? 0: tile_rows); if (recalc_r[0]) line_unfinished_relw_r <= curr_y + (cmd_wrmem ? 0: tile_rows);
if (mrst || (frame_start_mod || chn_dis_delayed)) line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid if (mrst || (frame_start_mod || chn_dis_delayed)) line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid
else if (recalc_r[2]) line_unfinished_r <= line_unfinished_relw_r + window_y0; /// else if (recalc_r[2]) line_unfinished_r <= line_unfinished_relw_r + window_y0;
else if (recalc_r[2] && busy_r) line_unfinished_r <= line_unfinished_relw_r + window_y0;
end end
always @ (negedge mclk) begin always @ (negedge mclk) begin
...@@ -669,7 +679,11 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r; ...@@ -669,7 +679,11 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
status_generate #( status_generate #(
.STATUS_REG_ADDR (MCNTRL_TILED_STATUS_REG_ADDR), .STATUS_REG_ADDR (MCNTRL_TILED_STATUS_REG_ADDR),
`ifdef DEBUG_MCNTRL_TILED_EXTRA_STATUS
.PAYLOAD_BITS (14)
`else
.PAYLOAD_BITS (2) .PAYLOAD_BITS (2)
`endif
) status_generate_i ( ) status_generate_i (
.rst (1'b0), // input .rst (1'b0), // input
.clk (mclk), // input .clk (mclk), // input
......
...@@ -2894,7 +2894,9 @@ jpeg_sim_multi 4 ...@@ -2894,7 +2894,9 @@ jpeg_sim_multi 4
################## Simulate Parallel 17 - free running, aborted frame #################### ################## Simulate Parallel 17 - free running, aborted frame ####################
./py393/test_mcntrl.py @py393/cocoargs --simulated=localhost:7777 ./py393/test_mcntrl.py @py393/cocoargs --simulated=localhost:7777
measure_all "*DI" measure_all "*DI"
setup_all_sensors True None 0xf #setup_all_sensors True None 0xf
setup_all_sensors True None 0xf False None None None None 0 1 5 # JP4
#setup_all_sensors True None 0xf False None None None None 0 1 0 # JPEG
#Setting ARO for free run mode? #Setting ARO for free run mode?
set_sensor_io_ctl all None None 1 # Set ARO low - check if it is still needed? set_sensor_io_ctl all None None 1 # Set ARO low - check if it is still needed?
......
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