added debug output

fpga_version.vh

@@ -35,7 +35,8 @@
  * contains all the components and scripts required to completely simulate it
  * with at least one of the Free Software programs.
  */
-        parameter FPGA_VERSION =          32'h03930121;      // VOSPI setting MOSI to low, according to DS
+        parameter FPGA_VERSION =          32'h03930122;      // Added debug output
+//      parameter FPGA_VERSION =          32'h03930121;      // VOSPI setting MOSI to low, according to DS
 //      parameter FPGA_VERSION =          32'h03930120;      // VOSPI
 //      parameter FPGA_VERSION =          32'h03930108;      // parallel - in master branch
 //      parameter FPGA_VERSION =          32'h03930107;      // parallel - 17.4 - restored delay after linear, fixed bug, all met

sensor/sens_lepton3.v

@@ -172,7 +172,7 @@ module  sens_lepton3 #(
     output        sof,  // @pclk
     output        eof,   // @pclk
             // not used PADS, keep for compatibility with PCB
-    input         dp2, //  input reserved
+    inout         dp2, //  input reserved - used for hardware debug (output for oscilloscope)
     input         dn2, // input reserved
     input         dn6  // input reserved
     
@@ -181,6 +181,7 @@ module  sens_lepton3 #(
 // Status data (6 bits + 4)
     wire [VOSPI_STATUS_BITS-1:0] status;
     wire                  [ 3:0] segment_id;
+    wire                         dbg_running;       // output debug output for oscilloscope
     wire                         crc_err_w;  // single-cycle CRC error
     reg                          crc_err_r;  // at least one CRC error happened since reset
     wire                         in_busy;
@@ -528,12 +529,26 @@ module  sens_lepton3 #(
         .T  (1'b1)                 // input - always off
     );
 
+    iobuf #( // sns_ctl
+        .DRIVE        (PXD_DRIVE),
+        .IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
+        .IOSTANDARD   (PXD_IOSTANDARD),
+        .SLEW         (PXD_SLEW)
+    ) dp2_i (
+        .O  (fake_dp2),            // output - currently not used
+        .IO (dp2),                 // inout I/O pad
+        .I  (dbg_running),         // input
+        .T  (1'b0)                 // input - always on
+    );
+
+/*
     ibuf_ibufg #(
         .IOSTANDARD   (PXD_IOSTANDARD)
     ) fake_dp2_i (
         .O(fake_dp2),
         .I(dp2)
     );
+*/
 
     ibuf_ibufg #(
         .IOSTANDARD   (PXD_IOSTANDARD)
@@ -606,7 +621,9 @@ module  sens_lepton3 #(
         .sof             (sof),              // output
         .eof             (eof),              // output
         .crc_err         (crc_err_w),        // output
-        .id              (segment_id)        // output[3:0] 
+        .id              (segment_id),       // output[3:0]
+        .dbg_running     (dbg_running)       // output debug output for oscilloscope
+         
     );
 
 

sensor/sensor_channel.v

@@ -1086,7 +1086,7 @@ module  sensor_channel#(
             .sof                  (sof),         // output
             .eof                  (eof),         // output
             // not used PADS, keep for compatibility with PCB
-            .dp2                  (sns_dp40[2]), // input reserved
+            .dp2                  (sns_dp40[2]), // inout reserved - used for debug
             .dn2                  (sns_dn40[2]), // input reserved
             .dn6                  (sns_dn76[6])  // input reserved
     );

sensor/vospi_segment_61.v

@@ -73,7 +73,8 @@ module  vospi_segment_61#(
     output        sof,             // start of frame
     output        eof,             // end of frame
     output        crc_err,         // crc error happened for any packet (valid at eos)
-    output  [3:0] id               // segment number  (valid at eos)
+    output  [3:0] id,               // segment number  (valid at eos)
+    output        dbg_running      // debug output for segment_running
 );
     localparam VOSPI_PACKETS_FRAME = (VOSPI_SEGMENT_LAST - VOSPI_SEGMENT_FIRST + 1) *
                                      (VOSPI_PACKET_LAST - VOSPI_PACKET_FIRST + 1);
@@ -134,7 +135,7 @@ module  vospi_segment_61#(
     assign in_busy=             segment_busy_r;       // waiting for or receiving a segment
     assign discard_segment=     discard_segment_r;    // segment was disc arded  
     
-    
+    assign dbg_running =        segment_running;
     // To Buffer
     always @ (posedge clk) begin
 //        if      (rst)   first_segment_in <= 0;