Commit 0aa9a5e2 authored by Andrey Filippov's avatar Andrey Filippov

added debug output

parent 8f2f1a21
...@@ -35,8 +35,9 @@ ...@@ -35,8 +35,9 @@
* contains all the components and scripts required to completely simulate it * contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
parameter FPGA_VERSION = 32'h03930121; // VOSPI setting MOSI to low, according to DS parameter FPGA_VERSION = 32'h03930122; // Added debug output
// parameter FPGA_VERSION = 32'h03930120; // VOSPI // parameter FPGA_VERSION = 32'h03930121; // VOSPI setting MOSI to low, according to DS
// parameter FPGA_VERSION = 32'h03930120; // VOSPI
// parameter FPGA_VERSION = 32'h03930108; // parallel - in master branch // parameter FPGA_VERSION = 32'h03930108; // parallel - in master branch
// parameter FPGA_VERSION = 32'h03930107; // parallel - 17.4 - restored delay after linear, fixed bug, all met // parameter FPGA_VERSION = 32'h03930107; // parallel - 17.4 - restored delay after linear, fixed bug, all met
// parameter FPGA_VERSION = 32'h03930110; //A serial - 17.4 - restored delay after linear, fixed bug, timing met // parameter FPGA_VERSION = 32'h03930110; //A serial - 17.4 - restored delay after linear, fixed bug, timing met
......
...@@ -172,7 +172,7 @@ module sens_lepton3 #( ...@@ -172,7 +172,7 @@ module sens_lepton3 #(
output sof, // @pclk output sof, // @pclk
output eof, // @pclk output eof, // @pclk
// not used PADS, keep for compatibility with PCB // not used PADS, keep for compatibility with PCB
input dp2, // input reserved inout dp2, // input reserved - used for hardware debug (output for oscilloscope)
input dn2, // input reserved input dn2, // input reserved
input dn6 // input reserved input dn6 // input reserved
...@@ -181,6 +181,7 @@ module sens_lepton3 #( ...@@ -181,6 +181,7 @@ module sens_lepton3 #(
// Status data (6 bits + 4) // Status data (6 bits + 4)
wire [VOSPI_STATUS_BITS-1:0] status; wire [VOSPI_STATUS_BITS-1:0] status;
wire [ 3:0] segment_id; wire [ 3:0] segment_id;
wire dbg_running; // output debug output for oscilloscope
wire crc_err_w; // single-cycle CRC error wire crc_err_w; // single-cycle CRC error
reg crc_err_r; // at least one CRC error happened since reset reg crc_err_r; // at least one CRC error happened since reset
wire in_busy; wire in_busy;
...@@ -528,12 +529,26 @@ module sens_lepton3 #( ...@@ -528,12 +529,26 @@ module sens_lepton3 #(
.T (1'b1) // input - always off .T (1'b1) // input - always off
); );
iobuf #( // sns_ctl
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) dp2_i (
.O (fake_dp2), // output - currently not used
.IO (dp2), // inout I/O pad
.I (dbg_running), // input
.T (1'b0) // input - always on
);
/*
ibuf_ibufg #( ibuf_ibufg #(
.IOSTANDARD (PXD_IOSTANDARD) .IOSTANDARD (PXD_IOSTANDARD)
) fake_dp2_i ( ) fake_dp2_i (
.O(fake_dp2), .O(fake_dp2),
.I(dp2) .I(dp2)
); );
*/
ibuf_ibufg #( ibuf_ibufg #(
.IOSTANDARD (PXD_IOSTANDARD) .IOSTANDARD (PXD_IOSTANDARD)
...@@ -606,7 +621,9 @@ module sens_lepton3 #( ...@@ -606,7 +621,9 @@ module sens_lepton3 #(
.sof (sof), // output .sof (sof), // output
.eof (eof), // output .eof (eof), // output
.crc_err (crc_err_w), // output .crc_err (crc_err_w), // output
.id (segment_id) // output[3:0] .id (segment_id), // output[3:0]
.dbg_running (dbg_running) // output debug output for oscilloscope
); );
......
...@@ -1086,7 +1086,7 @@ module sensor_channel#( ...@@ -1086,7 +1086,7 @@ module sensor_channel#(
.sof (sof), // output .sof (sof), // output
.eof (eof), // output .eof (eof), // output
// not used PADS, keep for compatibility with PCB // not used PADS, keep for compatibility with PCB
.dp2 (sns_dp40[2]), // input reserved .dp2 (sns_dp40[2]), // inout reserved - used for debug
.dn2 (sns_dn40[2]), // input reserved .dn2 (sns_dn40[2]), // input reserved
.dn6 (sns_dn76[6]) // input reserved .dn6 (sns_dn76[6]) // input reserved
); );
......
...@@ -73,7 +73,8 @@ module vospi_segment_61#( ...@@ -73,7 +73,8 @@ module vospi_segment_61#(
output sof, // start of frame output sof, // start of frame
output eof, // end of frame output eof, // end of frame
output crc_err, // crc error happened for any packet (valid at eos) output crc_err, // crc error happened for any packet (valid at eos)
output [3:0] id // segment number (valid at eos) output [3:0] id, // segment number (valid at eos)
output dbg_running // debug output for segment_running
); );
localparam VOSPI_PACKETS_FRAME = (VOSPI_SEGMENT_LAST - VOSPI_SEGMENT_FIRST + 1) * localparam VOSPI_PACKETS_FRAME = (VOSPI_SEGMENT_LAST - VOSPI_SEGMENT_FIRST + 1) *
(VOSPI_PACKET_LAST - VOSPI_PACKET_FIRST + 1); (VOSPI_PACKET_LAST - VOSPI_PACKET_FIRST + 1);
...@@ -134,7 +135,7 @@ module vospi_segment_61#( ...@@ -134,7 +135,7 @@ module vospi_segment_61#(
assign in_busy= segment_busy_r; // waiting for or receiving a segment assign in_busy= segment_busy_r; // waiting for or receiving a segment
assign discard_segment= discard_segment_r; // segment was disc arded assign discard_segment= discard_segment_r; // segment was disc arded
assign dbg_running = segment_running;
// To Buffer // To Buffer
always @ (posedge clk) begin always @ (posedge clk) begin
// if (rst) first_segment_in <= 0; // if (rst) first_segment_in <= 0;
...@@ -178,7 +179,7 @@ module vospi_segment_61#( ...@@ -178,7 +179,7 @@ module vospi_segment_61#(
segment_done <= segment_done_w; // module output reg segment_done <= segment_done_w; // module output reg
if (!segment_busy_r || start) segment_running <= 0; if (!segment_busy_r || start) segment_running <= 0;
else if (id_stb && (packet_id[11:0] == VOSPI_PACKET_FIRST)) segment_running <= 1; else if (id_stb && (packet_id[11:0] == VOSPI_PACKET_FIRST)) segment_running <= 1;
// packet_start <= !rst && !packet_busy && segment_busy_r; // packet_start <= !rst && !packet_busy && segment_busy_r;
packet_start <= !rst && !packet_busy && segment_busy_r && !packet_start; packet_start <= !rst && !packet_busy && segment_busy_r && !packet_start;
......
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