input[NUM_XFER_BITS-1:0]num128_in,// number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input[NUM_XFER_BITS-1:0]num128_in,// number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
inputskip_next_page_in,// do not reset external buffer (continue)
inputskip_next_page_in,// do not reset external buffer (continue)
inputstart,// start generating commands
inputstart,// start generating commands
outputreg[31:0]enc_cmd,// encoded commnad
outputreg[31:0]enc_cmd,// encoded command SuppressThisWarning VivadoSynthesis [Synth 8-3332] Sequential element cmd_encod_linear_rd.enc_cmd_reg[10:9,7:5,2] is unused and will be removed from module cmd_encod_linear_rd.
outputregenc_wr,// write encoded command
outputregenc_wr,// write encoded command
outputregenc_done// encoding finished
outputregenc_done// encoding finished
);
);
...
@@ -77,7 +77,7 @@ module cmd_encod_linear_rd #(
...
@@ -77,7 +77,7 @@ module cmd_encod_linear_rd #(
// reg gen_run_d;
// reg gen_run_d;
reg[ROM_DEPTH-1:0]gen_addr;// will overrun as stop comes from ROM
reg[ROM_DEPTH-1:0]gen_addr;// will overrun as stop comes from ROM
reg[ROM_WIDTH-1:0]rom_r;
reg[ROM_WIDTH-1:0]rom_r;// SuppressThisWarning VivadoSynthesis [Synth 8-3332] Sequential element cmd_encod_linear_rd.rom_r_reg[0] is unused and will be removed from module cmd_encod_linear_rd.
input[NUM_XFER_BITS-1:0]num128_in,// number of 128-bit words to transfer (8*16 bits) - full burst of 8 (0 - full 64)
input[NUM_XFER_BITS-1:0]num128_in,// number of 128-bit words to transfer (8*16 bits) - full burst of 8 (0 - full 64)
inputskip_next_page_in,// do not reset external buffer (continue)
inputskip_next_page_in,// do not reset external buffer (continue)
inputstart,// start generating commands
inputstart,// start generating commands
outputreg[31:0]enc_cmd,// encoded commnad
outputreg[31:0]enc_cmd,// encoded command SuppressThisWarning VivadoSynthesis [Synth 8-3332] Sequential element cmd_encod_linear_wr.enc_cmd_reg[9,6,4:3] is unused and will be removed from module cmd_encod_linear_wr.
outputregenc_wr,// write encoded command
outputregenc_wr,// write encoded command
outputregenc_done// encoding finished
outputregenc_done// encoding finished
);
);
...
@@ -90,7 +90,7 @@ module cmd_encod_linear_wr #(
...
@@ -90,7 +90,7 @@ module cmd_encod_linear_wr #(
// reg gen_run_d;
// reg gen_run_d;
reg[ROM_DEPTH-1:0]gen_addr;// will overrun as stop comes from ROM
reg[ROM_DEPTH-1:0]gen_addr;// will overrun as stop comes from ROM
reg[ROM_WIDTH-1:0]rom_r;
reg[ROM_WIDTH-1:0]rom_r;// SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_linear_wr.rom_r_reg[8] is unused and will be removed from module cmd_encod_linear_wr.
wirepre_done;
wirepre_done;
wire[1:0]rom_cmd;
wire[1:0]rom_cmd;
wire[1:0]rom_skip;
wire[1:0]rom_skip;
...
@@ -103,7 +103,7 @@ module cmd_encod_linear_wr #(
...
@@ -103,7 +103,7 @@ module cmd_encod_linear_wr #(
regdual_write;// Two bursts have to be written
regdual_write;// Two bursts have to be written
regfew_write;//write 1,2 or 3 bursts
regfew_write;//write 1,2 or 3 bursts
wirewrite_addr_w;// gen_addr that generates write commands
wirewrite_addr_w;// gen_addr that generates write commands
reg[ROM_DEPTH-1:0]jump_gen_addr;// will overrun as stop comes from ROM
reg[ROM_DEPTH-1:0]jump_gen_addr;// will overrun as stop comes from ROM SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_linear_wr.jump_gen_addr_reg[0] is unused and will be removed from module cmd_encod_linear_wr.
inputkeep_open_in,// keep banks open (for <=8 banks only
inputkeep_open_in,// keep banks open (for <=8 banks only
inputskip_next_page_in,// do not reset external buffer (continue)
inputskip_next_page_in,// do not reset external buffer (continue)
inputstart,// start generating commands
inputstart,// start generating commands
outputreg[31:0]enc_cmd,// encoded commnad
outputreg[31:0]enc_cmd,// encoded command SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_32_rd.enc_cmd_reg[11:9,7:5,2] is unused and will be removed from module cmd_encod_tiled_32_rd.
reg[COLADDR_NUMBER-4:0]col;// start memory column in 8-bursts
reg[COLADDR_NUMBER-4:0]col;// start memory column in 8-bursts SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_32_rd.col_reg[0] is unused and will be removed from module cmd_encod_tiled_32_rd.
reg[2:0]bank;// memory bank;
reg[2:0]bank;// memory bank;
reg[5:0]num_rows_m1;// number of rows in a tile minus 1
reg[5:0]num_rows_m1;// number of rows in a tile minus 1
reg[5:0]num_cols128_m2;// number of r16-byte columns in a tile -2 (even columns)
reg[5:0]num_cols128_m2;// number of r16-byte columns in a tile -2 (even columns) SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_32_rd.num_cols128_m2_reg[0] is unused and will be removed from module cmd_encod_tiled_32_rd.
// reg [FULL_ADDR_NUMBER-4:0] rowcol_inc; // increment {row.col} when bank rolls over, remove 3 LSBs (in 8-bursts)
// reg [FULL_ADDR_NUMBER-4:0] rowcol_inc; // increment {row.col} when bank rolls over, remove 3 LSBs (in 8-bursts)
reg[FRAME_WIDTH_BITS:0]rowcol_inc;// increment {row.col} when bank rolls over, remove 3 LSBs (in 8-bursts)
reg[FRAME_WIDTH_BITS:0]rowcol_inc;// increment {row.col} when bank rolls over, remove 3 LSBs (in 8-bursts)
reg[5:0]scan_row;// current row in a tile (valid @pre_act)
reg[5:0]scan_row;// current row in a tile (valid @pre_act)
reg[5:0]scan_col;// current 16-byte column in a tile (valid @pre_act)
reg[5:0]scan_col;// current 16-byte column in a tile (valid @pre_act) SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_32_rd.scan_col_reg[0] is unused and will be removed from module cmd_encod_tiled_32_rd.
regstart_d;// start, delayed by 1 clocks
regstart_d;// start, delayed by 1 clocks
wirelast_row;
wirelast_row;
reg[FULL_ADDR_NUMBER-1:0]row_col_bank;// RA,CA, BA - valid @pre_act;
reg[FULL_ADDR_NUMBER-1:0]row_col_bank;// RA,CA, BA - valid @pre_act;
inputkeep_open_in,// keep banks open (for <=8 banks only
inputkeep_open_in,// keep banks open (for <=8 banks only
inputskip_next_page_in,// do not reset external buffer (continue)
inputskip_next_page_in,// do not reset external buffer (continue)
inputstart,// start generating commands
inputstart,// start generating commands
outputreg[31:0]enc_cmd,// encoded commnad
outputreg[31:0]enc_cmd,// encoded command SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_rd.enc_cmd_reg[11:9,7:5,2] is unused and will be removed from module cmd_encod_tiled_rd.
inputkeep_open_in,// keep banks open (for <=8 banks only
inputkeep_open_in,// keep banks open (for <=8 banks only
inputskip_next_page_in,// do not reset external buffer (continue)
inputskip_next_page_in,// do not reset external buffer (continue)
inputstart,// start generating commands
inputstart,// start generating commands
outputreg[31:0]enc_cmd,// encoded commnad
outputreg[31:0]enc_cmd,// encoded command SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_wr.enc_cmd_reg[11,9,6,4:3,1] is unused and will be removed from module cmd_encod_tiled_wr.
outputregenc_wr,// write encoded command
outputregenc_wr,// write encoded command
outputregenc_done// encoding finished
outputregenc_done// encoding finished
);
);
...
@@ -107,7 +107,7 @@ module cmd_encod_tiled_wr #(
...
@@ -107,7 +107,7 @@ module cmd_encod_tiled_wr #(
// reg gen_run_d; // to output "done"?
// reg gen_run_d; // to output "done"?
reg[ROM_DEPTH-1:0]gen_addr;// will overrun as stop comes from ROM
reg[ROM_DEPTH-1:0]gen_addr;// will overrun as stop comes from ROM
reg[ROM_WIDTH-1:0]rom_r;
reg[ROM_WIDTH-1:0]rom_r;// SuppressThisWarning VivadoSynthesis: [Synth 8-3332] Sequential element cmd_encod_tiled_wr.rom_r_reg[8,0] is unused and will be removed from module cmd_encod_tiled_wr.
wirepre_done;
wirepre_done;
wire[1:0]rom_cmd;
wire[1:0]rom_cmd;
wire[1:0]rom_skip;
wire[1:0]rom_skip;
...
@@ -153,7 +153,7 @@ module cmd_encod_tiled_wr #(
...
@@ -153,7 +153,7 @@ module cmd_encod_tiled_wr #(
assignpre_done=rom_r[ENC_PRE_DONE]&&gen_run;
assignpre_done=rom_r[ENC_PRE_DONE]&&gen_run;
assignrom_cmd=rom_r[ENC_CMD_SHIFT+:2];// & {enable_act,1'b1}; // disable bit 1 if activate is disabled (not the first column)
assignrom_cmd=rom_r[ENC_CMD_SHIFT+:2];// & {enable_act,1'b1}; // disable bit 1 if activate is disabled (not the first column)
